CN111063677A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN111063677A
CN111063677A CN201910739955.1A CN201910739955A CN111063677A CN 111063677 A CN111063677 A CN 111063677A CN 201910739955 A CN201910739955 A CN 201910739955A CN 111063677 A CN111063677 A CN 111063677A
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Prior art keywords
package
package substrate
semiconductor
semiconductor chip
interposer
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Pending
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CN201910739955.1A
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English (en)
Inventor
李章雨
姜芸炳
金知晃
沈钟辅
池永根
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN111063677A publication Critical patent/CN111063677A/zh
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Abstract

一种半导体封装件，包括：第一封装基板；位于第一封装基板上的第一半导体芯片；将第一封装基板连接到第一半导体芯片的多个第一芯片连接单元；位于第一半导体芯片上的中介层，该中介层在平行于第一封装基板的上表面的方向上的宽度大于第一半导体芯片在平行于第一封装基板的上表面的方向上的宽度；以及上填充层，其包括位于第一半导体芯片和中介层之间的中心部分和围绕中心部分的外部部分，外部部分在垂直于第一封装基板的上表面的方向上的厚度大于中心部分在垂直于第一封装基板的上表面的方向上的厚度。

Description

半导体封装件
相关申请的交叉引用
本申请要求于2018年10月16日向韩国知识产权局提交的申请号为10-2018-0123270的韩国专利申请的优先权，其公开内容通过引用整体并入本文。
技术领域
示例实施例涉及半导体封装件，更具体地，涉及封装叠层。
背景技术
为了满足小型化和高度集成半导体封装件的需要，已经开发了封装叠层。封装叠层具有一个子封装件堆叠在另一个子封装件上的结构。因此，封装叠层可占据小面积并且可使半导体封装件小型化和高度集成。
发明内容
根据实施例的一个方面，提供了一种半导体封装件，包括：第一封装基板；位于第一封装基板上的第一半导体芯片；将第一封装基板连接到第一半导体芯片的多个第一芯片连接单元；位于第一半导体芯片上的中介层，该中介层在平行于第一封装基板的上表面的方向上的宽度大于第一半导体芯片在平行于第一封装基板的上表面的方向上的宽度；以及上填充层，其包括位于第一半导体芯片和中介层之间的中心部分和围绕中心部分的外部部分，外部部分在垂直于第一封装基板的上表面的方向上的厚度大于中心部分在垂直于第一封装基板的上表面的方向上的厚度。
根据实施例的另一方面，提供了一种半导体封装件，包括：第一封装基板；位于第一封装基板上的第一半导体芯片；将第一封装基板连接到第一半导体芯片的多个第一芯片连接单元；位于第一半导体芯片上的中介层，该中介层在平行于第一封装基板的上表面的方向上的宽度大于第一半导体芯片在平行于第一封装基板的上表面的方向上的宽度；上填充层，其填充中介层与第一半导体芯片之间的空间；以及下填充层，其包括填充第一半导体芯片和第一封装基板之间的空间的中心部分和围绕所述中心部分的外部部分，并且下填充层的外部部分在垂直于第一封装基板的上表面的方向上的厚度大于下填充层的中心部分在垂直于第一封装基板的上表面的方向上的厚度。
根据实施例的又一方面，提供了一种半导体封装件，包括：第一子封装件和第二子封装件，第一子封装件包括第一封装基板、第一封装基板上的第一半导体芯片、第一封装基板和第一半导体芯片之间的多个第一芯片连接单元、第一半导体芯片上的中介层、填充中介层和第一半导体芯片之间的空间的上填充层以及填充第一半导体芯片和第一封装基板之间的空间的下填充层，中介层在平行于第一封装基板的上表面的方向上的宽度大于第一半导体芯片在平行于第一封装基板的上表面的方向上的宽度，第二子封装包括位于中介层上的多个封装间连接单元、位于多个封装间连接单元上的第二封装基板、位于第二封装基板上的至少一个第二半导体芯片以及围绕至少一个第二半导体芯片并覆盖第二封装基板的上表面的第二模塑单元，其中，上填充层和下填充层中的至少一个与第一半导体芯片的侧壁接触。
附图说明
通过参照附图详细描述示例性实施例，特征对于本领域技术人员将变得显而易见，其中：
图1A示出了根据实施例的半导体封装件的截面图；
图1B示出了根据实施例的半导体封装件的截面图；
图1C示出了根据实施例的半导体封装件的截面图；
图2示出了根据实施例的半导体封装件的截面图；
图3示出了根据实施例的半导体封装件的截面图；
图4示出了根据实施例的半导体封装件的截面图；
图5示出了根据实施例的半导体封装件的截面图；
图6A示出了根据实施例的半导体封装件中包括的第一封装基板的平面图；
图6B示出了根据实施例的半导体封装件中包括的第一封装基板的平面图；
图6C示出了根据实施例的半导体封装件中包括的第一封装基板的平面图；
图7示出了根据实施例的半导体封装件的截面图；
图8示出了根据实施例的半导体封装件的截面图；
图9示出了根据实施例的半导体封装件的截面图；
图10示出了根据实施例的半导体封装件的截面图；
图11示出了根据实施例的半导体封装件的截面图；
图12A至图12D示出了根据实施例的制造半导体封装件的方法中的阶段的截面图；
图13示出了根据实施例的制造半导体封装件的方法的截面图；
图14示出了根据实施例的制造半导体封装件的方法的截面图；
图15示出了根据实施例的制造半导体封装件的方法的截面图；
图16A和图16B示出了根据实施例的制造半导体封装件的方法中的阶段的截面图；
图17示出了根据实施例的制造半导体封装件的方法的截面图；
图18A和图18B示出了根据实施例的制造半导体封装件的方法中的阶段的截面图；以及
图19A至图19C示出了根据实施例的制造半导体封装件的方法中的阶段的截面图。
具体实施方式
图1A是示出根据实施例的半导体封装件1000a的截面图。
参照图1A，半导体封装件1000a可以包括第一子封装件SP1和第二子封装件SP2。第二子封装件SP2可以堆叠在第一子封装件SP1上。例如，半导体封装件1000a可以是封装叠层。
第一子封装件SP1可以包括第一封装基板110、第一半导体芯片120、多个第一芯片连接单元130、中介层(interposer)140、上填充层150a、多条导线170以及第一模塑单元180。
第一封装基板110可以是印刷电路板(PCB)。PCB可以是刚性PCB或柔性PCB。第一封装基板110可以包括基板基底层、多个下连接焊盘、多个上连接焊盘、多条导电布线、多个通孔以及阻焊层。
第一封装基板110中的基板基底层可包括例如酚醛树脂、环氧树脂、聚酰亚胺树脂或其组合。例如，基板基底层可包括阻燃剂4(FR4)、四官能环氧树脂、聚苯醚、环氧/聚苯醚、双马来酰亚胺三嗪(BT)、聚醯胺短纤席材(thermount)、氰酸酯、聚酰亚胺或液晶聚合物。在一些实施例中，第一封装基板110可以是多层PCB，其中基板基底层配置有多个层。
第一封装基板110中的多个下连接焊盘可以设置在基板基底层的下表面上，并且多个上连接焊盘可以设置在基板基底层的上表面上。多个下连接焊盘可以连接到多个外部连接单元190，并且多个上连接焊盘可以连接到多个第一芯片连接单元130和多条导线170。多个下连接焊盘和多个上连接焊盘可各自包括例如铜(Cu)、镍(Ni)、铝(Al)、银(Ag)、金(Au)或其组合。
第一封装基板110中的多条导电布线和多个通孔可以设置在基板基底层中和基板基底层的表面上。多条导电布线和多个通孔可以连接多个下连接焊盘和多个上连接焊盘。多条导电布线和多个通孔可各自包括例如Cu、Ni、Al、Ag、Au或其组合。
第一封装基板110的阻焊层可以设置在基板基底层的上表面和下表面中的每一个上。然而，阻焊层可以不覆盖多个上连接焊盘和多个下连接焊盘。
第一半导体芯片120可以设置在第一封装基板110上。第一半导体芯片120可以在平行于第一封装基板110的上表面的方向(例如，在Y方向)上具有第一宽度W1。第一半导体芯片120可以是逻辑芯片或存储器芯片。逻辑芯片可以是，例如，存储器控制器芯片、中央处理单元(CPU)芯片、图形处理单元(GPU)芯片或应用处理器(AP)芯片。存储器芯片可以是，例如动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、闪存芯片、电可擦除可编程只读存储器(EEPROM)芯片、相变随机存取存储器(PRAM)芯片、磁随机存取存储器(MRAM)芯片或电阻随机存取存储器(RRAM)芯片。
多个第一芯片连接单元130可以将第一半导体芯片120连接到第一封装基板110。多个第一芯片连接单元130可以是，例如，多个凸块。在这种情况下，多个第一芯片连接单元130可以设置在第一半导体芯片120和第一封装基板110之间。多个第一芯片连接单元130可以各自包括例如Au、Cu、Ni、锡(Sn)、铅(Pb)或其组合。
中介层140可以设置在第一半导体芯片120上，例如，第一半导体芯片120可以相对于中介层140居中。中介层140可以将第一封装基板110连接到第二封装基板210。中介层140可以在平行于第一封装基板110的上表面的方向(例如，在Y方向)上具有第二宽度W2。中介层140的第二宽度W2可以大于第一半导体芯片120的第一宽度W1，例如，中介层140可以在第一半导体芯片120的每一侧上方悬垂。
中介层140可以包括中介层基底、多个连接焊盘140U和多条导电布线。中介层基底可包括，例如，有机材料、玻璃、陶瓷或半导体。中介层基底可包括例如硅(Si)。多个连接焊盘140U可以设置在中介层基底的上表面上。多条导电布线可以连接多个连接焊盘140U。多个连接焊盘140U和多条导电布线可各自包括例如Cu，Ni，Al，Ag，Au或其组合。
上填充层150a可以设置在第一封装基板110和中介层140之间。上填充层150a可以与第一封装基板110间隔开。上填充层150a可以接触中介层140的下表面和第一半导体芯片120的上表面，例如，上填充层150a可以接触中介层140的整个下表面和第一半导体芯片120的整个上表面。在一些实施例中，上填充层150a可以接触第一半导体芯片120的全部上表面和中介层140的全部下表面。上填充层150a可以接触第一半导体芯片120的侧壁以覆盖第一半导体芯片120的侧壁。上填充层150a可以在平行于第一封装基板110的上表面的方向(例如，在Y方向)上具有第三宽度W3。在一些实施例中，上填充层150a的第三宽度W3可以与中介层140的第二宽度W2相同。例如，如图1A所示，可以沿着上填充层150a的顶表面测量上填充层150a的第三宽度W3。
上填充层150a可包括中心部分P1a和外部部分P2a。上填充层150a的中心部分P1a和外部部分P2a可以提供作为一个(例如)整体，例如，作为由相同材料同时形成的单个无缝单元。例如，上填充层150a的中心部分P1a可以是(例如，完全)填充第一半导体芯片120和中介层140之间的空间的部分。例如，上填充层150a的外部部分P2a可以是从中心部分P1a延伸并且在中心部分P1a周边的部分，例如，从中心部分P1a沿着中介层140的底表面的其余部分并且沿着第一半导体芯片120的整个侧壁延伸。
上填充层150a的中心部分P1a可以设置在第一半导体芯片120和中介层140之间，并且可以接触第一半导体芯片120的上表面和中介层140的下表面。上填充层150a的外部部分P2a可以围绕例如中心部分P1a的整个周边，并且可以接触中介层140的下表面。在一些实施例中，上填充层150a的外部部分P2a可以接触第一半导体芯片120的侧壁以覆盖第一半导体芯片120的侧壁。在一些实施例中，上填充层150a的外部部分P2a的下表面和第一半导体芯片120的下表面可以设置在相同的水平，例如，彼此相同的水平。例如，在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上，上填充层150a的外部部分P2a的下表面距离第一封装基板110的高度可以与在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上，第一半导体芯片120的下表面距离第一封装基板110的高度相同。
上填充层150a的中心部分P1a在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上可以具有第一厚度T1，上填充层150a的外部部分P2a在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上可以具有第二厚度T2。第二厚度T2可以大于第一厚度T1。上填充层150a的悬垂在第一半导体芯片120上的外部部分P2a的厚度可以大于上填充层150a的中心部分P1a的厚度，从而防止中介层140的悬垂部分发生偏转。
上填充层150a可包括片上薄膜(FOD)或粘片膜(DAF)。例如，可以通过固化FOD或DAF形成上填充层150a。上填充层150a可包括，例如，环氧基有机材料。
多条导线170可以将中介层140连接到第一封装基板110。多条导线170可以，例如，从中介层140的上表面延伸到第一封装基板110的上表面。多条导线170可各自包括例如Au、Cu、Ag、Al或其组合。
第一模塑单元180可以围绕第一半导体芯片120、多个第一芯片连接单元130、多条导线170、上填充层150a和中介层140，并且可以覆盖第一封装基板110的上表面。例如，如图1A所示，第一模塑单元180可以围绕具有上填充层150a的中介层140的整个周边，并且可以填充上填充层150a的底表面与第一封装基板110的顶表面之间的空间，以及相邻的第一芯片连接单元130之间的空间。
第一模塑单元180可包括暴露中介层140的多个连接焊盘140U的多个开口，以使封装间连接单元290接触中介层140。第一模塑单元180可包括，例如，热固性树脂、热塑性树脂、紫外线(UV)固化树脂或其组合。第一模塑单元180可包括，例如，环氧树脂、硅树脂或其组合。第一模塑单元180可包括例如环氧树脂模塑料(EMC)。
半导体封装件1000a还可以包括外部连接单元190。外部连接单元190可以设置在第一封装基板110的下表面上。外部连接单元190可以将半导体封装件1000a连接到外部电路。外部连接单元190可以包括例如Au、Cu、Ni、Sn、Pb或其组合。外部连接单元190可以包括例如焊球。
第二子封装件SP2可以包括第二封装基板210、至少一个第二半导体芯片220、粘合剂层230、多个第二芯片连接单元270、第二模塑单元280和封装间连接单元290。
第二封装基板210可以是PCB。第二封装基板210可以设置在第一子封装件SP1的上方，例如，与第一子封装件SP1的顶部重叠。
至少一个第二半导体芯片220可以设置在第二封装基板210上，例如，第二封装基板210可以位于至少一个第二半导体芯片220和第一子封装件SP1之间。第二半导体芯片220可以是逻辑芯片或存储器芯片。在一些实施例中，第二半导体芯片220可以是种类不同于第一半导体芯片120的半导体芯片。例如，第二半导体芯片220可以是存储器芯片，并且第一半导体芯片120可以是逻辑芯片。在图1A中，示出了四个第二半导体芯片220。然而，第二子封装件SP2中包括的第二半导体芯片220的数量不限于四个，而是可以进行各种改变。在一些实施例中，两个或更多个第二半导体芯片220可以在竖直方向(例如，在Z方向)上堆叠在彼此顶部上。在一些实施例中，两个或更多个第二半导体芯片220可以在水平方向上(例如，在XY平面中)设置在第二封装基板210上，并且可以，例如，在X方向和/或Y方向上彼此间隔开。
通过使用粘合剂层230，第二半导体芯片220可以附接在第二封装基板210上，例如，并且/或者附接到另一个第二半导体芯片220的底部。粘合剂层230可以包括例如，DAF、非导电膜(NCF)或非导电膏(NCP)。
多个第二芯片连接单元270可以将第二半导体芯片220连接到第二封装基板210。多个第二芯片连接单元270中的每一个可以是，例如，导线。多个第二芯片连接单元270可各自包括例如Au、Cu、Ag、Al或其组合。
第二模塑单元280可以围绕第二半导体芯片220和多个第二芯片连接单元270，并且可以覆盖第二封装基板210的上表面。第二模塑单元280可以包括，例如，热固性树脂、热塑性树脂、UV固化树脂或其组合。第二模塑单元280可包括，例如，环氧树脂、硅树脂或其组合。第二模塑单元280可包括例如EMC。
多个封装间连接单元290可以设置在第二封装基板210的下表面和中介层140之间。多个封装间连接单元290可以分别设置在第一模塑单元180中包括的开口中。多个封装间连接单元290可以分别接触被第一模塑单元180暴露的中介层140的多个连接焊盘140U。多个封装间连接单元290可以将第一子封装件SP1连接到第二子封装件SP2。多个封装间连接单元290中的每一个可包括例如Au、Cu、Ni、Sn、Pb或其组合。多个封装间连接单元290中的每一个可包括例如焊球。
在根据实施例的半导体封装件1000a中，与上填充层150a的中心部分P1a相比，上填充层150a的外部部分P2a可以在沿着第一封装基板110的法线的方向上实质上更厚。由于上填充层150a的外部部分P2a的厚度相对较大，因此外部部分P2a可以充分支撑中介层140的悬垂在第一半导体芯片120上的边缘部分，从而防止或实质上减小中介层140的边缘部分朝向第一封装基板110的偏转(例如，弯曲)。
图1B是示出根据实施例的半导体封装件1000b的截面图。在下文中，将描述图1B中所示的半导体封装件1000b与图1A中所示的半导体封装件1000a之间的差异。
参照图1B，半导体封装件1000b可以包括第一子封装件SP1b和第二子封装件SP2。也就是说，半导体封装件1000b可以包括第一子封装件SP1b，而不是图1A所示的半导体封装件1000a的第一子封装件SP1。
具体地，如图1B所示，第一子封装件SP1b可以包括上填充层150b，而不是图1A中所示的第一子封装件SP1中包括的上填充层150a。上填充层150b可包括中心部分P1b和外部部分P2b。上填充层150b的外部部分P2b可以，例如，仅覆盖第一半导体芯片120的侧壁的一部分。上填充层150b的外部部分P2b的下表面可以设置在，例如，相对于第一封装基板110的顶表面，比第一半导体芯片120的下表面的位置高的水平处。也就是说，上填充层150b的外部部分P2b的下表面在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上距离第一封装基板110的上表面的高度可以大于第一半导体芯片120的下表面在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上距离第一封装基板110的上表面的高度。
图1C是示出根据实施例的半导体封装件1000c的截面图。在下文中，将描述图1C中所示的半导体封装件1000c与图1A中所示的半导体封装件1000a之间的差异。
参照图1C，半导体封装件1000c可以包括第一子封装件SP1c和第二子封装件SP2。也就是说，半导体封装件1000c可以包括第一子封装件SP1c，而不是图1A所示的半导体封装件1000a的第一子封装件SP1。
具体地，如图1C所示，第一子封装件SP1c可以包括上填充层150c，而不是图1A中所示的第一子封装件SP1中包括的上填充层150a。上填充层150c可包括中心部分P1c和外部部分P2c。上填充层150c的外部部分P2c的下表面可以设置在，例如，相对于第一封装基板110的顶表面，比第一半导体芯片120的下表面的位置低的水平处。也就是说，上填充层150c的外部部分P2c的下表面在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上距离第一封装基板110的上表面的高度可以小于第一半导体芯片120的下表面在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上距离第一封装基板110的上表面的高度。然而，上填充层150c的外部部分P2c可以与第一封装基板110间隔开。
图2是示出根据实施例的半导体封装件2000的截面图。在下文中，将描述图2中所示的半导体封装件2000与图1A中所示的半导体封装件1000a之间的差异。
参照图2，半导体封装件2000可以包括第一子封装件SP1和第二子封装件SP2d。也就是说，半导体封装件2000可以包括第二子封装件SP2d，而不是图1A所示的半导体封装件1000a的第二子封装件SP2。
具体地，如图2所示，在第二子封装件SP2d中，多个半导体芯片220可以通过第二芯片连接单元270d而不是图1A所示的第二子封装件SP2中包括的第二芯片连接单元270连接到第二封装基板210。第二芯片连接单元270d可以包括多个硅通孔(TSV)271和多个凸块273。多个TSV 271可以设置在多个半导体芯片220中的每一个中。在一些实施例中，多个TSV271可以不设置在堆叠的多个第二半导体芯片220的最上面的第二半导体芯片220中。多个TSV 271中的每一个可以包括硅(Si)。多个凸块273中的每一个可以设置在多个第二半导体芯片220中两个相邻的第二半导体芯片220之间。每个凸块273可以连接到对应的TSV 271。在一些实施例中，可以在凸块273中的每一个与对应的TSV 271之间设置将对应的凸块273连接到对应的TSV 271的布线层。可以在凸块273中的每一个与对应的TSV 271之间进一步设置绝缘层。
第二模塑单元280d可以围绕第二半导体芯片220并且可以覆盖第二封装基板210的上表面。第二模塑单元280d可以覆盖第二封装基板210的上表面和第二半导体芯片220的侧表面。在一些实施例中，如图2所示，第二模塑单元280d可以覆盖堆叠的多个第二半导体芯片220的最上面的第二半导体芯片220的上表面。在其他实施例中，与图2不同，第二模塑单元280d可以不覆盖堆叠的多个第二半导体芯片220的最上面的第二半导体芯片220的上表面。第二模塑单元280d的上表面和堆叠的多个第二半导体芯片220的最上面的第二半导体芯片220的上表面可以设置在相同的平面上。
在一些实施例中，散热构件可以附接在堆叠的多个第二半导体芯片220的最上面的第二半导体芯片220的上表面上。热界面材料(TIM)层可以设置在堆叠的多个第二半导体芯片220的最上面的第二半导体芯片220的上表面与散热构件之间。
图3是示出根据实施例的半导体封装件3000的截面图。在下文中，将描述图3中所示的半导体封装件3000与图1A中所示的半导体封装件1000a之间的差异。
参照图3，半导体封装件3000可以包括第一子封装件SP1e和第二子封装件SP2。也就是说，半导体封装件3000可以包括第一子封装件SP1e，而不是图1A所示的半导体封装件1000a的第一子封装件SP1。
具体地，如图3所示，第一子封装件SP1e可以包括上填充层150e，而不是图1A中所示的第一子封装件SP1中包括的上填充层150a。上填充层150e可包括中心部分P1e和外部部分P2e。上填充层150e的外部部分P2e可以不覆盖第一半导体芯片120的侧壁的至少一部分。在一些实施例中，上填充层150e的外部部分P2e可以不覆盖第一半导体芯片120的侧壁。在其他实施例中，上填充层150e的外部部分P2e可以覆盖第一半导体芯片120的侧壁的上部，并且可以不覆盖第一半导体芯片120的侧壁的下部。
例如，如图3所示，上填充层150e的外部部分P2e可以沿着中介层140的底部延伸，而不沿第一半导体芯片120的侧壁的整体延伸，例如，外部部分P2e的面对第一半导体芯片120的侧壁的侧壁可以远离第一半导体芯片120倾斜。例如，上填充层150e的外部部分P2e可以包括在越靠近第一封装基板110的方向上越远离第一半导体芯片120延伸的，例如，面对第一半导体芯片120的内壁。也就是说，随着距第一封装基板110的距离减小，内壁和第一半导体芯片120之间在Y方向上的距离可以增加。内壁可以在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上倾斜。
图4是示出根据实施例的半导体封装件4000的截面图。在下文中，将描述图4中所示的半导体封装件4000与图1A中所示的半导体封装件1000a之间的差异。
参照图4，半导体封装件4000可以包括第一子封装件SP1f和第二子封装件SP2。也就是说，半导体封装件4000可以包括第一子封装件SP1f，而不是图1A所示的半导体封装件1000a的第一子封装件SP1。
具体地，如图4所示，第一子封装件SP1f可以包括第一芯片连接单元130f，而不是图1A中所示的第一子封装件SP1中包括的第一芯片连接单元130。第一芯片连接单元130f可以将第一半导体芯片120连接到第一封装基板110。第一芯片连接单元130f可以是，例如，导线。在这种情况下，第一芯片连接单元130f可以在第一半导体芯片120的上表面和第一封装基板110的上表面之间延伸。在一些实施例中，上填充层150a可以与第一封装基板110间隔开而不与第一封装基板110接触，并且第一芯片连接单元130f的一部分可以设置在上填充层150a中。例如，第一芯片连接单元130f的上部可以设置在上填充层150a中，并且第一芯片连接单元130f的下部可以设置在第一模塑单元180中。在一些其他实施例中，上填充层150a可以接触第一封装基板110并且可以完全围绕第一芯片连接单元130f。
图5是示出根据实施例的半导体封装件5000的截面图。在下文中，将描述图5中所示的半导体封装件5000与图1A中所示的半导体封装件1000a之间的差异。
参照图5，半导体封装件5000可以包括第一子封装件SP1g和第二子封装件SP2。也就是说，半导体封装件5000可以包括第一子封装件SP1g，而不是图1A所示的半导体封装件1000a的第一子封装件SP1。
具体地，如图5所示，第一子封装件SP1g可以包括第一封装基板110a，而不是图1A所示的第一子封装件SP1中包括的第一封装基板110。第一封装基板110a可以包括：包括平坦的上表面的基底部分111；以及突起115，其在垂直于基底部分111的上表面的方向(例如，在Z方向)上突起，例如，突起115可以从基底部分111的上表面向上延伸，以接触上填充层150a的底部。突起115可以是阻焊坝。突起115的至少一部分可以包括第一封装基板110a的阻焊层的一部分。突起115可以在平行于第一封装基板110a的上表面的方向(例如，在Y方向)上具有第四宽度W4。突起115可以具有在垂直于第一封装基板110a的上表面的方向(例如，在Z方向)上距离基底部分111的上表面的高度H。在一些实施例中，突起115的第四宽度W4可以大于突起115的高度H。当突起115的第四宽度W4大于突起115的高度H时，可以加宽由突起115支撑的上填充层150a的区域，并且因此，可以有效地防止由上填充层150a支撑的中介层140的悬垂部分的偏转。
上填充层150a可以接触第一封装基板110a的突起115。具体地，上填充层150a的外部部分P2a可以接触第一封装基板110a的突起115。也就是说，上填充层150a可以由第一封装基板110a的突起115支撑。因此，中介层140的悬垂在第一半导体芯片120上的部分可以由上填充层150a的外部部分P2a和突起115支撑，因此，可以有效地防止中介层140的悬垂在第一半导体芯片120上的部分的偏转。
图6A是根据实施例的半导体封装件中包括的第一封装基板110a的平面图。参照图6A，第一封装基板110a可以包括突起115。从上方看，第一封装基板110a的突起115可以形成闭环形状，以具有一定的(例如，恒定的)宽度W4。在一些实施例中，如从上方所见，第一封装基板110a的突起115可以包括四边形上表面，并且该突起115可以具有四边形环形状。
图6B是根据实施例的半导体封装件中包括的第一封装基板110b的平面图。图5中所示的半导体封装件5000可以包括图6B中所示的第一封装基板110b，而不是图6A中所示的第一封装基板110a。
参照图6B，第一封装基板110b可以包括多个突起115b。多个突起115b可以沿切割环设置并且可以彼此间隔开。多个突起115b中的每一个可大致具有长方体形状，但不限于此。
图6C是根据实施例的半导体封装件中包括的第一封装基板110c的平面图。图5中所示的半导体封装件5000可以包括图6C中所示的第一封装基板110c，而不是图6A中所示的第一封装基板110a。
参照图6C，第一封装基板110c可以包括多个突起115c。多个突起115c可以彼此间隔开。多个突起115c中的每一个可以与第一封装基板110c的上表面的边缘中的对应的边缘相邻，并且可以在平行于对应的边缘的方向上延伸。例如，第一封装基板110c的上表面可以包括在Y方向延伸并且彼此相对的第一边缘E1和第二边缘E2，以及在X方向延伸并且彼此相对的第三边缘E3和第四边缘E4。多个突起115c中的一个可以在Y方向上延伸，并且与第二边缘E2相比，可以更靠近第一边缘E1。多个突起115c中的另一个突起可以在Y方向上延伸，并且与第一边缘E1相比，可以更靠近第二边缘E2。多个突起115c中的另一个突起可以在X方向上延伸，并且与第四边缘E4相比，可以更靠近第三边缘E3。多个突起115c中的另一个突起可以在X方向上延伸，并且与第三边缘E3相比，可以更靠近第四边缘E4。例如，如图6C所示，多个突起115c可以是彼此间隔的四个突起并且(在俯视图中)布置成矩形形状，但是实施例不限于此。
图7是示出根据实施例的半导体封装件7000的截面图。在下文中，将描述图7中所示的半导体封装件7000与图1A中所示的半导体封装件1000a之间的差异。
参照图7，半导体封装件7000可以包括第一子封装件SP1h和第二子封装件SP2。也就是说，半导体封装件7000可以包括第一子封装件SP1h，而不是图1A所示的半导体封装件1000a的第一子封装件SP1。
具体地，如图7所示，与图1A中所示的第一子封装件SP1不同，第一子封装件SP1h还可以包括下填充层160。下填充层160可以布置在第一半导体芯片120和第一封装基板110之间并且可以围绕多个第一芯片连接单元130。下填充层160可以包括例如DAF、底部填充物、NCF或NCP。下填充层160可包括例如环氧基有机材料。
图8是示出根据实施例的半导体封装件8000的截面图。在下文中，将描述图8中所示的半导体封装件8000与图7中所示的半导体封装件7000之间的差异。
参照图8，半导体封装件8000可以包括第一子封装件SP1i和第二子封装件SP2。也就是说，半导体封装件8000可以包括第一子封装件SP1i，而不是图7所示的半导体封装件7000的第一子封装件SP1h。
具体地，如图8所示，第一子封装件SP1i可以包括上填充层150i，而不是图7中所示的第一子封装件SP1h中包括的上填充层150a。上填充层150i可包括外部部分P2i和中心部分P1i。上填充层150i的中心部分P1i可以设置在第一半导体芯片120和中介层140之间。上填充层150i的外部部分P2i可以围绕中心部分P1i并且可以接触中介层140的下表面、下填充层160、第一半导体芯片120的侧壁以及第一封装基板110。
由于上填充层150i的外部部分P2i接触第一封装基板110，因此上填充层150i的外部部分P2i可以由第一封装基板110支撑。因此，中介层140的悬垂在第一半导体芯片120上的部分可以由第一封装基板110和上填充层150i的外部部分P2i支撑。因此，可以防止中介层140的悬垂部分的偏转或基本上使其最小化。
图9是示出根据实施例的半导体封装件9000的截面图。在下文中，将描述图9中所示的半导体封装件9000与图8中所示的半导体封装件8000之间的差异。
参照图9，半导体封装件9000可以包括第一子封装件SP1j和第二子封装件SP2。也就是说，半导体封装件9000可以包括第一子封装件SP1j，而不是图8所示的半导体封装件8000的第一子封装件SP1i。
具体地，如图9所示，第一子封装件SP1j可以包括下填充层160j，而不是图8中所示的第一子封装件SP1i中包括的下填充层160。下填充层160j可以接触第一半导体芯片120的侧壁的至少一部分。例如，下填充层160j可以接触第一半导体芯片120的侧壁的下部。在一些实施例中，下填充层160j的侧壁可以在从第一封装基板110和第一半导体芯片120之间的空间2到外部的方向上凸出地突起。
图10是示出根据实施例的半导体封装件10000的截面图。在下文中，将描述图10中所示的半导体封装件10000与图8中所示的半导体封装件8000之间的差异。
参照图10，半导体封装件10000可以包括第一子封装件SP1k和第二子封装件SP2。也就是说，半导体封装件10000可以包括第一子封装件SP1k，而不是图8所示的半导体封装件8000的第一子封装件SP1i。
具体地，如图10所示，第一子封装件SP1k可以包括下填充层160k和上填充层150k，而不是图8中第一子封装件SP1i中包括的下填充层160和上填充层150i。下填充层160k可包括中心部分P3k和外部部分P4k。下填充层160k的中心部分P3k可以设置在第一半导体芯片120和第一封装基板110之间。下填充层160k的外部部分P4k可以围绕中心部分P3k并且可以接触第一封装基板110的上表面和第一半导体芯片120的侧壁。下填充层160k的外部部分P4k可以覆盖第一半导体芯片120的整个侧壁。下填充层160k的外部部分P4k的上表面和第一半导体芯片120的上表面可以共面。
下填充层160k可以在平行于第一封装基板110的上表面的方向(例如，在Y方向)上具有第五宽度W5。在一些实施例中，下填充层160k的第五宽度W5可以与中介层140的第二宽度W2相同。在一些其他实施例中，下填充层160k的第五宽度W5可以大于中介层140的第二宽度W2。下填充层160k的宽度W5可以小于中介层140的第二宽度W2。
下填充层160k的中心部分P3k可以在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上具有第三厚度T3，下填充层160k的外部部分P4k可以在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上具有第四厚度T4。下填充层160k的中心部分P3k的第三厚度T3可以小于下填充层160k的外部部分P4k的第四厚度T4。
上填充层150k可以不覆盖第一半导体芯片120的侧壁。上填充层150k可以包括中心部分P1k和外部部分P2k。上填充层150k的中心部分P1k可以设置在第一半导体芯片120和中介层140之间。上填充层150k的外部部分P2k可以围绕上填充层150k的中心部分P1k并且可以接触中介层140的下表面和下填充层160k。上填充层150k可包括平坦的下表面。上填充层150k的外部部分P2k和上填充层150k的中心部分P1k可以在垂直于第一封装基板110的上表面的方向(例如，在Z方向)上具有相同的厚度。
在根据实施例的半导体封装件10000中，中介层140的悬垂在第一半导体芯片120上的部分可以由上填充层150k和下填充层160k支撑。因此，可以防止中介层140的悬垂部分的偏转。
图11是示出根据实施例的半导体封装件11000的截面图。在下文中，将描述图11中所示的半导体封装件11000与图10中所示的半导体封装件10000之间的差异。
参照图11，半导体封装件11000可以包括第一子封装件SP1m和第二子封装件SP2。也就是说，半导体封装件11000可以包括第一子封装件SP1m，而不是图10所示的半导体封装件10000的第一子封装件SP1k。
具体地，如图11所示，第一子封装件SP1m可以包括上填充层150m和下填充层160m，分别代替图10中所示的第一子封装件SP1k中包括的上填充层150k和下填充层160k。上填充层150m可包括中心部分P1m和外部部分P2m。上填充层150m的外部部分P2m可以接触第一半导体芯片120的侧壁的一部分。下填充层160m可以包括中心部分P3m和外部部分P4m。下填充层160m的外部部分P4m可以接触第一半导体芯片120的侧壁的另一部分。上填充层150m的下表面可以接触下填充层160m的上表面。上填充层150m的下表面和下填充层160m的上表面之间的边界表面可以设置在比第一半导体芯片120的上表面的位置低并且比第一半导体芯片120的下表面的位置高的水平处。
图12A至图12D是描述根据实施例的制造半导体封装件的方法中的阶段的截面图。在下文中，将描述制造图1A至图3中分别示出的半导体封装件中的每一个的方法。
参照图12A，其上附接多个第一芯片连接单元130的第一半导体芯片120可以附接在第一封装基板110上，以使多个第一芯片连接单元130面对第一封装基板110。多个第一芯片连接单元130可以将第一半导体芯片120连接到第一封装基板110。
在图12A中，示出了在将第一半导体芯片120附接在第一封装基板110上之前，将外部连接单元190附接在第一封装基板110的下表面上，但是本实施例不限于此。在一些实施例中，如图12D所示，可以将第二子封装件SP2附接在第一子封装件SP1上，然后，可以将外部连接单元190附接在第一封装基板110的下表面上。
参照图12B，上填充层150a可以附接在中介层140的下表面上。随后，其上附接有上填充层150a的中介层140可以附接在第一半导体芯片120上以使上填充层150a面对第一半导体芯片120。也就是说，具有上填充层150a的中介层140可以布置在第一半导体芯片120上方，使得上填充层150a可以面向第一半导体芯片120的顶部。在将中介层140(在沿图12B中的箭头的向下方向上)附接在第一半导体芯片120上的同时，可以向中介层140施加压力。当压力施加到中介层140时，上填充层150a可以基于第一半导体芯片120的形状而变形，例如，上填充层150a的悬垂在半导体芯片120上的部分可以沿着第一半导体芯片120的侧壁被推向第一封装基板110。换言之，上填充层150a的下表面可以比第一半导体芯片120的上表面向下移动更多，例如，移动超过第一半导体芯片120的上表面。可以向中介层140施加压力直到从第一封装基板110的上表面到上填充层150a的下表面的高度变得与从第一封装基板110的上表面到第一半导体芯片120的下表面的高度相等。
因此，如图12C所示，上填充层150a的外部部分P2a的厚度T2可以大于上填充层150a的中心部分P1a的厚度T1。如图12C中进一步所示，中介层140可以通过使用多条导线170连接到第一封装基板110。例如，多条导线170可以形成为从中介层140的上表面延伸到第一封装基板110的上表面。
随后，第一模塑单元180可以形成在第一封装基板110上。第一模塑单元180可以形成为围绕第一半导体芯片120、多个第一芯片连接单元130、多条导线170、上填充层150a和中介层140，并覆盖第一封装基板110的上表面。
参照图12D，可以在第一模塑单元180中形成暴露中介层140的多个连接焊盘140U的多个开口，因此，可以形成第一子封装件SP1。例如，可以通过使用激光的钻孔工艺形成多个开口。
可以独立于第一子封装件SP1制备图1A中所示的第二子封装件SP2。将描述制备第二子封装件SP2的过程，可以通过使用粘合剂层230将至少一个第二半导体芯片220附接在第二封装基板210上，第二封装基板210可以通过多个第二芯片连接单元270连接到第二半导体芯片220，可以形成围绕多个第二芯片连接单元270和第二半导体芯片220并且覆盖第二封装基板210的上表面的第二模塑单元280，并且多个封装间连接单元290可以附接在第二封装基板210的下表面上，从而制备第二子封装件SP2。
随后，第二子封装件SP2可以附接在第一子封装件SP1上，以使多个封装间连接单元290通过第一模塑单元180的多个开口分别接触中介层140的多个连接焊盘140U。因此，可以完成半导体封装件1000a。
在一些实施例中，分别连接到中介层140的多个连接焊盘140U的多个下部封装间连接单元可以分别设置在分别暴露中介层140的多个连接焊盘140U的多个开口中。随后，多个上部封装间连接单元可以附接在第二封装基板210的下表面上，并且随后多个下部封装间连接单元可以分别连接到多个上部封装间连接单元，由此形成多个封装间连接单元290。
为了制造图1B中所示的半导体封装件1000b，如图12A中所示，第一半导体芯片120可以附接在第一封装基板110上。随后，参照图1B，上填充层150b可以附接在中介层140的下表面上。其上附接有上填充层150b的中介层140可放置在第一半导体芯片120上。随后，可以向中介层140施加压力直到从第一封装基板110的上表面到上填充层150b的下表面的高度大于从第一封装基板110的上表面到第一半导体芯片120的下表面的高度。随后的工艺与制造图1A所示的半导体封装件1000a的方法相同，因此省略其详细描述。
为了制造图1C中所示的半导体封装件1000c，如图12A中所示，第一半导体芯片120可以附接在第一封装基板110上。随后，参照图1C，上填充层150c可以附接在中介层140的下表面上。其上附接有上填充层150c的中介层140可放置在第一半导体芯片120上。随后，可以对中介层140施加压力直到从第一封装基板110的上表面到上填充层150c的下表面的高度变得小于从第一封装基板110的上表面到第一半导体芯片120的下表面的高度。随后的工艺与制造图1A所示的半导体封装件1000a的方法相同，因此省略其详细描述。
为了制造图2中所示的半导体封装件2000，以通过执行上面参照图12A至图12D描述的工艺来制备第一子封装件SP1。随后，可以制备图2所示的第二子封装件SP2d。制备第二子封装件SP2d的工艺可以包括制备其中堆叠了通过TSV 271和凸块273连接到彼此的第二半导体芯片220的堆叠结构的工艺、将堆叠结构放置在第二封装基板210上的工艺以及形成第二模塑单元280的工艺。随后，通过将第二子封装件SP2d耦接到第一子封装件SP1，可以完成图2所示的第二半导体封装件2000。
为了制造图3中所示的半导体封装件3000，如图12A所示，第一半导体芯片120可以附接在第一封装基板110上。随后，参照图3，上填充层150e可以附接在中介层140的下表面上。其上附接有上填充层150e的中介层140可放置在第一半导体芯片120上。随后，上填充层150e的下表面可以向下移动，在这种情况下，可以向中介层140施加热和/或压力，以使上填充层150e不覆盖第一半导体芯片120的侧壁的至少一部分。随后的工艺与制造图1A所示的半导体封装件1000a的方法相同，因此省略其详细描述。
图13是用于描述根据实施例的制造半导体封装件的方法的图。在下文中，将描述制造图4中所示的半导体封装件4000的方法。
参照图13，第一半导体芯片120可以附接在第一封装基板110上。随后，第一半导体芯片120可以通过第一芯片连接单元130f连接到第一封装基板110。例如，第一芯片连接单元130f可以形成为从第一半导体芯片120的上表面延伸到第一封装基板110的上表面。
随后，上填充层150a可以附接在中介层140的下表面上。随后，其上附接有上填充层150a的中介层140可放置在第一半导体芯片120上，并且可对该中介层140施加压力。因此，上填充层150a可以围绕第一芯片连接单元130f的一部分。在一些实施例中，上填充层150a和第一封装基板110可以彼此间隔开而不在其间接触。在一些其他实施例中，上填充层150a可以接触第一封装基板110并且可以完全围绕第一芯片连接单元130f。随后的工艺与制造图1A所示的半导体封装件1000a的方法相同，因此省略其详细描述。
图14是用于描述根据实施例的制造半导体封装件的方法的图。在下文中，将描述制造图5中所示的半导体封装件5000的方法。
参照图14，可以提供包括突起115的第一封装基板110a。上填充层150a可以附接在中介层140的下表面上。随后，其上附接有上填充层150a的中介层140可放置在第一半导体芯片120上，并且可以向中介层140施加压力以使上填充层150a接触突起115。随后的工艺与制造图1A所示的半导体封装件1000a的方法相同，因此省略其详细描述。
图15是用于描述根据实施例的制造半导体封装件的方法的图。在下文中，将描述制造图7中所示的半导体封装件7000的方法。
参照图15，第一半导体芯片120可以附接在第一封装基板110上。围绕多个第一芯片连接单元130的下填充层160可以填充到第一封装基板110与第一半导体芯片120之间的空间中。在一些实施例中，下填充层160可以附接在第一半导体芯片120的下表面上，可将第一半导体芯片120放置在第一封装基板110上以使下填充层160面对第一封装基板110，并且可以对第一半导体芯片120施加压力。在一些其他实施例中，第一半导体芯片120可以附接在第一封装基板110上，然后，可以形成填充第一封装基板110和第一半导体芯片120之间的空间的下填充层160。随后的工艺与制造图1A所示的半导体封装件1000a的方法相同，因此省略其详细描述。
图16A和16B是用于描述根据实施例的制造半导体封装件的方法的图。在下文中，将描述制造图8中所示的半导体封装件8000的方法。
参照图16A，如上参照图15所述，第一半导体芯片120可以附接在第一封装基板110上，以使下填充层160填充第一封装基板110与第一半导体芯片120之间的空间。上填充层150i可以形成在或附接在中介层140的下表面上。随后，可将其上附接有上填充层150i的中介层140放置在第一半导体芯片120上以使上填充层150i面对第一半导体芯片120。随后，可以对中介层140施加压力和热量。
因此，如图16B所示，上填充层150i可以变形，因此，上填充层150i可以接触第一封装基板110的上表面。在一些实施例中，上填充层150i可以接触下填充层160的侧表面。随后的工艺与制造图1A所示的半导体封装件1000a的方法相同，因此省略其详细描述。
图17是用于描述根据实施例的制造半导体封装件的方法的图。在下文中，将描述制造图9中所示的半导体封装件9000的方法。
参照图17，第一半导体芯片120可以附接在第一封装基板110上。围绕多个第一芯片连接单元130的下填充层160可以填充在第一封装基板110与第一半导体芯片120之间的空间中。此时，下填充层160j可以形成为覆盖第一半导体芯片120的侧壁的至少一部分。在一些实施例中，例如，下填充层160j可以附接到第一半导体芯片120的下表面上，然后，可将第一半导体芯片120放置在第一封装基板110上，以使下填充层160j面对第一封装基板110。随后，通过对第一半导体芯片120施加压力，多个第一芯片连接单元130可以连接到第一封装基板110。在这样的工艺中，下填充层160j的一部分可以从第一封装基板110和第一半导体芯片120之间的空间溢出到外部并且可以凸出地突起。在一些实施例中，下填充层160j可以从第一封装基板110和第一半导体芯片120之间的空间溢出到外部，并且可以接触第一半导体芯片120的侧壁的至少一部分。在一些其他实施例中。第一半导体芯片120可以附接在第一封装基板110上，然后，下填充层160j可以形成为填充第一封装基板110和第一半导体芯片120之间的空间并接触第一半导体芯片120的侧壁。随后的工艺与制造图1A所示的半导体封装件1000a的方法相同，因此省略其详细描述。
图18A和18B是用于描述根据实施例的制造半导体封装件的方法的图。在下文中，将描述制造图10中所示的半导体封装件10000的方法。
参照图18A，可以形成下填充层160k，使得第一半导体芯片120的上表面和下填充层160k的上表面共面。在一些实施例中，第一半导体芯片120可以附接在第一封装基板110上，然后，可以形成下填充层160k使得下填充层160k围绕第一半导体芯片120，并且第一半导体芯片120上表面和下填充层160k的上表面共面。在一些其他实施例中，其上附接有下填充层160k的第一半导体芯片120可以附接在第一封装基板110上，下填充层160k面对第一封装基板110。随后，可以在第一半导体芯片120的上表面和下填充层160k的上表面上附接条带(tape)并且可以向该条带施加压力。随后，当移除条带时，第一半导体芯片120的上表面和下填充层160k的上表面可以共面。
参照图18B，其上附接有上填充层150k的中介层140可以附接在第一半导体芯片120上，以使上填充层150k面对第一半导体芯片120。随后的工艺与制造图1A所示的半导体封装件1000a的方法相同，因此省略其详细描述。
图19A至图19C是用于描述根据实施例的制造半导体封装件的方法的图。在下文中，将描述制造图11中所示的半导体封装件11000的方法。
参照图19A，下填充层160m可以形成为仅覆盖第一半导体芯片120的侧壁的一部分。在一些实施例中，第一半导体芯片120可以附接在第一封装基板110上并且下填充层160m可以形成在第一封装基板110上，以使下填充层160m仅覆盖第一半导体芯片120的侧壁的一部分。
参照19B至图19C，上填充层150m可以附接在中介层140的下表面上。随后，其上附接有上填充层150m的中介层140可以放置在第一半导体芯片120上以使上填充层150m面对第一半导体芯片120，并且通过向中介层140施加压力，上填充层150m可以覆盖第一半导体芯片120的侧壁的另一部分。
通过总结和回顾，示例实施例提供了一种半导体封装件，其中减小了封装件中的中介层的偏转。也就是说，在基板和中介层140的悬垂于第一半导体芯片120的部分之间提供支撑，以减小悬垂部分的偏转。支撑件可包括上填充层的厚部分、从基板突出的突起、在半导体芯片和基板之间的朝向中介层延伸的下填充层。
本文已经公开了示例实施例，并且尽管采用了特定术语，但是它们仅以一般性和描述性意义来使用和解释，而不是出于限制的目的。在一些情况下，如本领域普通技术人员在提交本申请时显而易见的，结合特定实施例描述的特性、特征和/或元件可以单独使用或与结合其他实施例描述的特性、特征和/或元件组合使用，除非另外特别指出。因此，本领域技术人员将理解，在不脱离所附权利要求中阐述的本发明的精神和范围的情况下，可以在形式和细节上进行各种改变。

Claims (25)

1.一种半导体封装件，包括：
第一封装基板；
第一半导体芯片，其位于所述第一封装基板上；
多个第一芯片连接单元，其用于将所述第一封装基板连接到所述第一半导体芯片；
中介层，其位于所述第一半导体芯片上，所述中介层在平行于所述第一封装基板的上表面的方向上的宽度大于所述第一半导体芯片在平行于所述第一封装基板的上表面的方向上的宽度；以及
上填充层，其包括中心部分和外部部分，所述中心部分位于所述第一半导体芯片和所述中介层之间，所述外部部分围绕所述中心部分，并且所述外部部分在垂直于所述第一封装基板的上表面的方向上的厚度大于所述中心部分在垂直于所述第一封装基板的上表面的方向上的厚度。
2.根据权利要求1所述的半导体封装件，其中，所述上填充层的所述外部部分与所述中介层的下表面并与所述第一半导体芯片的侧壁接触。
3.根据权利要求1所述的半导体封装件，其中，所述上填充层在平行于所述第一封装基板的上表面的方向上的宽度与所述中介层在平行于所述第一封装基板的上表面的方向上的宽度相同。
4.根据权利要求1所述的半导体封装件，其中，所述上填充层与所述第一封装基板间隔开。
5.根据权利要求1所述的半导体封装件，其中，所述上填充层与所述第一封装基板接触。
6.根据权利要求5所述的半导体封装件，其中，
第一封装基板包括基底部分和从所述基底部分的上表面向上突出的突起，并且
所述上填充层与所述第一封装基板的所述突起接触。
7.根据权利要求6所述的半导体封装件，其中，所述第一封装基板的所述突起在平面图中具有闭环形状。
8.根据权利要求6所述的半导体封装件，其中，所述突起在平行于所述第一封装基板的上表面的方向上的宽度大于所述突起在垂直于所述第一封装基板的上表面的方向上的高度。
9.根据权利要求1所述的半导体封装件，其中，所述上填充层与所述第一半导体芯片的整个上表面和所述中介层的整个下表面接触。
10.根据权利要求1所述的半导体封装件，还包括位于所述第一封装基板和所述第一半导体芯片之间的下填充层，所述下填充层围绕所述多个第一芯片连接单元。
11.根据权利要求10所述的半导体封装件，其中，所述下填充层与所述上填充层接触。
12.根据权利要求10所述的半导体封装件，其中，所述下填充层与所述第一半导体芯片的侧壁的至少一部分接触。
13.根据权利要求1所述的半导体封装件，还包括：
第二封装基板，其位于所述中介层上；
封装间连接单元，其位于所述第二封装基板和所述中介层之间；以及
至少一个第二半导体芯片，其位于所述第二封装基板上。
14.一种半导体封装件，包括：
第一封装基板；
第一半导体芯片，其位于所述第一封装基板上；
多个第一芯片连接单元，其用于将所述第一封装基板连接到所述第一半导体芯片；
中介层，其位于所述第一半导体芯片上，所述中介层在平行于所述第一封装基板的上表面的方向上的宽度大于所述第一半导体芯片在平行于所述第一封装基板的上表面的方向上的宽度；
上填充层，其填充所述中介层和所述第一半导体芯片之间的空间；以及
下填充层，其包括中心部分和外部部分，所述下填充层的中心部分填充所述第一半导体芯片和所述第一封装基板之间的空间，所述下填充层的外部部分围绕所述下填充层的中心部分，并且所述下填充层的外部部分在垂直于所述第一封装基板的上表面的方向上的厚度大于所述下填充层的中心部分在垂直于所述第一封装基板的上表面的方向上的厚度。
15.根据权利要求14所述的半导体封装件，其中，所述上填充层包括位于所述第一半导体芯片和所述中介层之间的中心部分，和围绕所述上填充层的中心部分的外部部分，并且所述上填充层的外部部分在垂直于所述第一封装基板的上表面的方向上的厚度大于所述上填充层的中心部分在垂直于所述第一封装基板的上表面的方向上的厚度。
16.根据权利要求14所述的半导体封装件，其中，所述下填充层与所述上填充层接触。
17.根据权利要求14所述的半导体封装件，其中，所述上填充层与所述第一半导体芯片的侧壁的上部接触。
18.根据权利要求14所述的半导体封装件，其中，所述第一半导体芯片的上表面和所述下填充层的外部部分的上表面共面。
19.根据权利要求14所述的半导体封装件，其中，所述下填充层的外部部分与所述第一半导体芯片的侧壁的下部接触。
20.根据权利要求14所述的半导体封装件，其中，所述下填充层的外部部分与所述第一半导体芯片的整个侧壁接触。
21.根据权利要求14所述的半导体封装件，还包括：
第二封装基板，其位于所述中介层上；
封装间连接单元，其位于所述第二封装基板和所述中介层之间；以及
至少一个第二半导体芯片，其位于所述第二封装基板上。
22.根据权利要求14所述的半导体封装件，还包括将所述中介层的上表面连接到所述第一封装基板的多条导线。
23.根据权利要求14所述的半导体封装件，还包括第一模塑单元，所述第一模塑单元围绕所述中介层和所述下填充层，并覆盖所述第一封装基板。
24.一种半导体封装件，包括：
第一子封装件，其包括：
第一封装基板，
第一半导体芯片，其位于所述第一封装基板上，
多个第一芯片连接单元，其位于所述第一封装基板和所述第一半导体芯片之间，
中介层，其位于所述第一半导体芯片上，所述中介层在平行于所述第一封装基板的上表面的方向上的宽度大于所述第一半导体芯片在平行于所述第一封装基板的上表面的方向上的宽度，
上填充层，其填充所述中介层和所述第一半导体芯片之间的空间，以及
下填充层，其填充所述第一半导体芯片和所述第一封装基板之间的空间的；和
第二子封装件，其包括：
多个封装间连接单元，其位于所述中介层上，
第二封装基板，其位于所述多个封装间连接单元上，
至少一个第二半导体芯片，其位于所述第二封装基板上，以及
第二模塑单元，其围绕所述至少一个第二半导体芯片并覆盖所述第二封装基板的上表面，
其中，所述上填充层和所述下填充层中的至少一个与所述第一半导体芯片的侧壁接触。
25.根据权利要求24所述的半导体封装件，其中，所述上填充层与所述第一半导体芯片的侧壁接触，并且所述下填充层与所述第一半导体芯片的侧壁间隔开。
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