CN111048589B - 一种功率半导体集成器件 - Google Patents

一种功率半导体集成器件 Download PDF

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CN111048589B
CN111048589B CN201911225848.3A CN201911225848A CN111048589B CN 111048589 B CN111048589 B CN 111048589B CN 201911225848 A CN201911225848 A CN 201911225848A CN 111048589 B CN111048589 B CN 111048589B
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谢福渊
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Nanjing Jiangzhi Technology Co ltd
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Abstract

本发明公开了一种包括屏蔽栅沟槽式金属氧化物半导体场效应管单元(SGT MOSFET)和超级势垒整流器(SBR)单元的集成电路，其中，SBR与SGT MOSFET位于同一芯片的不同位置。SBR单元为MOS沟道中的多数载流子提供了一个低势垒的环境，因此相比与传统的肖特基整流器来说，具有更低的反向电压和更低的反向漏电流。同时，在一些优选的实施例中，屏蔽栅结构采用了多阶梯状氧化物(MSO)结构，以进一步降低导通电阻。

Description

一种功率半导体集成器件
技术领域
本发明主要涉及一种功率半导体集成器件的单元结构，特别涉及一种新型的包括屏蔽栅沟槽式金属氧化物半导体场效应管（Shielded Gate Trench Metal-oxide-Semiconductor Field EffectTransistor,SGT MOSFET）单元和超级势垒整流器（SuperBarrier Rectifier, SBR）单元的功率半导体集成器件的单元结构。
背景技术
图1A和图1B分别示出了现有技术中两种典型的SGT MOSFET结构，与传统的具有单栅结构的沟槽式MOSFET相比，图1A和图1B中所示的两种结构由于具有位于漂移区的电荷耦合区和位于栅氧下方的厚氧化层，从而具有更低的栅电荷和导通电阻。
为了更进一步降低导通电阻，美国专利号9，716，009公开了一种具有多阶梯氧化层（Multiple SteppedOxide,MSO）结构的SGTMOSFET，如图1C所示。与图1A和图1B相比，图1C所示的结构可以降低约25%的导通电阻。根据该现有技术，在一个沟槽中，该MSO结构具有多个小的阶梯状氧化层和阶梯状的多晶硅场板，通过优化阶梯的宽度和长度，在相同击穿电压的情况下，具有该MSO结构的SGTMOSFET可以实现更低的导通电阻。
然而，由于寄生体二极管的存在，上述三种结构的SGT MOSFET仍然面临具有较高反向恢复电荷Qrr（reverserecovery charge）的问题，而这会导致器件具有较高的开关损耗。
因此，在半导体功率器件领域中，特别是对于SGT MOSFET的设计和制造，仍需要提供一种新型的单元结构和器件构造可以使得SGT MOSFET实现更低的导通电阻的同时，具有更低的开关损耗。
发明内容
本发明提供了一种功率半导体集成器件，包括集成在同一芯片上的SGT MOSFET和SBR，以降低器件的开关损耗。SBR结构在MOS沟道中为多数载流子创造了一个低势垒的环境，并且可以通过对栅氧的厚度、体区的掺杂浓度和沟道长度加以调节。与肖特基整流器相比，该SBR结构具有较低的正向电压Vf和较低的反向泄漏电流Ir，与此同时，在高温环境下，在该SBR结构具有更加良好和更加稳定的性能。
根据本发明的一个方面，提供了一种功率半导体集成器件，其特征在于，包括水平地位于同一芯片上不同位置的SGT MOSFET和SBR，还包括：
(a)第一导电类型的外延层，覆盖所述第一导电类型的衬底上方，所述衬底的多数载流子掺杂浓度高于所述外延层；
(b)所述SGT MOSFET进一步包括：
(c)多个第一类沟槽，位于所述外延层中，每个所述第一类沟槽中填充以第一屏蔽电极和第一栅电极，所述第一屏蔽电极与所述外延层之间由第一绝缘层绝缘，所述第一栅电极与所述外延层之间由第一栅极氧化层绝缘，所述第一屏蔽电极和所述第一栅电极之间相互绝缘；
(d)第二导电类型的第一体区，其上方包括所述第一导电类型的第一源区，并且所述第一体区围绕衬有所述第一栅极氧化层的所述第一栅电极；
(e)所述SBR进一步包括；
(f)至少一个第二类沟槽，位于所述外延层中，且填充以第二屏蔽电极和第二栅电极，所述第二屏蔽电极与所述外延层之间由第二绝缘层绝缘，所述第二栅电极与所述外延层之间由第二栅极氧化层绝缘，所述第二屏蔽电极与所述第二栅电极之间相互绝缘；
(g)所述第二栅极氧化层的厚度小于所述第一栅极氧化层的厚度；
(h)第二导电类型的第二体区，其上方包括所述第一导电类型的第二源区，并且所述第二体区围绕衬有所述第二栅极氧化层的所述第二栅电极；并且
(i)所述第一体区、所述第二体区、所述源区和所述第二栅电极通过多个沟槽式接触区连接至源极金属。
根据本发明的另一个方面，位于SBR中的第二体区可以比位于SGT MOSFET中的第一体区具有更浅的结深和更低的掺杂浓度，这样可以提供一个更短的沟道长度，使得SBR结构更为有效。因此，在一些优选的实施例中，所述第二体区的结深和多数载流子掺杂浓度小于所述第一体区。在另一些优选的实施例中，所述第二体区的结深和多数载流子掺杂浓度与所述第一体区相同。
根据本发明的另一个方面，所述外延层可以包括单层结构和双层结构，因此在一些优选的实施例中，所述外延层为单一外延层且具有均匀的掺杂浓度。在另一些优选的实施例中，所述外延层进一步包括电阻率为R1的第一外延层和电阻率为R2的第二外延层，其中第一外延层位于第二外延层的下方，且R1>R2，所述第一和第二类沟槽穿过所述第二外延层延伸入所述第一外延层。在另一些优选的实施例中，所述外延层进一步包括一个第一导电类型的漂移区，该漂移区形成于所述外延层的上部，并且所述第一和第二类沟槽的沟槽底部都位于所述漂移区。
根据本发明的另一个方面，在一些优选的实施例中，在每个所述第一类沟槽中，所述第一屏蔽电极位于沟槽的下部，所述第一栅电极位于沟槽的上部，所述第一屏蔽电极和所述第一栅电极之间由第三绝缘层绝缘；在所述第二类沟槽中，所述第二屏蔽电极位于沟槽的下部，所述第二栅电极位于沟槽的上部，所述第二屏蔽电极和所述第二栅电极之间由所述第四绝缘层绝缘。在另一些优选的实施例中，在每个所述第一类沟槽中，所述第一屏蔽电极位于沟槽中央，所述第一栅电极围绕所述屏蔽电极的上部，所述第一屏蔽电极和所述第一栅电极之间由所述第一栅极氧化层绝缘；在所述第二类沟槽中，所述第二屏蔽电极位于沟槽中央，所述第二栅电极围绕所述第二屏蔽电极的上部，所述第二屏蔽电极和所述第二栅电极之间由所述第二栅极氧化层绝缘。
根据本发明的另一个方面，当屏蔽电极位于沟槽下部时，在一些优选的实施例中，位于屏蔽电极与外延层之间的第一和第二绝缘层为厚度均匀的单一绝缘层。在另一些优选的实施例中，所述第一和第二绝缘层为多个阶梯状氧化层结构，且其位于沟槽底部的厚度大于其位于沟槽侧壁的厚度。
根据本发明的另一个方面，在一些优选的实施例中，所述第二类沟槽的沟槽宽度和沟槽长度分别等于所述第一类沟槽的沟槽宽度和沟槽长度。在另一些优选的实施例中，所述第二类沟槽的沟槽宽度和沟槽长度分别大于所述第一类沟槽的沟槽宽度和沟槽长度。
通过参考以下各个附图，阅读下文对优选实施例的详细描述，本发明的上述及其他目的和有点对于本领域的普通技术人员来说无疑是显而易见的。
附图说明
图1A示出了现有技术所揭示的一种传统的SGT MOSFET的剖面图。
图1B示出了现有技术所揭示的另一种传统的SGT MOSFET的剖面图。
图1C示出了现有技术所揭示的MSO MOSFET的剖面图。
图2A是根据本发明一个优选实施例的剖面图。
图2B是根据本发明另一个优选实施例的剖面图。
图2C是根据本发明另一个优选实施例的剖面图。
图3A是根据本发明另一个优选实施例的剖面图。
图3B是根据本发明另一个优选实施例的剖面图。
图3C是根据本发明另一个优选实施例的剖面图。
图4是根据本发明另一个优选实施例的剖面图。
图5是根据本发明另一个优选实施例的剖面图。
图6A是根据本发明另一个优选实施例的剖面图。
图6B是根据本发明另一个优选实施例的剖面图。
图6C是根据本发明另一个优选实施例的剖面图。
图7A是根据本发明另一个优选实施例的剖面图。
图7B是根据本发明另一个优选实施例的剖面图。
图7C是根据本发明另一个优选实施例的剖面图。
具体实施方式
下面参照附图更详细地说明本发明，其中示出了本发明的优选实施例。本发明可以，但是以不同的方式体现，但是不应该局限于在此所述的实施例。例如，这里的说明更多地引用N沟道的半导体集成电路，但是很明显其他器件也是可能的。下文是通过参考各个附图来对实践本发明的优选实施例进行详细描述。一些方向术语，例如“顶部”、“底部”、“前”、“后”、“上方”、“下方”等，是参考各个附图的方向进行描述的。由于实施例中的元件可以被放置在许多不同的方向，因此，本发明中的方向术语只是用于描述而不能被视为对本发明的限制。应该理解的是，实施例中各种结构或者逻辑上的替代和修改都应该被涵盖在本发明的真正精神和范围内。因此，以下的详细描述不能被视为对本发明的限制，本发明的涵盖范围由附后的权利要求界定。应该理解的是，本发明中所描述的各个优选实施例的发明特征可以相互结合，有特别说明的除外。
图2A所示的是本发明的一个优选实施例，其中N沟道的SGT MOSFET 200和一个SBR200’集成在同一个芯片上，该芯片形成于N外延层202中且位于N+衬底201之上，其中，N外延层202的多数载流子掺杂浓度小于N+衬底201。更进一步地，在N外延层202中，垂直形成有多个第一类沟槽203和至少一个第二类沟槽204，每个沟槽内均填充以屏蔽栅结构，即每个所述第一类沟槽203中包括一个位于沟槽下部且衬有第一绝缘层206的第一屏蔽电极205（SG，如图2A所示），每个所述第二类沟槽204中包括一个位于沟槽下部且衬有第二绝缘层206’的第二屏蔽电极205’。所述第一类沟槽和第二类沟槽内的填充结构的不同之处在于：第一类沟槽203中包括一个第一栅电极207，其与所述第一屏蔽电极205之间由第三绝缘层208绝缘，其与所述N外延层202之间由第一栅极氧化层209绝缘，并且该第一栅电极207进一步连接至SGT 200的栅极金属层（未示出）；第二类沟槽204包括一个第二栅电极210，其与所述第二屏蔽电极205’之间由第四绝缘层208’绝缘，其与所述N外延层202之间由第二栅极氧化层211绝缘，其中，为了更好地形成SBR，所述第二栅极氧化层211的厚度小于所述第一栅极氧化层209的厚度，与此同时，所述第二栅电极210通过沟槽式接触区213-1进一步连接至一层源极金属212。在SGT MOSFET 200的部分，p1第一体区214位于所述N外延层202的上部分且围绕衬有第一栅极氧化层209的第一栅电极207，且p1第一体区214上方包括一个n+第一源区215。在SBR 200’的部分，p2第二体区216位于所述N外延层202的上部分且围绕衬有第二栅极氧化层211的第二栅电极210，且p2第二体区216上方包括n+第二源区215’。值得注意的是：p2第二体区216的结深和多数载流子掺杂浓度都小于p1第一体区214，以此为SBR结构提供一个较短的沟道长度。同时，p1第一体区214、p2第二体区216、n+第一源区215和n+第二源区215’都分别通过沟槽式接触区213-2、213-3和213-4连接至源极金属212。以上提到的多个沟槽式接触区（213-1~213-4）都填充以衬有势垒层的金属插塞，且都穿过一个接触绝缘层217并延伸入体区，在体区内，该多个沟槽式接触区的底部都被一个p+体接触区218包围，以减少体区和金属插塞之间的接触电阻。在该优选实施例中，所述第二类沟槽204的沟槽宽度和深度都大于或等于所述第一类沟槽203的沟槽宽度和深度，以避免在SBR结构的部分发生过早的击穿。
图2B所示的是根据本发明的另一个优选的实施例，与图2A相比，图2B中所示的集成电路不仅包括一个SGT MOSFET 300和一个SBR 300’，还包括一个双层结构的外延层。该双层结构的外延层进一步包括一层电阻率为R1的第一外延层302-1和电阻率为R2的第二外延层302-2，其中第一外延层302-1位于第二外延层302-2的下方，且R1>R2，位于SGT MOSFET300中的第一类沟槽303和位于SBR 300’中的第二类沟槽304穿过所述第二外延层302-2并延伸入所述第一外延层302-1。值得注意的是，在该优选实施例中，R1>R2，这样可以在靠近沟槽底部的转角处提供高电阻率的外延层，以避免发生过早击穿，同时，可以在沟槽底部上方提供低电阻率的外延层，以降低器件的导通电阻。
图2C所示的是根据本发明的另一个优选的实施例，与图2A相比，图2C所示的集成电路不仅包括一个SGT MOSFET 400和一个SBR 400’，还包括一个位于N外延层402上方的N型漂移区413。位于SGT MOSFET 400中的第一类沟槽403和位于SBR 400’中的第二类沟槽404都位于所述N型漂移区413中，这是因为在制造过程中，所述N型漂移区413的形成是通过在第一和第二类沟槽的开口处进行有角度的离子注入，以将N型掺杂离子注入进沟槽之间的台面中；或者是通过对位于沟槽之间的台面上方进行离子注入，以将N型掺杂离子注入进台面中。
图3A所示的是根据本发明的另一个优选的实施例，其包括一个N沟道的SGTMOSFET 500和一个SBR 500’。与图2A相比，在图3A中，位于SBR 500’中的p型第一体区514与位于SGT MOSFET 500中的p型第二体区514’具有相同的结深和掺杂浓度，以防止图2A中的短沟道结构发生穿通现象。
图3B所示的是根据本发明的另一个优选的实施例，其包括一个N沟道的SGTMOSFET 600和一个SBR 600’。与图2B相比，在图3B中，位于SBR 600’中的p型第一体区614与位于SGT MOSFET 600中的p型第二体区614’具有相同的结深和掺杂浓度，以防止图2B中的短沟道结构发生穿通现象。
图3C所示的是根据本发明的另一个优选的实施例，其包括一个N沟道的SGTMOSFET 700和一个SBR 700’。与图2C相比，在图3C中，位于SBR 700’中的p型体区714与位于SGT MOSFET 700中的p型体区714’具有相同的结深和掺杂浓度，以防止图2C中的短沟道结构发生穿通现象。
图4所示的是根据本发明的另一个优选的实施例，其包括一个N沟道的SGT MOSFET800和一个SBR 800’。与图2C相比，图4中位于所有沟槽内的第一绝缘层806均具有MSO结构，以在进一步降低导通电阻的同时维持击穿电压不变。此外，所述第一绝缘层806和所述第二绝缘层806’位于沟槽底部的厚度最大。
图5所示的是根据本发明的另一个优选的实施例，其包括一个N沟道的SGT MOSFET900和一个SBR 900’。与图3C相比，图5中位于所有沟槽内的第一绝缘层906均具有MSO结构，以在进一步降低导通电阻的同时维持击穿电压不变。此外，所述第一绝缘层906和所述第二绝缘层906’位于沟槽底部的厚度最大。
图6A所示的是根据本发明的另一个优选的实施例，其包括一个N沟道SGT MOSFET1000和一个SBR 1000’，并且图6A中的第一类沟槽1003和第二类沟槽1004中包括与图2A不同的屏蔽栅结构。在位于SGT MOSFET 1000部分的第一类沟槽1003中，屏蔽栅结构包括：一个第一屏蔽电极1005，位于沟槽中央；一个第一栅电极1007，位于第一类沟槽1003的上部，且位于所述第一屏蔽电极1005和所述第一类沟槽1003侧壁的中央；其中所述第一屏蔽电极1005与N外延层1002之间由第一绝缘层1006绝缘，所述第一栅电极1007与所述第一屏蔽电极1005和所述外延层之间由第一栅极氧化层1009绝缘。在位于SBR 1000’部分的第二类沟槽1004中，屏蔽栅结构包括：一个第二屏蔽电极1005’，位于沟槽中央；一个第二栅电极1010，位于第二类沟槽1004的上部，且位于所述第二屏蔽电极1005’和所述第二类沟槽1004侧壁的中央；其中所述第二屏蔽电极1005’与所述N外延层1002之间由第二绝缘层1006’绝缘，所述第二栅电极1010与所述第二屏蔽电极1005’以及所述外延层之间由第二栅极氧化层1011绝缘，其中所述第二栅极氧化层1011的厚度小于所述第一栅极氧化层1009的厚度，以形成SBR结构。此外，所述第二类沟槽1004的沟槽宽度和沟槽深度都等于或者大于所述第一类沟槽1003，以放置在SBR区域发生过早的击穿。
图6B所示的是根据本发明的另一个优选的实施例，与图6A相比，图6B中所示的集成电路不仅包括一个SGT MOSFET 1100和一个SBR 1100’，还包括一个双层结构的外延层。该双层结构的外延层进一步包括一层电阻率为R1的第一外延层1102-1和电阻率为R2的第二外延层1102-2，其中第一外延层1102-1位于第二外延层1102-2的下方，且R1>R2，位于SGTMOSFET 1100中的第一类沟槽1103和位于SBR 1100’中的第二类沟槽1104穿过所述第二外延层1102-2并延伸入所述第一外延层1102-1。值得注意的是，在该优选实施例中，R1>R2，这样可以在靠近沟槽底部的转角处提供高电阻率的外延层，以避免发生过早击穿，同时，可以在沟槽底部上方提供低电阻率的外延层，以降低器件的导通电阻。
图6C所示的是根据本发明的另一个优选的实施例，与图6A相比，图6C所示的集成电路不仅包括一个SGT MOSFET 1200和一个SBR 1200’，还包括一个位于N外延层1202上方的N型漂移区1213。位于SGT MOSFET 1200中的第一类沟槽1203和位于SBR 1200’中的第二类沟槽1204都位于所述N型漂移区1213中，这是因为在制造过程中，所述N型漂移区1213的形成是通过在第一和第二类沟槽的开口处进行有角度的离子注入，以将N型掺杂离子注入进沟槽之间的台面中；或者是通过对位于沟槽之间的台面上方进行离子注入，以将N型掺杂离子注入进台面中。
图7A所示的是根据本发明的另一个优选的实施例，其包括一个N沟道的SGTMOSFET 1300和一个SBR 1300’。与图6A相比，在图7A中，位于SGT MOSFET 1300中的p型第一体区1314与位于SBR 1300’中的p型第二体区1314’具有相同的结深和掺杂浓度，以防止图6A中的短沟道结构发生穿通现象。
图7B所示的是根据本发明的另一个优选的实施例，其包括一个N沟道的SGTMOSFET 1400和一个SBR 1400’。与图6B相比，在图7B中，位于SGT MOSFET 1400中的p型第一体区1414与位于SBR 1400’中的p型第二体区1414’与具有相同的结深和掺杂浓度，以防止图6B中的短沟道结构发生穿通现象。
图7C所示的是根据本发明的另一个优选的实施例，其包括一个N沟道的SGTMOSFET 1500和一个SBR 1500’。与图6C相比，在图7C中，位于SGT MOSFET 1500中的p型第一体区1514与位于SBR 1500’中的p型第二体区1514’与具有相同的结深和掺杂浓度，以防止图6C中的短沟道结构发生穿通现象。
尽管在此说明了各种实施例，可以理解，在不脱离本发明的精神和范围的所附权利要求书的范围内，通过所述的指导，可以对本发明作出各种修改。例如，可以用本发明的方法形成其导电类型与文中所描述的相反的导电类型的各种半导体区域的结构。

Claims (8)

1. 一种功率半导体集成器件，其特征在于，包括水平地位于同一芯片上不同位置的一个屏蔽栅沟槽式金属氧化物半导体场效应管（SGT MOSFET）和一个超级势垒整流器（SBR），还包括：
第一导电类型的外延层，覆盖所述第一导电类型的衬底上方，所述衬底的多数载流子掺杂浓度高于所述外延层；
所述SGT MOSFET进一步包括：
多个第一类沟槽，位于所述外延层中，每个所述第一类沟槽中填充以第一屏蔽电极和第一栅电极，所述第一屏蔽电极与所述外延层之间由第一绝缘层绝缘，所述第一栅电极与所述外延层之间由第一栅极氧化层绝缘，所述第一屏蔽电极和所述第一栅电极之间相互绝缘；
第二导电类型的第一体区，其上方包括所述第一导电类型的第一源区，并且所述第一体区围绕衬有所述第一栅极氧化层的所述第一栅电极；
所述SBR进一步包括：
至少一个第二类沟槽，与所述第一类沟槽平行位于所述外延层中，且填充以第二屏蔽电极和第二栅电极，所述第二屏蔽电极与所述外延层之间由第二绝缘层绝缘，所述第二栅电极与所述外延层之间由第二栅极氧化层绝缘，所述第二屏蔽电极和所述第二栅电极之间相互绝缘；
所述第二栅极氧化层的厚度小于所述第一栅极氧化层的厚度；
第二导电类型的第二体区，其上方包括所述第一导电类型的第二源区，并且所述第二体区围绕衬有所述第二栅极氧化层的所述第二栅电极；
所述第一体区、所述第二体区、所述第一和第二源区和所述第二栅电极通过多个沟槽式接触区连接至源极金属；并且
所述第二体区的结深小于所述第一体区，所述第二体区的掺杂浓度小于所述第一体区。
2.根据权利要求1所述的功率半导体集成器件，其特征在于，所述外延层为单一外延层且具有均匀的掺杂浓度。
3.根据权利要求1所述的功率半导体集成器件，其特征在于，所述外延层进一步包括电阻率为R1的第一外延层和电阻率为R2的第二外延层，其中所述第二外延层位于所述第一外延层的上方，且R1>R2，所述第一和第二类沟槽穿过所述第二外延层且延伸入所述第一外延层中。
4.根据权利要求1所述的功率半导体集成器件，其特征在于，所述外延层进一步包括一个所述第一导电类型的漂移区，该漂移区形成于所述外延层的上部，并且所述第一和第二类沟槽的沟槽底部都位于所述漂移区中。
5.根据权利要求1所述的功率半导体集成器件，其特征在于，在每个所述第一类沟槽中，所述第一屏蔽电极位于沟槽的下部，所述第一栅电极位于沟槽的上部，所述第一屏蔽电极和所述第一栅电极之间由第三绝缘层绝缘；在所述第二类沟槽中，所述第二屏蔽电极位于沟槽的下部，所述第二栅电极位于沟槽的上部，所述第二屏蔽电极和所述第二栅电极之间由第四绝缘层绝缘。
6.根据权利要求5所述的功率半导体集成器件，其特征在于，所述第一绝缘层为厚度均匀的单一绝缘层。
7.根据权利要求5所述的功率半导体集成器件，其特征在于，所述第一和第二绝缘层为多个阶梯状氧化层结构，其位于沟槽底部的厚度大于其位于沟槽侧壁的厚度。
8.根据权利要求1所述的功率半导体集成器件，其特征在于，所述第二类沟槽的沟槽宽度和沟槽深度等于所述第一类沟槽。
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