CN111048471B - n沟道和p沟道增强型GaN器件集成结构的制备方法 - Google Patents
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Abstract
本发明公开了一种n沟道和p沟道增强型GaN器件集成结构的制备方法,包括:洁净衬底上进行高阻缓冲层、n沟道层、势垒层、p沟道层、插入层、p沟阈值调制层、p沟栅流抑制层的制作;n沟阈值调制层和n沟栅流抑制层再生长掩模的制作;n沟阈值调制层和n沟栅流抑制层制作;p沟器件欧姆接触金属的制作;n沟器件欧姆接触金属的制作;器件隔离区域制作;表面钝化层制作;n沟道器件和p沟道器件栅接触的制作;n沟道器件和p沟道器件欧姆接触压块的制作。本发明基于JFET GaN器件结构和能带理论,实现n沟道和p沟道增强型GaN器件的集成,可有效降低GaN数字集成电路功耗,结构及工艺兼容性高,器件阈值电压均匀性高、稳定性高。
Description
技术领域
本发明属于半导体器件制备技术领域,特别是一种n沟道和p沟道增强型GaN器件集成结构的制备方法。
背景技术
GaN基宽禁带半导体材料具有高临界击穿场强、高载流子漂移速度以及抗辐照等优异的物理和化学特性,是研制高性能微波器件和电力电子开关器件的优选材料。虽然GaN微波器件和电力电子器件展现了优异的器件特性,单在使用中需要配合Si CMOS逻辑控制电路来使用。由于两种器件无法实现单片集成,通常采用封装的方式采用金丝键合等方式进行电学连接,并封装在一起进行实用。采用这种方法会在两种材料之间引入高的寄生电感等特性,从而无法发挥出GaN器件的性能优势。
为了解决这一问题,国内外众多研究机构已经开展了GaN逻辑电路的相关研究。主要采用n沟道的增强型器件和n沟道耗尽型器件来实现反向器,与非门等GaN逻辑单元,并取得了一定的进展。然而,随着研究的深入,采用n沟道增强型器件和n沟道耗尽型器件形成的逻辑单元功耗无法降低的问题逐渐显现。为此国外HRL等机构已开展p沟道GaN器件的研制。目前国外主要采用p掺杂GaN/非故意掺杂GaN/非故意掺杂AlGaN的结构来实现p沟道GaN器件。采用该结构一般形成的是耗尽型p沟道GaN器件,为了实现增强型p沟道GaN器件,目前主要采用的方法是采用MIS结构,在栅的区域进行GaN层的刻蚀,通过这种方法来降低栅下p沟道载流子浓度,从而实现p沟道的增强型GaN器件,如谢菲尔大学的Narayanan(J.Phys.D:Appl.Phys.51(2018)163001:28-29)和HRL的Rongming Chu(J.Phys.D:Appl.Phys.51(2018)163001:32-33)都介绍了采用该方法实现n沟道和p沟道增强型GaN器件集成的方法。但由于GaN基材料是化合物半导体,在GaN基材料上很难实现低界面态密度的MIS结构。高的界面态密度将导致GaN MIS结构器件出现阈值电压漂移以及可靠性问题。
发明内容
本发明的目的在于提供一种n沟道和p沟道增强型GaN器件集成结构的制备方法,针对采用MIS结构实现n沟道和p沟道增强型GaN器件集成中存在界面态密度高,容易导致器件阈值电压漂移和可靠性降低的问题,通过采用JFET器件结构来实现n沟道和p沟道增强型GaN器件,基于选择再生长等技术实现新结构n沟道和p沟道增强型GaN器件集成。
实现本发明目的的技术解决方案为:一种n沟道和p沟道增强型GaN器件集成结构的制备方法,包括以下步骤:
步骤1:在洁净的衬底上依次外延生长高阻缓冲层、n沟道层、势垒层、p沟道层、p型插入层、p沟阈值调制层和p沟栅流抑制层;
步骤2:在样品表面生长刻蚀掩模层,通过光刻、显影工艺,利用光刻胶定义刻蚀区域,然后刻蚀无光刻胶保护区域的刻蚀掩模层,通过有机清洗剂去除光刻胶,以剩余刻蚀掩模层为掩模依次刻蚀无掩模区域的p沟栅流抑制层、p沟阈值调制层和p型插入层;
步骤3:在样品表面淀积刻蚀掩模层,通过光刻、显影工艺,利用光刻胶定义刻蚀区域,然后刻蚀无光刻胶保护区域的刻蚀掩模层,通过有机清洗剂去除光刻胶,以剩余刻蚀掩模层为掩模刻蚀无掩模区域p沟道层;
步骤4:利用湿法腐蚀的方法,去除刻蚀掩模层和,在样品表面淀积选择再生长掩模层,通过光刻、显影工艺,利用光刻胶定义选择再生长窗口区域,然后刻蚀无光刻胶保护区域的刻蚀再生长掩模层,通过有机清洗剂去除光刻胶;
步骤5:利用氧等离子体进行表面处理,然后通过酸性和碱性溶液对表面进行表面清洁,然后在样品表面依次外延生长n沟阈值调制层和n沟栅流抑制层;
步骤6:利用氢氟酸缓冲溶液在超声下去除选择再生长掩模层及其上的n沟阈值调制层和n沟栅流抑制层;
步骤7:在样品表面旋涂光刻胶掩模,通过光刻、显影工艺,利用光刻胶定义刻蚀区域,然后刻蚀无光刻胶保护区域的n沟栅流抑制层;
步骤8:在样品表面淀积p沟器件欧姆接触金属层,然后利用正胶剥离的方法去除光刻胶掩模以外的p沟器件欧姆接触金属层(15);
步骤9:通过光刻、显影工艺,利用光刻胶定义n沟道器件欧姆接触区域,淀积n沟道器件欧姆接触层,然后利用正胶剥离的方法去除光刻胶定义n沟道器件欧姆接触区域以外的n沟道器件欧姆接触层,在惰性气体的保护下进行合金处理;
步骤10:通过光刻、显影工艺,利用光刻胶定义器件隔离区域,利用离子注入技术在势垒层、n沟道层和部分高阻缓冲层中注入高能粒子形成隔离层;
步骤11:利用有机溶剂在超声下去除离子注入时的光刻胶,利用氮等离子体进行表面处理,随后在样品表面淀积表面钝化层;
步骤12:通过光刻、显影工艺,利用光刻胶定义n沟道器件和p沟道器件栅接触区域,刻蚀无光刻胶保护区域的表面钝化层,然后淀积栅金属接触层,然后利用正胶剥离的方法去除光刻胶定义n沟道器件和p沟道器件栅接触区域以外的栅金属接触层,在惰性气体的保护下进行低温处理;
步骤13:通过光刻、显影工艺,利用光刻胶定义n沟道器件和p沟道器件欧姆接触压块区域,刻蚀无光刻胶保护区域的表面钝化层,通过有机清洗剂去除光刻胶。
本发明与现有技术相比,其显著优点为:(1)本发明可有效降低GaN数字集成电路功耗;(2)结构及工艺兼容性高,可实现GaN功率开关、GaN微波功率器件以及GaN逻辑电路的全集成;(3)器件阈值电压均匀性高、稳定性高;(4)集成器件抗辐照性能高;(5)增强型器件阈值控制工艺窗口宽,工艺实现难度低。
附图说明
图1为n沟道和p沟道增强型GaN器件集成结构的示意图。
图2(a)~图2(m)为n沟道和p沟道增强型GaN器件集成结构的制备流程图,其中:
图2(a)为洁净衬底上进行高阻缓冲层、n沟道层、势垒层、p沟道层、插入层、p沟阈值调制层、p沟栅流抑制层制作的示意图。
图2(b)为刻蚀无掩模区域p沟栅流抑制层、p沟阈值调制层和p型插入层的示意图。
图2(c)为刻蚀无掩模区域p沟道层的示意图。
图2(d)为刻蚀无光刻胶保护区域的刻蚀再生长掩模层示意图。
图2(e)为n沟阈值调制层和n沟栅流抑制层再生长掩模制作示意图。
图2(f)为利用氢氟酸缓冲溶液在超声下去除选择再生长掩模层及其上的n沟阈值调制层和n沟栅流抑制层的示意图。
图2(g)为刻蚀无光刻胶保护区域的GaN n沟栅流抑制层的示意图。
图2(h)为p沟器件欧姆接触金属的制作示意图。
图2(i)为n沟器件欧姆接触金属的制作示意图。
图2(j)为器件隔离区域的制作示意图。
图2(k)为表面钝化层的制作示意图。
图2(l)为n沟道器件和p沟道器件栅接触的制作示意图。
图2(m)为n沟道器件和p沟道器件欧姆接触压块的制作示意图。
具体实施方式
本发明针对GaN E/D集成技术功耗高以及MIS结构集成n沟道和p沟道GaN增强型器件界面态密度高,导致阈值电压漂移严重以及可靠性差的问题,基于JFET GaN器件结构和能带理论,设计了新型材料结构和制备方法来实现n沟道和p沟道增强型GaN器件的集成,开发了不依赖MIS结构的一种n沟道和p沟道增强型GaN器件集成结构的制备方法。
如图1所示,一种n沟道和p沟道增强型GaN器件集成结构的制备方法,包括以下步骤:
步骤1:在洁净的衬底1上利用MOCVD或MBE依次外延生长高阻缓冲层2、n沟道层3、势垒层4、p沟道层5、p型插入层6、p沟阈值调制层7和p沟栅流抑制层8;
步骤2:在样品表面生长刻蚀掩模层9,通过光刻、显影工艺,利用光刻胶定义刻蚀区域,然后刻蚀无光刻胶保护区域的刻蚀掩模层9,通过有机清洗剂去除光刻胶,以剩余刻蚀掩模层9为掩模依次刻蚀无掩模区域的p沟栅流抑制层8、p沟阈值调制层7和p型插入层6;
步骤3:在样品表面淀积刻蚀掩模层10,通过光刻、显影工艺,利用光刻胶定义刻蚀区域,然后刻蚀无光刻胶保护区域的刻蚀掩模层10,通过有机清洗剂去除光刻胶,以剩余刻蚀掩模层10为掩模刻蚀无掩模区域p沟道层5;
步骤4:利用湿法腐蚀的方法,去除刻蚀掩模层9和10,在样品表面淀积选择再生长掩模层11,通过光刻、显影工艺,利用光刻胶定义选择再生长窗口区域,然后刻蚀无光刻胶保护区域的刻蚀再生长掩模层11,通过有机清洗剂去除光刻胶;
步骤5:利用氧等离子体进行表面处理,然后通过酸性和碱性溶液对表面进行表面清洁,然后在样品表面依次外延生长n沟阈值调制层12和n沟栅流抑制层13;
步骤6:利用氢氟酸缓冲溶液在超声下去除选择再生长掩模层11及其上的n沟阈值调制层12和n沟栅流抑制层13;
步骤7:在样品表面旋涂光刻胶掩模14,通过光刻、显影工艺,利用光刻胶定义刻蚀区域,然后刻蚀无光刻胶保护区域的n沟栅流抑制层13;
步骤8:在样品表面淀积p沟器件欧姆接触金属层15,然后利用正胶剥离的方法去除光刻胶掩模14以外的p沟器件欧姆接触金属层15;
步骤9:通过光刻、显影工艺,利用光刻胶定义n沟道器件欧姆接触区域,淀积n沟道器件欧姆接触层16,然后利用正胶剥离的方法去除光刻胶定义n沟道器件欧姆接触区域以外的n沟道器件欧姆接触层16,在惰性气体的保护下进行合金处理;
步骤10:通过光刻、显影工艺,利用光刻胶定义器件隔离区域,利用离子注入技术在势垒层4、n沟道层3和部分高阻缓冲层2中注入高能粒子形成隔离层17;
步骤11:利用有机溶剂在超声下去除离子注入时的光刻胶,利用氮等离子体进行表面处理,随后在样品表面淀积表面钝化层18;
步骤12:通过光刻、显影工艺,利用光刻胶定义n沟道器件和p沟道器件栅接触区域,刻蚀无光刻胶保护区域的表面钝化层18,然后淀积栅金属接触层19,然后利用正胶剥离的方法去除光刻胶定义n沟道器件和p沟道器件栅接触区域以外的栅金属接触层19,在惰性气体的保护下进行低温处理;
步骤13:通过光刻、显影工艺,利用光刻胶定义n沟道器件和p沟道器件欧姆接触压块区域,刻蚀无光刻胶保护区域的表面钝化层18,通过有机清洗剂去除光刻胶。
进一步的,在步骤1、2、3和10中,所述洁净的衬底1为导电或半绝缘的硅、碳化硅、蓝宝石、氮化铝、氮化镓、氧化锌或金刚石;所述高阻缓冲层2为铁、碳或镁掺杂的GaN与AlGaN、AlN组合的多层结构;所述n沟道层3为非故意掺杂的GaN和InGaN的单层或多层组合结构,厚度大于10nm;所述势垒层4为非故意掺杂的AlGaN和InAlGaN的单层或多层组合结构,势垒层禁带宽度高于沟道层,厚度小于30nm;所述p沟道层5为p型轻掺杂的GaN和InGaN的单层或多层组合结构,掺杂浓度低于5E18cm-3,厚度大于10nm;所述p型插入层6为p型轻掺杂的AlGaN或InAlGaN,掺杂浓度低于1E18cm-3,厚度小于10nm;所述p沟阈值调制层7为n型掺杂的GaN和InGaN的单层或多层组合结构,掺杂浓度高于1E19cm-3,厚度大于30nm;所述p沟栅流抑制层8为非故意掺杂GaN和InGaN的单层或多层组合结构,厚度小于50nm。
进一步的,在步骤2和步骤3中,所述刻蚀掩模层9和刻蚀掩模层10为采用热蒸发、溅射或化学气相沉积的Si3N4、SiO2、Al2O3或Al的单层或多层结构,可采用氟基等离子体刻蚀或氢氟酸进行刻蚀。
进一步的,在步骤2、3和7中所述p沟栅流抑制层8、p沟阈值调制层7、p型插入层6、p沟道层5和n沟栅流抑制层13的刻蚀采用氯和氧混合等离子体进行刻蚀,刻蚀功率低于20W。
进一步的,在步骤4中,所述再生长掩模层11为SiO2介质,介质厚度大于再生长材料的2倍。
进一步的,在步骤5中,所述氧等离子体功率大于100W;所述酸性溶液为不含氢氟酸的强酸性溶液;所述碱性溶液为不含金属离子的碱性溶液;在步骤5、6和7所述n沟阈值调制层12和n沟栅流抑制层13为GaN和InGaN的单层或多层组合结构,其中n沟阈值调制层12需要进行p型高掺杂,掺杂浓度高于1E19cm-3,厚度大于50nm,n沟栅流抑制层13非故意掺杂,厚度小于50nm。
进一步的,在步骤8中,所述p沟器件欧姆接触金属层15为Ni、Pt、Au等具有高功函数的金属和Al等具有高电导率金属组成的多层结构,其中具有高功函数的金属和半导体材料直接接触。
进一步的,在步骤9中,所述n沟道器件欧姆接触层16,为Ti、Al、TiN、TaN等具有低功函数的金属和Al、Au等具有高电导率金属组成的多层结构,具有低功函数的金属与半导体材料直接接触,合金在氮气或氩气等惰性气体中开展,处理温度在500度到800度之间。
进一步的,在步骤10中,所述高能粒子为硼、镁等无法形成n型掺杂的元素形成的粒子,注入能量高于30KeV,注入计量高于1E14cm-2。
进一步的,在步骤11中,所述氮等离子体处理功率低于10W;在步骤11到13中,所述表面钝化层18为Si3N4或AlN介质,介质生长时间和氮等离子体处理间隔小于30min。
进一步的,在步骤12中,所述栅金属接触层19为TiN、W、Ni等难容性金属作为第一层的多层结构,第一层金属厚度低于100nm;所述低温处理温度在200到400度之间。
下面结合实施例和附图对本发明的制备方法进行详细说明。
实施例
一种n沟道和p沟道增强型GaN器件集成结构的制备方法,具体步骤如下:
(1)在洁净的导电Si衬底1上利用MOCVD依次外延生长碳掺杂的50nm AlN/500nmAlGaN/500nm GaN高阻缓冲层2,300nm非故意掺杂GaN n沟道层3、15nm AlGaN势垒层4、100nm掺杂浓度2E17cm-3的镁掺杂GaN p沟道层5、3nm掺杂浓度1E17cm-3的镁掺杂AlGaN p型插入层6、50nm掺杂浓度3E19cm-3的硅掺杂InGaN p沟阈值调制层7和30nm非意掺杂GaN p沟栅流抑制层8,如图2(a)所示;
(2)利用PECVD在样品表面生长200nm Si3N4刻蚀掩模层9,通过常规光刻、显影工艺,利用光刻胶定义刻蚀区域,然后利用ICP刻蚀设备,采用六氟化硫刻蚀气体刻蚀无光刻胶保护区域的Si3N4刻蚀掩模层9,通过丙酮、乙醇和去离子水去除光刻胶,以剩余Si3N4刻蚀掩模层9为掩模,利用ICP刻蚀设备,采用氯和氧刻蚀气体,刻蚀功率5W,依次刻蚀无掩模区域p沟栅流抑制层8、p沟阈值调制层7和p型插入层6,如图2(b)所示;
(3)利用PECVD在样品表面淀积100nm SiO2刻蚀掩模层10,通过常规光刻、显影工艺,利用光刻胶定义刻蚀区域,然后利用ICP刻蚀设备,采用六氟化硫刻蚀气体刻蚀无光刻胶保护区域的SiO2刻蚀掩模层10,通过丙酮、乙醇和去离子水去除光刻胶,以剩余SiO2刻蚀掩模层10为掩模,利用ICP刻蚀设备,采用氯刻蚀气体,刻蚀功率5W,刻蚀无掩模区域p沟道层5,如图2(c)所示;
(4)利用氢氟酸和水的混合溶液(体积比1:10)去除Si3N4刻蚀掩模层9和SiO2刻蚀掩模层10,利用PECVD在样品表面淀积300nm SiO2选择再生长掩模层11,通过常规光刻、显影工艺,利用光刻胶定义选择再生长窗口区域,然后利用ICP刻蚀设备,采用六氟化硫刻蚀气体刻蚀无光刻胶保护区域的SiO2刻蚀再生长掩模层11,通过丙酮、乙醇和去离子水去除光刻胶,如图2(d)所示;
(5)利用200W氧等离子体表面处理10分钟,然后用盐酸溶液(浓盐酸(37%)和水体积比1:1)浸泡1分钟,氨水浸泡1分钟,用去离子水冲洗干净吹干,然后利用MOCVD在样品表面依次外延生长100nm掺杂浓度3E19cm-3的镁掺杂GaN n沟阈值调制层12和20nm非故意掺杂GaN n沟栅流抑制层13,如图2(e)所示;
(6)利用氢氟酸缓冲溶液在超声下去除选择SiO2再生长掩模层11及其上的GaN n沟阈值调制层12和GaN n沟栅流抑制层13,如图2(f)所示;
(7)在样品表面旋涂光刻胶掩模14,通过常规光刻、显影工艺,利用光刻胶定义刻蚀区域,然后利用ICP刻蚀设备,采用氯刻蚀气体,刻蚀功率2W,刻蚀无光刻胶保护区域的GaN n沟栅流抑制层13,如图2(g)所示;
(8)利用电子束蒸发台在样品表面淀积30nm Ni/200nm Au p沟器件欧姆接触金属层15,然后利用正胶剥离的方法去除光刻胶掩模14以外的Ni/Au p沟器件欧姆接触金属层15,如图2(h)所示;
(9)通过常规光刻、显影工艺,利用光刻胶定义n沟道器件欧姆接触区域,利用热蒸发等方法淀积20nm Ti/150nm Al/10nm Ti n沟道器件欧姆接触层16,然后利用正胶剥离的方法去除光刻胶定义n沟道器件欧姆接触区域以外的n沟道器件欧姆接触层16,利用热处理设备,在氮气下600度处理1分钟,如图2(i)所示;
(10)通过常规光刻、显影工艺,利用光刻胶定义器件隔离区域,在50KeV下注入4E14cm-2的硼离子到势垒层4、n沟道层3和部分高阻缓冲层2中形成隔离层17,如图2(j)所示;
(11)利用有丙酮和乙醇分别在超声下去除离子注入时的光刻胶,利用RIE设备,在5W的氮等离子体下表面处理1分钟,随后利用PECVD在样品表面淀积300nm Si3N4表面钝化层18,如图2(k)所示;
(12)通过常规光刻、显影工艺,利用光刻胶定义n沟道器件和p沟道器件栅接触区域,利用ICP设备,采用六氟化硫气体刻蚀无光刻胶保护区域的Si3N4表面钝化层18,然后利用磁控溅射台,溅射30nm TiN/100nm Al栅金属接触层19,利用正胶剥离的方法去除光刻胶定义n沟道器件和p沟道器件栅接触区域以外的栅金属接触层19,在氮气保护下300度处理10分钟,如图2(l)所示;
(13)通过常规光刻、显影工艺,利用光刻胶定义n沟道器件和p沟道器件欧姆接触压块区域,利用ICP设备,采用六氟化硫气体刻蚀无光刻胶保护区域的表面钝化层18,通过丙酮和乙醇去除光刻胶,如图2(m)所示。
本发明针对采用MIS结构实现n沟道和p沟道增强型GaN器件集成中存在界面态密度高,容易导致器件阈值电压漂移和可靠性降低的问题,通过采用JFET器件结构来实现n沟道和p沟道增强型GaN器件,基于选择再生长等技术实现了新结构n沟道和p沟道增强型GaN器件集成的方法,具有器件阈值电压均匀性高、稳定性高、与现有GaN微波器件和电力电子器件集成兼容性高的特点,可应用于n沟道和p沟道增强型GaN器件以及逻辑集成电路的研制生产中。
Claims (10)
1.一种n沟道和p沟道增强型GaN器件集成结构的制备方法,其特征在于,包括以下步骤:
步骤1:在洁净的衬底(1)上依次外延生长高阻缓冲层(2)、n沟道层(3)、势垒层(4)、p沟道层(5)、p型插入层(6)、p沟阈值调制层(7)和p沟栅流抑制层(8);
步骤2:在样品表面生长第一刻蚀掩模层(9),通过光刻、显影工艺,利用光刻胶定义刻蚀区域,然后刻蚀无光刻胶保护区域的第一刻蚀掩模层(9),通过有机清洗剂去除光刻胶,以剩余第一刻蚀掩模层(9)为掩模依次刻蚀无掩模区域的p沟栅流抑制层(8)、p沟阈值调制层(7)和p型插入层(6);
步骤3:在样品表面淀积第二刻蚀掩模层(10),通过光刻、显影工艺,利用光刻胶定义刻蚀区域,然后刻蚀无光刻胶保护区域的第二刻蚀掩模层(10),通过有机清洗剂去除光刻胶,以剩余第二刻蚀掩模层(10)为掩模刻蚀无掩模区域p沟道层(5);
步骤4:利用湿法腐蚀的方法,去除第一刻蚀掩模层(9)和第二刻蚀掩模层(10),在样品表面淀积选择再生长掩模层(11),通过光刻、显影工艺,利用光刻胶定义选择再生长窗口区域,然后刻蚀无光刻胶保护区域的刻蚀再生长掩模层(11),通过有机清洗剂去除光刻胶;
步骤5:利用氧等离子体进行表面处理,然后通过酸性和碱性溶液对表面进行表面清洁,然后在样品表面依次外延生长n沟阈值调制层(12)和n沟栅流抑制层(13);
步骤6:利用氢氟酸缓冲溶液在超声下去除选择再生长掩模层(11)及其上的n沟阈值调制层(12)和n沟栅流抑制层(13);
步骤7:在样品表面旋涂光刻胶掩模(14),通过光刻、显影工艺,利用光刻胶定义刻蚀区域,然后刻蚀无光刻胶保护区域的n沟栅流抑制层(13);
步骤8:在样品表面淀积p沟器件欧姆接触金属层(15),然后利用正胶剥离的方法去除光刻胶掩模(14)以外的p沟器件欧姆接触金属层(15);
步骤9:通过光刻、显影工艺,利用光刻胶定义n沟道器件欧姆接触区域,淀积n沟道器件欧姆接触层(16),然后利用正胶剥离的方法去除光刻胶定义n沟道器件欧姆接触区域以外的n沟道器件欧姆接触层(16),在惰性气体的保护下进行合金处理;
步骤10:通过光刻、显影工艺,利用光刻胶定义器件隔离区域,利用离子注入技术在势垒层(4)、n沟道层(3)和部分高阻缓冲层(2)中注入高能粒子形成隔离层(17);
步骤11:利用有机溶剂在超声下去除离子注入时的光刻胶,利用氮等离子体进行表面处理,随后在样品表面淀积表面钝化层(18);
步骤12:通过光刻、显影工艺,利用光刻胶定义n沟道器件和p沟道器件栅接触区域,刻蚀无光刻胶保护区域的表面钝化层(18),然后淀积栅金属接触层(19),然后利用正胶剥离的方法去除光刻胶定义n沟道器件和p沟道器件栅接触区域以外的栅金属接触层(19),在惰性气体的保护下进行低温处理;
步骤13:通过光刻、显影工艺,利用光刻胶定义n沟道器件和p沟道器件欧姆接触压块区域,刻蚀无光刻胶保护区域的表面钝化层(18),通过有机清洗剂去除光刻胶。
2.根据权利要求1所述的n沟道和p沟道增强型GaN器件集成结构的制备方法,其特征在于,在步骤1、2、3和10中,所述洁净的衬底(1)为导电或半绝缘的硅、碳化硅、蓝宝石、氮化铝、氮化镓、氧化锌或金刚石;所述高阻缓冲层(2)为铁、碳或镁掺杂的GaN与AlGaN、AlN组合的多层结构;所述n沟道层(3)为非故意掺杂的GaN和InGaN的单层或多层组合结构,厚度大于10nm;所述势垒层(4)为非故意掺杂的AlGaN和InAlGaN的单层或多层组合结构,势垒层禁带宽度高于沟道层,厚度小于30nm;所述p沟道层(5)为p型轻掺杂的GaN和InGaN的单层或多层组合结构,掺杂浓度低于5E18cm-3,厚度大于10nm;所述p型插入层(6)为p型轻掺杂的AlGaN或InAlGaN,掺杂浓度低于1E18cm-3,厚度小于10nm;所述p沟阈值调制层(7)为n型掺杂的GaN和InGaN的单层或多层组合结构,掺杂浓度高于1E19cm-3,厚度大于30nm;所述p沟栅流抑制层(8)为非故意掺杂GaN和InGaN的单层或多层组合结构,厚度小于50nm。
3.根据权利要求1所述的n沟道和p沟道增强型GaN器件集成结构的制备方法,其特征在于,在步骤2和步骤3中,所述第一刻蚀掩模层(9)和第二刻蚀掩模层(10)为采用热蒸发、溅射或化学气相沉积的Si3N4、SiO2、Al2O3或Al的单层或多层结构,采用氟基等离子体刻蚀或氢氟酸进行刻蚀。
4.根据权利要求1所述的n沟道和p沟道增强型GaN器件集成结构的制备方法,其特征在于,在步骤2、3和7中所述p沟栅流抑制层(8)、p沟阈值调制层(7)、p型插入层(6)、p沟道层(5)和n沟栅流抑制层(13)的刻蚀采用氯和氧混合等离子体进行刻蚀,刻蚀功率低于20W。
5.根据权利要求1所述的n沟道和p沟道增强型GaN器件集成结构的制备方法,其特征在于,在步骤4中,所述再生长掩模层(11)为SiO2介质,介质厚度大于再生长材料的2倍。
6.根据权利要求1所述的n沟道和p沟道增强型GaN器件集成结构的制备方法,其特征在于,在步骤5中,所述氧等离子体功率大于100W;所述酸性溶液为不含氢氟酸的强酸性溶液;所述碱性溶液为不含金属离子的碱性溶液;在步骤5、6和7所述n沟阈值调制层(12)和n沟栅流抑制层(13)为GaN和InGaN的单层或多层组合结构,其中n沟阈值调制层(12)需要进行p型高掺杂,掺杂浓度高于1E19cm-3,厚度大于50nm,n沟栅流抑制层(13)非故意掺杂,厚度小于50nm。
7.根据权利要求1所述的n沟道和p沟道增强型GaN器件集成结构的制备方法,其特征在于,在步骤8中,所述p沟器件欧姆接触金属层(15)为具有高功函数的金属和具有高电导率金属组成的多层结构,其中具有高功函数的金属和半导体材料直接接触;步骤9中,所述n沟道器件欧姆接触层(16)为具有低功函数的金属和具有高电导率金属组成的多层结构,具有低功函数的金属与半导体材料直接接触,合金在惰性气体中开展,处理温度在500度到800度之间。
8.根据权利要求1所述的n沟道和p沟道增强型GaN器件集成结构的制备方法,其特征在于,在步骤10中,所述高能粒子为硼或镁,注入能量高于30KeV,注入计量高于1E14cm-2。
9.根据权利要求1所述的n沟道和p沟道增强型GaN器件集成结构的制备方法,其特征在于,在步骤11中,所述氮等离子体处理功率低于10W;在步骤11到13中,所述表面钝化层(18)为Si3N4或AlN介质,介质生长时间和氮等离子体处理间隔小于30min。
10.根据权利要求1所述的n沟道和p沟道增强型GaN器件集成结构的制备方法,其特征在于,在步骤12中,所述栅金属接触层(19)为TiN、W或Ni作为第一层的多层结构,第一层金属厚度低于100nm;所述低温处理温度在200到400度之间。
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