CN111048459B - 对准晶片的方法、接合晶片的方法以及对准晶片的装置 - Google Patents

对准晶片的方法、接合晶片的方法以及对准晶片的装置 Download PDF

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CN111048459B
CN111048459B CN201910709613.5A CN201910709613A CN111048459B CN 111048459 B CN111048459 B CN 111048459B CN 201910709613 A CN201910709613 A CN 201910709613A CN 111048459 B CN111048459 B CN 111048459B
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朴玄睦
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Samsung Electronics Co Ltd
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Abstract

提供了一种对准晶片的方法、接合晶片的方法以及对准晶片的装置。在对准晶片的方法中，在具有第一对准键的第一晶片上布置具有第二对准键的第二晶片。通过穿过所述第二晶片形成对准孔，以暴露所述第二对准键和所述第一对准键。通过所述对准孔使所述第一对准键和所述第二对准键彼此对准，来将所述第一晶片和所述第二晶片彼此对准。因此，通过所述对准孔暴露的所述第一对准键和所述第二对准键可以被定位在同一条垂直线上，以使所述第一晶片与所述第二晶片精确对准。

Description

对准晶片的方法、接合晶片的方法以及对准晶片的装置
相关申请的交叉引用
通过引用的方式将于2018年10月11日在韩国知识产权局(KIPO)提交的题为“Method of Aligning Wafers,Method of Bonding Wafers Using the Same,andApparatus for Performing the Same”的韩国专利申请No.2018-0121028的整体并入本文。
技术领域
示例实施例涉及对准晶片的方法、使用该方法接合晶片的方法以及用于执行该方法的装置。更具体地，示例实施例涉及使用对准键对准至少两个晶片的对准方法、使用对准方法接合两个晶片的接合方法以及用于执行对准方法和接合方法的装置。
背景技术
通常，当晶片可以接合在一起时，可能需要精确地对准晶片。可以使用对准键(alignment key)使晶片彼此对准。可以将对准键提供给每个晶片。
当可以使用机械对准装置对准晶片时，由于机械对准装置的低精确度，所以使用机械对准装置可能无法精确地对准晶片。光学对准装置可以具有比机械对准装置更高的精确度。然而，当可以使用光学对准装置对准晶片时，晶片也可能彼此对不准。例如，光学对准装置可以包括两台用于拍摄晶片中的对准键的相机。由于图像的误差，晶片可能无法彼此精确地对准。
发明内容
实施例涉及一种对准晶片的方法，包括：在具有第一对准键的第一晶片的上方布置具有第二对准键的第二晶片；通过穿过所述第二晶片形成对准孔，以暴露所述第二对准键和所述第一对准键；以及通过所述对准孔使所述第一对准键和所述第二对准键彼此对准，来将所述第一晶片和所述第二晶片彼此对准。
实施例涉及一种接合晶片的方法，包括：在具有第一对准键的第一晶片上布置具有第二对准键的第二晶片；通过穿过所述第二晶片形成对准孔，以暴露所述第二对准键和所述第一对准键；通过所述对准孔使所述第一对准键和所述第二对准键彼此对准，来将所述第一晶片和所述第二晶片彼此对准；以及将所述第一晶片和所述第二晶片彼此接合。
实施例涉及一种用于对准晶片的装置，包括：钻孔器，所述钻孔器用于通过穿过第二晶片形成对准孔，以暴露所述第二晶片的第二对准键和第一晶片的第一对准键；相机，所述相机用于通过所述对准孔拍摄所述第一对准键和所述第二对准键，以获得所述第一对准键和所述第二对准键的图像；以及致动器，所述致动器用于基于图像移动所述第一晶片和/或所述第二晶片，以使所述第一对准键和所述第二对准键彼此对准。
附图说明
通过参照附图详细描述示例实施例，对于本领域技术人员而言特征将变得显而易见，其中：
图1至图10例示了根据示例实施例的将第一晶片接合到第二晶片的方法中的各阶段的截面图和俯视图；以及
图11例示了用于使图1中的第一晶片和第二晶片彼此对准的装置。
具体实施方式
在下文中，将参照附图详细说明示例实施例。
图1至图10是例示了根据示例实施例的将晶片彼此接合的方法的各阶段的晶片的截面图和俯视图。
参照图1，第一晶片110可以包括可以沿垂直于第一衬底110_1的顶表面的Y方向堆叠的第一衬底110_1和第一绝缘结构110_2。第一绝缘结构110_2可以包括多个第一半导体芯片130。每个第一半导体芯片130可以包括第一接合焊盘(bonding pad)112。第一接合焊盘112可以布置在第一晶片110的第一绝缘结构110_2的上表面上。例如，第一晶片110的第一绝缘结构110_2的上表面可以是有源区域或有源表面。每个第一半导体芯片130可以包括至少一个第一对准键114。第一对准键114可以布置在第一接合焊盘112的周围。例如，第一对准键114可以布置在第一半导体芯片130的边缘部分上。第一对准键114可以具有矩形截面形状。例如，第一对准键114可以具有在X方向上与第一绝缘结构110_2的上表面相邻的侧表面，X方向平行于第一衬底110_1的顶表面。在另一个实施例中，第一对准键114可以具有各种截面形状。
在示例实施例中，第一绝缘结构110_2可以包括不透明的绝缘材料。在这种情况下，第一对准键114可以暴露在第一绝缘结构110_2的上表面的外部，以便通过相机识别第一对准键114。或者，当第一绝缘结构可以包括透明材料时，第一对准键114可以不被暴露，并且可以布置在第一绝缘结构110_2内部。
第二晶片120可以布置在第一晶片110的上方。第二晶片120可以包括可以沿Y方向堆叠的第二绝缘结构120_2和第二衬底120_1。第二晶片120可以包括在第二绝缘结构120_2中的多个第二半导体芯片140。每个第二半导体芯片140可以包括第二接合焊盘122。第二接合焊盘122可以布置在第二晶片120的第二绝缘结构120_2的下表面上。例如，第二绝缘结构120_2的下表面可以是有源区域或有源表面。每个第二半导体芯片140可以包括至少一个第二对准键124。第二对准键124可以布置在第二接合焊盘122的周围。例如，第二对准键124可以布置在第二半导体芯片140的边缘部分上。第二对准键124可以具有与第一对准键114的形状基本相同的形状。第二对准键124可以具有矩形截面形状。在另一个实施例中，第二对准键124可以具有各种截面形状。
在示例实施例中，第二绝缘结构120_2可以包括不透明的绝缘材料。在这种情况下，第二对准键124可以暴露在第二绝缘结构120_2的下表面的外部，以便通过相机识别第二对准键124。或者，当第二绝缘结构120_2可以包括透明材料时，第二对准键124可以不被暴露，并且可以布置在第二绝缘结构120_2内部。
参照图2，至少一个初始对准孔126可以通过穿过第二晶片120来形成。初始对准孔126可以通过穿过第二晶片120的与第二对准键124相邻的边缘部分而垂直形成。例如，初始对准孔126可以沿Y方向穿过第二衬底120_1和第二绝缘结构120_2。初始对准孔126可以从第二绝缘结构120_2的下表面延伸到第二衬底120_1的上表面。因为初始对准孔126可以通过穿过第二晶片120而垂直形成，所以第一晶片110的第一对准键114可以通过第二晶片120的初始对准孔126暴露。例如，第一晶片110的第一对准键114的上表面可以通过第二晶片120的初始对准孔126暴露。然而，因为第二晶片120的初始对准孔126可以在X方向上与第二晶片的第二对准键124相邻，所以第二晶片120的第二对准键124的侧表面可以与第二晶片120的初始对准孔126的内表面相邻地布置。例如，第二晶片120的第二对准键124的侧表面可以不暴露在第二绝缘结构120_2的外部。例如，第二晶片120的初始对准孔126在Y方向上可以不与第一晶片110的第一对准键114交叠。或者，第二晶片120的初始对准孔126可以形成在第二半导体芯片140之间的划片线上。
在示例实施例中，第二晶片120的初始对准孔126可以使用激光钻212形成。例如，参照图11，第二晶片120可以装载到钻孔器210中。钻孔器210中的激光钻212可以通过穿过第二晶片120形成初始对准孔126。
参照图3，第二晶片120的初始对准孔126可以包括布置在第二晶片120的边缘部分的两个孔。或者，第二晶片120的初始对准孔126可以包括一个孔、至少三个孔或更多个孔。例如，初始对准孔126之间的间隙可以是均匀的或是彼此不同的。
参照图4和图5，第二晶片120的初始对准孔126的宽度(或直径)可以扩大或增大以形成对准孔128。对准孔128可以具有闭环形状，例如圆形、矩形或任何多边形。例如，随着对准孔128可以沿Y方向(即，从第二晶片120的下表面到上表面的方向)延伸，对准孔128的宽度(或直径)可以逐渐增大。例如，第二对准键124的上表面和侧表面可以通过第二晶片120的对准孔128暴露。在示例实施例中，第二对准键124的上表面可以通过第二晶片120的对准孔128全部或部分地暴露。因此，第一晶片110的第一对准键114的上表面和侧表面与第二晶片120的第二对准键124的上表面和侧表面可以通过对准孔128暴露。此外，第二晶片120的第二对准键124的底表面可以通过对准孔128全部或部分地暴露。例如，当第一晶片110和第二晶片120可以彼此对准时，第二晶片120的对准孔128在Y方向上可以与第一对准键114的上表面和侧表面交叠。
在示例实施例中，参照图11，可以使用扩展装置(expander)220扩大或增大初始对准孔126的宽度(或直径)。扩展装置220可以包括湿式蚀刻装置。湿式蚀刻装置可以将湿蚀刻溶液涂覆到初始对准孔126的内表面以扩大初始对准孔126的宽度(或直径)。湿蚀刻溶液的涂覆可以包括向初始对准孔126喷射湿蚀刻溶液或者将第二晶片120浸入到可以保存湿蚀刻溶液的湿蚀刻容器中。湿蚀刻溶液可以包括KOH、TMAH等。
参照图6，可以布置在第二晶片120上方的相机232可以拍摄可以通过第二晶片120的对准孔128暴露的第一晶片110的第一对准键114和第二晶片120的第二对准键124。例如，第一晶片110的第一对准键114和第二晶片120的第二对准键124可以通过一个对准孔128暴露，并且第一晶片110的第一对准键114和第二晶片120的第二对准键124可以仅使用一台相机232来拍摄。
致动器234可以基于通过相机232获取的第一对准键114和第二对准键124的图像移动第二晶片120，以将第一对准键114侧表面和第二对准键124的侧表面定位在同一条垂直线上。所述垂直线垂直于例如第一晶片110的顶表面。当第一对准键114的侧表面和第二对准键124的侧表面可以位于一条垂直线时，第一接合焊盘112和第二接合焊盘122可以彼此对准。例如，致动器234可以调整第二晶片120的位置，以使第一对准键114的侧表面与第二对准键124的侧表面在Y方向上对准，使得第一接合焊盘112和第二接合焊盘122可以彼此对准。
在示例实施例中，致动器234可以仅移动第二晶片120。或者，致动器234可以仅移动第一晶片110。此外，致动器234可以移动第一晶片110和第二晶片120两者。致动器234可以包括伺服电动机。
参照图7，在第一晶片110和第二晶片120彼此对准之后，第一晶片110和第二晶片120可以彼此接合。例如，因为第一对准键114和第二对准键124可以在一条垂直线上彼此精确地对准，所以第一接合焊盘112和第二接合焊盘122也可以彼此精确地对准并且可以彼此精准地连接。
参照图8和图9，可以去除第二晶片120的对准孔128所在的边缘部分。例如，可以通过去除第二晶片120的边缘部分来去除第二晶片120的第二对准键124。此外，可以去除第二晶片120的对准孔128。例如，也可以暴露第一晶片110的上边缘表面和第一对准键114的上表面。例如，第二晶片120可以不覆盖第一晶片110的上边缘表面和第一晶片110的第一对准键114的上表面。
参照图10，为了减小每个堆叠封装件的厚度(或者为了使接合的第一晶片110和第二晶片120的厚度最小化)，可以部分地去除第一晶片110的背部和第二晶片120的背部。第一晶片110的划片道和第二晶片120的划片道可以被切割以形成堆叠封装件。例如，每个堆叠封装件可以包括可以接合在一起的一个第一半导体芯片130和一个第二半导体芯片140。
参照图11，用于对准第一晶片110和第二晶片120的装置可以包括钻孔器210、扩展装置220和对准器230。对准器230可以包括相机232和致动器234。钻孔器210、扩展装置220和对准器230可以布置在一个系统中。在这种情况下，在一个系统中的钻孔器210、扩展装置220和对准器230可以仅用于对准晶片110和120。参照图7说明的第一晶片110和第二晶片120的接合工艺可以由对准器230来执行。
根据示例实施例，第二晶片的第二对准键和第一晶片的第一对准键可以同时通过至少一个穿过第二晶片而形成的对准孔暴露。因此，通过至少一个对准孔暴露的第一对准键和第二对准键可以被定位在一条垂直线上，以使第一晶片与第二晶片精确地对准。第一晶片和第二晶片可以通过精确且精准的对准而接合在一起。因此，可以提高彼此接合的第一晶片和第二晶片的焊盘的电连接的可靠性。
本文已经公开了示例实施例，并且尽管采用了特定术语，但是它们仅以一般性和描述性意义来使用和解释，而不是出于限制的目的。在某些情况下，如对于本领域普通技术人员在提交本申请时将显而易见的，结合特定实施例描述的特征、特性和/或元件可以单独使用或与结合其他实施例描述的特征、特性和/或元件组合使用，除非另外特别指出。因此，本领域技术人员将理解的是，在不脱离所附权利要求中阐述的本发明的精神和范围的情况下，可以进行形式和细节上的各种改变。

Claims (15)

1.一种对准晶片的方法，所述方法包括：
在具有第一对准键的第一晶片上方布置具有第二对准键的第二晶片；
通过穿过所述第二晶片形成对准孔，以暴露所述第二对准键和所述第一对准键；以及
通过所述对准孔使所述第一对准键和所述第二对准键彼此对准，来将所述第一晶片和所述第二晶片彼此对准，
其中，所述的形成所述对准孔包括：
通过穿过所述第二晶片形成初始对准孔，以暴露所述第二对准键的侧表面和所述第一对准键的上表面；以及
扩大所述初始对准孔的宽度以形成所述对准孔，从而暴露所述第二对准键的上表面。
2.根据权利要求1所述的方法，其中，所述的形成所述初始对准孔包括使用激光钻对所述第二晶片进行钻孔。
3.根据权利要求1所述的方法，其中，所述的扩大所述初始对准孔的宽度包括对所述初始对准孔的内表面进行湿式蚀刻。
4.根据权利要求1所述的方法，其中，所述的形成所述对准孔包括在所述第二晶片的边缘部分形成所述对准孔。
5.根据权利要求1所述的方法，其中，所述的形成所述对准孔包括在所述第二晶片中形成至少两个对准孔。
6.根据权利要求1所述的方法，其中，所述的使所述第一对准键和所述第二对准键彼此对准包括：
通过所述对准孔拍摄所述第一对准键和所述第二对准键以获得图像；以及
基于所述图像移动所述第一晶片和/或所述第二晶片，以将所述第一对准键和所述第二对准键定位在同一条垂直线上。
7.一种接合晶片的方法，所述方法包括：
在具有第一对准键的第一晶片上方布置具有第二对准键的第二晶片；
通过穿过所述第二晶片形成对准孔，以暴露所述第二对准键和所述第一对准键；
通过所述对准孔使所述第一对准键和所述第二对准键彼此对准，来将所述第一晶片和所述第二晶片彼此对准；以及
将所述第一晶片和所述第二晶片彼此接合，其中，
所述第一对准键包括两个以上的第一对准键；
所述第二对准键包括两个以上的第二对准键；并且
所述的形成所述对准孔包括在所述第二晶片的边缘部分形成至少两个对准孔，其中，所述的形成所述至少两个对准孔包括：
通过穿过所述第二晶片的边缘部分形成至少两个初始对准孔，以暴露所述两个以上的第二对准键的侧表面和所述两个以上的第一对准键的上表面；以及
扩大所述至少两个初始对准孔中的每个初始对准孔的宽度以形成所述至少两个对准孔中的每个对准孔，从而暴露所述两个以上的第二对准键中的每个第二对准键的上表面。
8.根据权利要求7所述的方法，还包括在将所述第一晶片和所述第二晶片彼此接合之后去除所述第二晶片的边缘部分。
9.根据权利要求8所述的方法，其中，所述的去除所述第二晶片的边缘部分包括去除所述两个以上的第二对准键。
10.根据权利要求8所述的方法，还包括部分地去除所述第一晶片的背部和所述第二晶片的背部。
11.根据权利要求7所述的方法，其中，所述的使所述第一对准键和所述第二对准键彼此对准包括：
通过所述对准孔拍摄所述第一对准键和所述第二对准键以获得图像；以及
基于所述图像移动所述第一晶片和/或所述第二晶片，以将所述第一对准键和所述第二对准键定位在同一条垂直线上。
12.一种用于对准晶片的装置，所述装置包括：
钻孔器，所述钻孔器用于通过穿过第二晶片形成初始对准孔，以暴露所述第二晶片的第二对准键的侧表面和第一晶片的第一对准键的上表面；
扩展装置，所述扩展装置用于扩大所述初始对准孔的宽度以形成对准孔，从而暴露所述第二对准键的上表面；
相机，所述相机用于通过所述对准孔拍摄所述第一对准键和所述第二对准键，来获得所述第一对准键和所述第二对准键的图像；以及
致动器，所述致动器用于基于所述图像移动所述第一晶片和/或所述第二晶片，以使所述第一对准键和所述第二对准键彼此对准。
13.根据权利要求12所述的装置，其中，所述钻孔器包括激光钻。
14.根据权利要求12所述的装置，其中，所述扩展装置包括湿式蚀刻装置。
15.根据权利要求12所述的装置，其中，所述致动器包括伺服电动机。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW396399B (en) * 1998-07-24 2000-07-01 United Microelectronics Corp Method of solving chip alignment error
KR100790250B1 (ko) * 2006-08-09 2008-01-02 동부일렉트로닉스 주식회사 정렬 키 어셈블리 및 이의 제조 방법
WO2009066847A1 (en) * 2007-11-20 2009-05-28 Secron Co., Ltd. Method of aligning a wafer and method of manufacturing a flip chip using the same
KR20100078436A (ko) * 2008-12-30 2010-07-08 주식회사 동부하이텍 반도체 소자의 얼라인먼트 방법
US8563403B1 (en) * 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US9748128B1 (en) * 2016-06-01 2017-08-29 Micron Technology, Inc. Systems and methods for wafer alignment
KR20170139263A (ko) * 2016-06-09 2017-12-19 주식회사 디비하이텍 얼라인 키를 내장한 웨이퍼 및 이의 제조 방법

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6085967A (en) 1998-12-28 2000-07-11 Eastman Kodak Company Method of registrably aligning fabricated wafers preceding bonding
TWI272654B (en) 2003-07-18 2007-02-01 Asia Pacific Microsystems Inc Method for keeping the precision of photolithography alignment after wafer bonding
KR100567911B1 (ko) * 2004-11-23 2006-04-05 매그나칩 반도체 유한회사 웨이퍼 얼라인 방법
US7442476B2 (en) 2004-12-27 2008-10-28 Asml Netherlands B.V. Method and system for 3D alignment in wafer scale integration
KR100792525B1 (ko) * 2006-08-11 2008-01-09 삼성전기주식회사 인쇄회로기판 제조방법
KR100926652B1 (ko) 2007-11-08 2009-11-16 세크론 주식회사 웨이퍼 정렬 방법 및 플립칩 제조 방법
US7588993B2 (en) 2007-12-06 2009-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment for backside illumination sensor
KR100981097B1 (ko) 2008-04-24 2010-09-09 엘아이지에이디피 주식회사 불투명 레이어 코팅을 갖는 템플릿 및 그 제조 방법
EP2299472B1 (de) * 2009-09-22 2020-07-08 EV Group E. Thallner GmbH Vorrichtung zum Ausrichten zweier Substrate
US8299584B2 (en) 2010-03-08 2012-10-30 International Business Machines Corporation Alignment of wafers for 3D integration
EP2399863A1 (en) * 2010-06-22 2011-12-28 Valtion Teknillinen Tutkimuskeskus Multi-layer substrate structure and manufacturing method for the same
KR20120098012A (ko) 2011-02-28 2012-09-05 에스케이하이닉스 주식회사 관통실리콘비아를 갖는 반도체 패키지 및 그 제조 방법
TWI409885B (zh) 2011-05-16 2013-09-21 矽品精密工業股份有限公司 具微機電元件之封裝結構及其製法
US8877637B2 (en) 2011-09-16 2014-11-04 Globalfoundries Singapore Pte. Ltd Damascene process for aligning and bonding through-silicon-via based 3D integrated circuit stacks
KR20130102209A (ko) * 2012-03-07 2013-09-17 삼성전자주식회사 웨이퍼 정렬 장치 및 웨이퍼 정렬 방법
US9012265B2 (en) 2012-03-26 2015-04-21 Ge Yi Magnet assisted alignment method for wafer bonding and wafer level chip scale packaging
US9372406B2 (en) * 2012-04-13 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Film portion at wafer edge
US20140370624A1 (en) 2013-06-18 2014-12-18 International Business Machines Corporation Wafer alignment and bonding tool for 3d integration

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW396399B (en) * 1998-07-24 2000-07-01 United Microelectronics Corp Method of solving chip alignment error
KR100790250B1 (ko) * 2006-08-09 2008-01-02 동부일렉트로닉스 주식회사 정렬 키 어셈블리 및 이의 제조 방법
WO2009066847A1 (en) * 2007-11-20 2009-05-28 Secron Co., Ltd. Method of aligning a wafer and method of manufacturing a flip chip using the same
KR20100078436A (ko) * 2008-12-30 2010-07-08 주식회사 동부하이텍 반도체 소자의 얼라인먼트 방법
US8563403B1 (en) * 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US9748128B1 (en) * 2016-06-01 2017-08-29 Micron Technology, Inc. Systems and methods for wafer alignment
KR20170139263A (ko) * 2016-06-09 2017-12-19 주식회사 디비하이텍 얼라인 키를 내장한 웨이퍼 및 이의 제조 방법

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