WO2009066847A1 - Method of aligning a wafer and method of manufacturing a flip chip using the same - Google Patents

Method of aligning a wafer and method of manufacturing a flip chip using the same Download PDF

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Publication number
WO2009066847A1
WO2009066847A1 PCT/KR2008/003624 KR2008003624W WO2009066847A1 WO 2009066847 A1 WO2009066847 A1 WO 2009066847A1 KR 2008003624 W KR2008003624 W KR 2008003624W WO 2009066847 A1 WO2009066847 A1 WO 2009066847A1
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WO
WIPO (PCT)
Prior art keywords
alignment mark
distance
wafer
template
image
Prior art date
Application number
PCT/KR2008/003624
Other languages
French (fr)
Inventor
Jung-Bae Oh
Original Assignee
Secron Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Secron Co., Ltd. filed Critical Secron Co., Ltd.
Publication of WO2009066847A1 publication Critical patent/WO2009066847A1/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/06—Solder feeding devices; Solder melting pans
    • B23K3/0607—Solder feeding devices
    • B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
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    • H01L2924/014—Solder alloys

Definitions

  • the present invention relates to a method of aligning a wafer, and a method of manufacturing a flip chip. More particularly, the present invention relates to a method of aligning a wafer to a template formed of an opaque material, and a method of manufacturing a flip chip using the same.
  • solder bump technologies used in volume production. For example, these include electroplating, solder paste printing, evaporation, the direct attachment of preformed solder spheres, and the like.
  • C4NP controlled collapse chip connection new process
  • spherical solder bumps are formed in cavities of a template and then attached onto bump pads formed on a semiconductor wafer at the reflow temperature of the solder bumps.
  • the template needs to be precisely aligned with the wafer so as to attach the solder bumps formed in the cavities to the bump pads.
  • a conventional template is formed of a transparent material, such as glass and the like
  • the template may be aligned with the wafer without any difficulty.
  • the template formed of the transparent material, such as glass and the like may be easily damaged by external shock or have a short life.
  • the template is formed of an opaque material, it may be difficult to align the template to the wafer, and the solder bumps may not be precisely attached to the bump pads.
  • Example embodiments of the present invention provide a method of precisely and effectively aligning a wafer to a template formed of an opaque material. Further, example embodiments of the present invention provide a method of manufacturing a flip chip using the wafer aligning method as mentioned above.
  • a wafer on which a first alignment mark may be formed may be prepared.
  • a template formed of an opaque material may be prepared.
  • the template may have a through-hole formed at a position corresponding to that of the first alignment mark and a second alignment mark formed at a position spaced apart from the center of the through-hole by a first distance.
  • the wafer and the template may be disposed to be adjacent to each other.
  • a second distance between the first alignment mark observed through the through-hole and the second alignment mark may be measured. The second distance may be compared with the first distance. When the second distance is different from the first distance, at least one of the wafer and the template may be moved to allow the second distance to be substantially equal to the first distance.
  • the template may be formed of metal. Further, at least one of the size, shape, brightness and chroma of the first alignment mark may be different from that of the second alignment mark.
  • a first image of the first alignment mark may be acquired through the through-hole using a first image section which is disposed under the template, and a second image of the second alignment mark may be acquired using a second image section which is disposed adjacent to the first image section. The second distance may be measured between the center of the first alignment mark and the center of the second alignment mark using the first image and the second image.
  • the first distance may be substantially equal to a distance between the center of the first image section and the center of the second image section.
  • allowing the second distance to be substantially equal to the first distance may include at least one of the following steps: rotating at least one of the wafer and the template, and moving at least one of the wafer and the template.
  • one of the first alignment mark and the second alignment mark may have a rectangular shape, and another one of the first alignment mark and the second alignment mark may have a cross shape.
  • a wafer having a plurality of bump pads may be prepared.
  • a first alignment mark may be formed on the wafer.
  • a template formed of an opaque material may be prepared.
  • the template may have cavities formed at surface portions thereof to correspond the bump pads and a through-hole formed at a position corresponding to that of the first alignment mark.
  • a second alignment mark may be formed at a position spaced apart from the center of the through-hole by a first distance.
  • the cavities may be filled with a solder material, and spherical solder bumps may be formed in the cavities by heating the solder material.
  • the wafer and the template may be disposed to be adjacent to each other, and the bump pads of the wafer may be aligned with the solder bumps. Then, the solder bumps may be attached to the bump pads by moving at least one of the wafer and the template.
  • a second distance between the first alignment mark observed through the through-hole and the second alignment mark may be measured, and the second distance may be compared with the first distance.
  • the second distance is different from the first distance, at least one of the wafer and the template may be moved to allow the second distance to be substantially equal to the first distance.
  • a first image of the first alignment mark may be acquired through the through-hole using a first image section which is disposed under the template, and a second image of the second alignment mark may be acquired using a second image section which is disposed adjacent to the first image section.
  • the second distance may be measured between the center of the first alignment mark and the center of the second alignment mark using the first image and the second image.
  • the second distance may be allowed to be substantially equal to the first distance by performing at least one of the following steps: rotating at least one of the wafer and the template, and moving at least one of the wafer and the template.
  • a wafer in case a template is formed of an opaque material, a wafer may be precisely aligned with the template through a through-hole formed in the template.
  • the wafer may be aligned precisely and effectively to the template regardless of changes in the material used for the template, and process efficiency in manufacturing a flip chip may further be improved.
  • FIG. 1 is a schematic view illustrating a wafer, a template and an image section to describe a method of aligning a wafer in accordance with an example embodiment of the present invention
  • FIG. 2 is an enlarged view illustrating a portion confined by a circle 'A' shown in FIG. 1;
  • FIG. 3 is a flowchart illustrating a method of aligning a wafer in accordance with an example embodiment of the present invention
  • FIGS. 4 to 8 are schematic views illustrating the wafer aligning method shown in FIG. 3;
  • FIGS. 9 to 17 are schematic views illustrating a method of manufacturing a flip chip in accordance with some example embodiments of the present invention.
  • first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
  • a first thin film could be termed a second thin film, and, similarly, a second thin film could be termed a first thin film without departing from the teachings of the disclosure.
  • the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
  • the singular forms "a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
  • relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe one element's relationship to other elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower,” can therefore, encompass both an orientation of “lower” and “upper” depending on the particular orientation of the figure.
  • Example embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present invention.
  • FIG. 1 is a schematic view illustrating a wafer, a template and an image section to describe a method of aligning a wafer in accordance with an example embodiment of the present invention
  • FIG. 2 is an enlarged view illustrating a portion confined by a circle 'A' shown in FIG. 1.
  • a wafer 100 may be prepared.
  • a first alignment mark 102 may be formed on the wafer 100.
  • a first alignment mark 102 may be formed on an edge portion of the wafer 100.
  • a plurality of first alignment marks 102 may be formed on edge portions of the wafer 100.
  • four first alignment marks 102 spaced at regular intervals may be formed on edge portions of the wafer 100.
  • the first alignment mark 102 may be an embossed pattern or an engraved pattern.
  • a template 200 may be disposed on the opposite side of the wafer 100.
  • the size of the template 200 may be relatively greater than that of the wafer 100.
  • the template 200 may be formed of an opaque material.
  • the template 200 may be formed of metal.
  • the template 200 may be formed of an opaque material that is not easily damaged by external shock and has a relatively long life.
  • the template 200 may have improved durability in comparison with a template formed of a transparent material such as glass.
  • the template 200 may have a through-hole 202 formed at a position corresponding to that of the first alignment mark 102 of the wafer 100.
  • four through-holes 202 may be formed through the template 200 to correspond to the first alignment marks 102.
  • the template 200 may include a transparent window (not shown) formed at a position corresponding to that of the first alignment mark 102 of the wafer 100.
  • the template 200 may include a plurality of transparent windows corresponding to the plurality of first alignment marks 102 in the same way as the through-holes 202.
  • the transparent window may be formed of a transparent material such as glass.
  • a second alignment mark 204 may be formed on the template 200.
  • the second alignment mark 204 may be spaced apart from the center of the through-hole 202 by a predetermined distance. Referring to FIG. 2, the second alignment mark 204 may be formed at a position spaced apart from the center of the through-hole 202 by a first distance dl.
  • the second alignment mark 204 may be an embossed pattern or an engraved pattern. At least one of the size, shape, brightness and chroma of the first alignment mark 102 may be different from that of the second alignment mark 204. Alternatively, the size, shape, brightness and chroma of the first alignment mark 102 may be the same as those of the second alignment mark 204.
  • a first image section 300 may be disposed under the template 200.
  • the first image section 300 may be disposed under the through-hole 202 formed in the template 200.
  • a vision camera may be used as the first image section 300.
  • the first image section 300 may acquire a first image of the first alignment mark 102 through the through-hole 202 under the template 200.
  • a second image section 400 may be disposed to be adjacent to the first image section 300.
  • the second image section 400 may be disposed under the second alignment mark 202 formed on the template 200. That is, a distance between the first image section 300 and the second image section 400 may be substantially equal to the first distance dl between the center of the through-hole 202 and the second alignment mark 204.
  • a vision camera may be used as the second image section 400.
  • the second image section 400 may acquire a second image of the second alignment 204 formed on the template 200.
  • the wafer 100 may be supported by an upper stage (not shown), and the template 200 may be supported by a lower stage (not shown).
  • the upper stage and the lower stage may move the wafer 100 and the template 200 vertically and horizontally and may rotate the wafer 100 and the template 200.
  • at least one of the upper stage and the lower stage may move at least one of the wafer 100 and template 200 so as to align the wafer 100 and the template 200 with each other.
  • a controller may control the operation of the upper and/or lower stages on the basis of the first and second images of the first alignment mark 102 and the second alignment mark 204 acquired by the first image section 300 and the second image section 400.
  • the wafer 100 and the template 200 may be aligned with each other using position and distance information of the first alignment mark 102 observed through the through-hole 202 and the second alignment mark 204 formed on the template 200.
  • FIG. 3 is a flowchart illustrating a method of aligning a wafer in accordance with an example embodiment of the present invention
  • FIGS. 4 to 8 are schematic views illustrating the wafer aligning method shown in FIG. 3.
  • a wafer 100 may be prepared (step SlOO), a template (200) may be prepared (step S200), and the wafer 100 and the template 200 may be disposed to be adjacent to each other (step S300). Then, positions of the wafer 100 and the template 200 may be sensed (step S400), and the positions of the wafer 100 and the template 200 may be corrected when the wafer 100 and the template 200 are not disposed at predetermined positions (step S500).
  • a wafer 100 on which a first alignment mark 102 is formed may be prepared in step SlOO.
  • a template 200 having a through-hole 202 formed at a position corresponding to that of the first alignment mark 102 may be prepared in step S200.
  • a second alignment mark 204 may be formed at a position spaced apart from the center of the through-hole 202 by a first distance dl.
  • the template 200 may be formed of an opaque material such as metal.
  • the wafer 100 and the template 200 may be disposed to be adjacent to each other.
  • an upper stage (not shown) may move the wafer 100 so as to be adjacent to the template 200.
  • a lower stage (not shown) may move the template 200 so as to be adjacent to the wafer 100.
  • the wafer 100 may be disposed under the template 200, and the wafer 100 and the template 200 may be moved by the upper and lower stages, respectively.
  • a distance between the first alignment mark 102 and the second alignment mark 204 may be measured.
  • a first image section 300 may acquire a first image of the first alignment mark 102 through the through-hole 202 of the template 200
  • a second image section 400 may acquire a second image of the second alignment mark 204.
  • a distance between the first image section 300 and the second image section 400 may be substantially equal to the first distance between the center of the through-hole 202 and the second alignment mark 204.
  • a second distance d2 between the first alignment mark 102 and the second alignment mark 204 may be measured using the first and second images.
  • the second distance d2 may be compared with the first distance dl.
  • the second distance d2 may be compared with the first distance dl by a controller (not shown) connected with the first image section 300 and the second image section 400.
  • the wafer 100 and the template 200 may be moved to allow the second distance d2 to be substantially equal to the first distance dl.
  • at least one of the wafer 100 and the template 200 may be moved in a horizontal direction to allow the second distance d2 to be substantially equal to the first distance dl.
  • the wafer 100 may be misaligned with the template 200.
  • At least one of the wafer 100 and the template 200 may be rotated to align the first alignment mark 102 with the center of the through-hole 202 so that the wafer 100 may be aligned with the template 200. That is, step(s) of rotating at least one of the wafer 100 and the template 200 and/or moving at least one of the wafer 100 and the template 200 may be performed to align the wafer 100 and the template 200 with each other.
  • an image of the first alignment mark 102 and the second alignment mark 204 may be acquired by one image section. That is, an image of the through-hole 202, the first alignment mark 102 and the second alignment mark 204 may be acquired by one image section, and a first distance between the through-hole 202 and the second alignment mark 204 and a second distance between the first alignment mark 102 and the second alignment mark 204 may be measured using the image.
  • the wafer 100 and the template 200 may be aligned with each other by measuring whether the first alignment mark 102 is aligned with the center of the through-hole 202. That is, when the first alignment mark 102 is not aligned with the center of the through-hole 202, the wafer 100 and/or the template 200 may be moved to allow the first alignment mark 102 to be aligned with the center of the through-hole 202 so that the wafer 100 may be aligned with the template 200.
  • the first alignment mark 102 may be shown in a first image 302a acquired by the first image section 300.
  • the first image 302a may have the size and/or shape corresponding to those of the through-hole 202.
  • the first image 302a may have the same size and/or shape as those of the through-hole 202.
  • the through-hole 202 and the first image 302a may have a common central axis.
  • the second alignment mark 204 may be shown in a second image 402a acquired by the second image section 400.
  • the center of the second alignment mark 204 may be disposed on a central portion of the second image 402a.
  • a distance between the center of the first image 302a and the center of the second alignment mark 204 may be substantially equal to the first distance dl.
  • the first distance dl and the second distance d2 are different from each other, and the first alignment mark 102 is spaced apart from the center of the through-hole 202.
  • At least one of the wafer 100 and the template 200 may be rotated so that the first alignment mark 102 and the second alignment mark 204 may be disposed in the same direction.
  • At least one of the wafer 100 and the template 200 may be moved in a first direction, and at least one of the wafer 100 and the template 200 may be moved in a second direction perpendicular to the first direction so that the first distance dl and the second distance d2 may be substantially equal to each other, and the center of the first alignment mark 102 may be aligned with the central axis of the through-hole 202.
  • a first alignment mark 102 may have a cross shape
  • a second alignment mark 205 may have a rectangular shape as shown in FIG. 8.
  • At least one of the wafer 100 and the template 200 may be moved in the first and second directions perpendicular to each other so that a first distance dl between the first alignment mark 102 and the center of the through-hole 202 may be substantially equal to a second distance d2 between the center of the first alignment mark 102 and the center of the second alignment mark 205.
  • a first alignment mark may have a rectangular shape
  • a second alignment mark may have a cross shape. That is, when one of the first alignment mark and the second alignment mark has a rectangular shape, another one of the first alignment mark and the second alignment mark may have a cross shape. Further, both of the first alignment mark and the second alignment mark may have a rectangular shape.
  • the scope of the present invention may not be limited by the shapes of the first alignment mark 102 and the second alignment mark 204 or 205.
  • the second distance d2 between the first alignment mark 102 observed through the through-hole 202, which may be formed in the template 200 formed of the opaque material, and the second alignment mark 204 may be compared with the first distance dl between the second alignment mark 204 and the center of the through-hole 202.
  • At least one of the wafer 100 and the template 200 may be moved or rotated so as to allow the second distance d2 to be substantially equal to the first distance dl.
  • the wafer 100 may be precisely aligned with the template 200.
  • FIGS. 9 to 17 are schematic views illustrating a method of manufacturing a flip chip in accordance with some example embodiments of the present invention.
  • a plurality of semiconductor chips 104 are formed on a wafer 100, and bumps pads 106 are formed on each of the semiconductor chips 104.
  • a protective layer 108 may be formed on the wafer 100 such that the bump pads 106 are exposed.
  • the bump pads may be formed of aluminum, copper, and the like.
  • under-bump metallurgy (UBM) pads 110 may be formed on the bump pads 106.
  • solder bumps which will be described later, may be attached to the UBM pads 110, and the bump pads 106 may thus be electrically connected with the solder bumps.
  • the UBM pads 110 may have a multilayer structure including an adhesive layer, a diffusion barrier layer and a wetting layer.
  • a template 200 may be provided to form solder bumps.
  • a plurality of cavities 206 may be formed at surface portions of the template 200 to correspond with positions of the bump pads 106 formed on the wafer 100. Meanwhile, each of the cavities 206 may have a hemispherical shape. However, the scope of the present invention may not be limited by the shape of the cavities 206.
  • the cavities 206 may be filled with a solder material 208.
  • a method of filling the cavities 206 with the solder material 208 may include a method of filling the cavities 206 with a molten solder material using an injection nozzle, a method using a solder paste and a stencil mask, and the like.
  • Examples of a material that may be used as the solder material 208 may include gold (Au), silver (Ag), tin (Sn), copper (Cu), lead (Pb) or a combination thereof.
  • the solder material 208 filled in the cavities 206 may be heated to form spherical solder bumps 210 or solder balls in the cavities 206.
  • the solder material 208 may be heated to a temperature higher than a melting point of the solder material 208 to thereby form the solder bumps 210.
  • the spherical solder bumps 210 may be positioned on central portions of the cavities 206 and may be solidified at a temperature lower than the melting point or a room temperature.
  • the wafer 100 and the template 200 may be arranged in a vertical direction to be opposite to each other.
  • the UBM pads 110 of the wafer 100 and the solder bumps 210 in the cavities 206 may be opposite to each other in the vertical direction.
  • the wafer 100 may be disposed over the template 200 so as to face the UBM pads 110 downward. Then, the wafer 100 may be moved downward to attach the solder bumps 210 to the UBM pads 110.
  • the solder bumps 210 may be attached by an adhesive force of the UBM pads 210.
  • the wafer 100 may be moved upward. As a result, the solder bumps 210 may be transferred to the wafer 100.
  • the template 200 may be moved to transfer the solder bumps 210 to the UBM pads 110 of the wafer 100.
  • the template 200 or the wafer 100 may be moved upward or downward to transfer the solder bumps 210 to the UBM pads 110 of the wafer 100.
  • the solder bumps 210 may be easily attached to the UBM pads 110 of the wafer 100 and may be easily removed from the template 200 due to the weight of the solder bumps 210.
  • the various methods may be used to transfer the solder bumps 210 to the UBM pads 110 of the wafer 100.
  • a dicing process may be performed to individualize semiconductor chips 104 from the wafer 100 after the solder bumps 210 are transferred to the wafer 100.
  • the solder bumps 210 on the individualized semiconductor chip 104 may be electrically connected to electrodes of a substrate 400 to manufacture a flip chip.
  • the solder bumps 210 are connected to the UBM pads 110 of the semiconductor chip 104, and the semiconductor chip 104 may thus be electrically connected to the substrate 400 through the solder bumps 210.
  • the semiconductor chip 104 may be attached to the substrate 400 at a solder reflow temperature of about 80 to about 200 0 C.
  • the solder reflow temperature may be determined on the basis of the melting point of the solder bumps 210. Particularly, the solder reflow temperature may be about 150 to about 180 0 C.
  • the template 200 formed of the opaque material and the wafer 100 may be precisely arranged with respect to each other, and process efficiency may thus be improved in manufacturing the flip chip. Further, productivity and throughput may be improved in manufacturing the flip chip.
  • the template when a template is formed of an opaque material, the template may be aligned with the wafer using an alignment mark observed through a through-hole, which may be formed in the template.
  • the template and the wafer may be precisely aligned with each other, and the step of transferring solder bumps to the wafer, which may be subsequently performed, may be effectively performed.
  • process efficiency may be improved as a whole, and productivity and throughput may thus be improved in manufacturing the flip chip.

Abstract

In a method of aligning a wafer and a method of manufacturing a flip chip, a wafer on which a first alignment mark is formed and a template formed of an opaque material is prepared. The template has a through-hole formed at a position corresponding to that of the first alignment mark and a second alignment mark formed at a position spaced apart from the center of the through-hole by a first distance. The wafer and the template are disposed to be adjacent to each other, and a second distance between the first alignment mark observed through the through-hole and the second alignment mark is measured. After comparing the second distance with the first distance, and when the second distance is different from the first distance, at least one of the wafer and the template is moved to allow the second distance to be equal to the first distance.

Description

METHOD OF ALIGNING A WAFER AND METHOD OF MANUFACTURING A FLIP CHIP USING THE SAME
Technical Field The present invention relates to a method of aligning a wafer, and a method of manufacturing a flip chip. More particularly, the present invention relates to a method of aligning a wafer to a template formed of an opaque material, and a method of manufacturing a flip chip using the same.
Background Art
Nowadays, microelectronic packaging technology is increasingly moving from wire bonds to solder bumps as the method of interconnection. There are various solder bump technologies used in volume production. For example, these include electroplating, solder paste printing, evaporation, the direct attachment of preformed solder spheres, and the like.
Particularly, controlled collapse chip connection new process (C4NP) technology, which was proposed by IBM, has lately attracted considerable attention by enabling fine pitch bumping at low cost and improving the reliability of semiconductor devices. Examples of the C4NP technology are disclosed in U.S. Patent Nos. 5,607,099, 5,775,569, 6,025,258, etc.
According to the C4NP technology, spherical solder bumps are formed in cavities of a template and then attached onto bump pads formed on a semiconductor wafer at the reflow temperature of the solder bumps. Thus, the template needs to be precisely aligned with the wafer so as to attach the solder bumps formed in the cavities to the bump pads.
Here, since a conventional template is formed of a transparent material, such as glass and the like, the template may be aligned with the wafer without any difficulty. However, there is a problem in that the template formed of the transparent material, such as glass and the like, may be easily damaged by external shock or have a short life. Meanwhile, when the template is formed of an opaque material, it may be difficult to align the template to the wafer, and the solder bumps may not be precisely attached to the bump pads.
Disclosure of the Invention Technical Problem
Example embodiments of the present invention provide a method of precisely and effectively aligning a wafer to a template formed of an opaque material. Further, example embodiments of the present invention provide a method of manufacturing a flip chip using the wafer aligning method as mentioned above. Technical Solution
In a method of aligning a wafer according to some example embodiments of the present invention, a wafer on which a first alignment mark may be formed may be prepared. A template formed of an opaque material may be prepared. The template may have a through-hole formed at a position corresponding to that of the first alignment mark and a second alignment mark formed at a position spaced apart from the center of the through-hole by a first distance. The wafer and the template may be disposed to be adjacent to each other. A second distance between the first alignment mark observed through the through-hole and the second alignment mark may be measured. The second distance may be compared with the first distance. When the second distance is different from the first distance, at least one of the wafer and the template may be moved to allow the second distance to be substantially equal to the first distance.
In some example embodiments of the present invention, the template may be formed of metal. Further, at least one of the size, shape, brightness and chroma of the first alignment mark may be different from that of the second alignment mark. In some example embodiments of the present invention, in measuring the second distance, a first image of the first alignment mark may be acquired through the through-hole using a first image section which is disposed under the template, and a second image of the second alignment mark may be acquired using a second image section which is disposed adjacent to the first image section. The second distance may be measured between the center of the first alignment mark and the center of the second alignment mark using the first image and the second image.
In some example embodiments of the present invention, the first distance may be substantially equal to a distance between the center of the first image section and the center of the second image section.
In some example embodiments of the present invention, allowing the second distance to be substantially equal to the first distance may include at least one of the following steps: rotating at least one of the wafer and the template, and moving at least one of the wafer and the template.
In some example embodiments of the present invention, one of the first alignment mark and the second alignment mark may have a rectangular shape, and another one of the first alignment mark and the second alignment mark may have a cross shape. In a method of manufacturing a flip chip according to some example embodiments of the present invention, a wafer having a plurality of bump pads may be prepared. A first alignment mark may be formed on the wafer. A template formed of an opaque material may be prepared. The template may have cavities formed at surface portions thereof to correspond the bump pads and a through-hole formed at a position corresponding to that of the first alignment mark. A second alignment mark may be formed at a position spaced apart from the center of the through-hole by a first distance. The cavities may be filled with a solder material, and spherical solder bumps may be formed in the cavities by heating the solder material. The wafer and the template may be disposed to be adjacent to each other, and the bump pads of the wafer may be aligned with the solder bumps. Then, the solder bumps may be attached to the bump pads by moving at least one of the wafer and the template.
In some example embodiments of the present invention, in aligning the bump pads of the wafer to the solder bumps, a second distance between the first alignment mark observed through the through-hole and the second alignment mark may be measured, and the second distance may be compared with the first distance. When the second distance is different from the first distance, at least one of the wafer and the template may be moved to allow the second distance to be substantially equal to the first distance.
In some example embodiments of the present invention, a first image of the first alignment mark may be acquired through the through-hole using a first image section which is disposed under the template, and a second image of the second alignment mark may be acquired using a second image section which is disposed adjacent to the first image section. The second distance may be measured between the center of the first alignment mark and the center of the second alignment mark using the first image and the second image.
In some example embodiments of the present invention, the second distance may be allowed to be substantially equal to the first distance by performing at least one of the following steps: rotating at least one of the wafer and the template, and moving at least one of the wafer and the template. Advantageous Effects
According to the example embodiments of the present invention, in case a template is formed of an opaque material, a wafer may be precisely aligned with the template through a through-hole formed in the template. Thus, the wafer may be aligned precisely and effectively to the template regardless of changes in the material used for the template, and process efficiency in manufacturing a flip chip may further be improved. Brief Description of the Drawings
Example embodiments of the present invention will become readily apparent along with the following detailed description when considered in conjunction with the accompanying drawings, wherein: FIG. 1 is a schematic view illustrating a wafer, a template and an image section to describe a method of aligning a wafer in accordance with an example embodiment of the present invention;
FIG. 2 is an enlarged view illustrating a portion confined by a circle 'A' shown in FIG. 1; FIG. 3 is a flowchart illustrating a method of aligning a wafer in accordance with an example embodiment of the present invention;
FIGS. 4 to 8 are schematic views illustrating the wafer aligning method shown in FIG. 3; and
FIGS. 9 to 17 are schematic views illustrating a method of manufacturing a flip chip in accordance with some example embodiments of the present invention.
Best Mode for Carrying Out the Invention
Embodiments of the present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.
It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first thin film could be termed a second thin film, and, similarly, a second thin film could be termed a first thin film without departing from the teachings of the disclosure. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising" or "includes" and/or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to other elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The exemplary term "lower," can therefore, encompass both an orientation of "lower" and "upper" depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The exemplary terms "below" or "beneath" can, therefore, encompass both an orientation of above and below.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Example embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present invention.
FIG. 1 is a schematic view illustrating a wafer, a template and an image section to describe a method of aligning a wafer in accordance with an example embodiment of the present invention, and FIG. 2 is an enlarged view illustrating a portion confined by a circle 'A' shown in FIG. 1.
Referring to FIG. 1, a wafer 100 may be prepared. A first alignment mark 102 may be formed on the wafer 100. For example, a first alignment mark 102 may be formed on an edge portion of the wafer 100. Alternatively, a plurality of first alignment marks 102 may be formed on edge portions of the wafer 100. In accordance with some example embodiments of the present invention, four first alignment marks 102 spaced at regular intervals may be formed on edge portions of the wafer 100. For example, the first alignment mark 102 may be an embossed pattern or an engraved pattern.
A template 200 may be disposed on the opposite side of the wafer 100. The size of the template 200 may be relatively greater than that of the wafer 100. In accordance with some example embodiments of the present, the template 200 may be formed of an opaque material. For example, the template 200 may be formed of metal. Further, the template 200 may be formed of an opaque material that is not easily damaged by external shock and has a relatively long life. Thus, the template 200 may have improved durability in comparison with a template formed of a transparent material such as glass. However, it may be difficult to align the wafer 100 to the template 200 because the template 200 is opaque.
The template 200 may have a through-hole 202 formed at a position corresponding to that of the first alignment mark 102 of the wafer 100. In accordance with some example embodiments of the present invention, in a case where four first alignment marks 102 are formed on edge portions of the wafer 100, four through-holes 202 may be formed through the template 200 to correspond to the first alignment marks 102.
Meanwhile, the template 200 may include a transparent window (not shown) formed at a position corresponding to that of the first alignment mark 102 of the wafer 100. Alternatively, the template 200 may include a plurality of transparent windows corresponding to the plurality of first alignment marks 102 in the same way as the through-holes 202. Here, the transparent window may be formed of a transparent material such as glass.
A second alignment mark 204 may be formed on the template 200. In some example embodiments of the present invention, the second alignment mark 204 may be spaced apart from the center of the through-hole 202 by a predetermined distance. Referring to FIG. 2, the second alignment mark 204 may be formed at a position spaced apart from the center of the through-hole 202 by a first distance dl. The second alignment mark 204 may be an embossed pattern or an engraved pattern. At least one of the size, shape, brightness and chroma of the first alignment mark 102 may be different from that of the second alignment mark 204. Alternatively, the size, shape, brightness and chroma of the first alignment mark 102 may be the same as those of the second alignment mark 204. A first image section 300 may be disposed under the template 200. For example, the first image section 300 may be disposed under the through-hole 202 formed in the template 200. In accordance with some example embodiments of the present invention, a vision camera may be used as the first image section 300. For example, the first image section 300 may acquire a first image of the first alignment mark 102 through the through-hole 202 under the template 200.
A second image section 400 may be disposed to be adjacent to the first image section 300. For example, the second image section 400 may be disposed under the second alignment mark 202 formed on the template 200. That is, a distance between the first image section 300 and the second image section 400 may be substantially equal to the first distance dl between the center of the through-hole 202 and the second alignment mark 204. For example, a vision camera may be used as the second image section 400. The second image section 400 may acquire a second image of the second alignment 204 formed on the template 200. Meanwhile, the wafer 100 may be supported by an upper stage (not shown), and the template 200 may be supported by a lower stage (not shown). The upper stage and the lower stage may move the wafer 100 and the template 200 vertically and horizontally and may rotate the wafer 100 and the template 200. Thus, in a case where the wafer 100 and the template 200 are misaligned with each other, at least one of the upper stage and the lower stage may move at least one of the wafer 100 and template 200 so as to align the wafer 100 and the template 200 with each other.
Further, a controller (not shown) may control the operation of the upper and/or lower stages on the basis of the first and second images of the first alignment mark 102 and the second alignment mark 204 acquired by the first image section 300 and the second image section 400.
As described above, when the template 200 is formed of the opaque material, the wafer 100 and the template 200 may be aligned with each other using position and distance information of the first alignment mark 102 observed through the through-hole 202 and the second alignment mark 204 formed on the template 200.
FIG. 3 is a flowchart illustrating a method of aligning a wafer in accordance with an example embodiment of the present invention, and FIGS. 4 to 8 are schematic views illustrating the wafer aligning method shown in FIG. 3.
Referring to FIGS. 1 to 3, in a method of aligning a wafer according to an example embodiment of the present invention, a wafer 100 may be prepared (step SlOO), a template (200) may be prepared (step S200), and the wafer 100 and the template 200 may be disposed to be adjacent to each other (step S300). Then, positions of the wafer 100 and the template 200 may be sensed (step S400), and the positions of the wafer 100 and the template 200 may be corrected when the wafer 100 and the template 200 are not disposed at predetermined positions (step S500).
In detail, a wafer 100 on which a first alignment mark 102 is formed may be prepared in step SlOO. A template 200 having a through-hole 202 formed at a position corresponding to that of the first alignment mark 102 may be prepared in step S200. Here, a second alignment mark 204 may be formed at a position spaced apart from the center of the through-hole 202 by a first distance dl. In accordance with some example embodiments of the present invention, the template 200 may be formed of an opaque material such as metal.
In step S300, the wafer 100 and the template 200 may be disposed to be adjacent to each other. For example, an upper stage (not shown) may move the wafer 100 so as to be adjacent to the template 200. Alternatively, a lower stage (not shown) may move the template 200 so as to be adjacent to the wafer 100. Further, the wafer 100 may be disposed under the template 200, and the wafer 100 and the template 200 may be moved by the upper and lower stages, respectively.
In step S400, a distance between the first alignment mark 102 and the second alignment mark 204 may be measured. In detail, a first image section 300 may acquire a first image of the first alignment mark 102 through the through-hole 202 of the template 200, and a second image section 400 may acquire a second image of the second alignment mark 204. A distance between the first image section 300 and the second image section 400 may be substantially equal to the first distance between the center of the through-hole 202 and the second alignment mark 204. Then, a second distance d2 between the first alignment mark 102 and the second alignment mark 204 may be measured using the first and second images.
In step S500, the second distance d2 may be compared with the first distance dl. Here, the second distance d2 may be compared with the first distance dl by a controller (not shown) connected with the first image section 300 and the second image section 400.
When the second distance d2 is different from the first distance dl, at least one of the wafer 100 and the template 200 may be moved to allow the second distance d2 to be substantially equal to the first distance dl. For example, at least one of the wafer 100 and the template 200 may be moved in a horizontal direction to allow the second distance d2 to be substantially equal to the first distance dl. When the second distance d2 is substantially equal to the first distance dl, but the first alignment mark 102 is misaligned with the center of the through-hole 202, the wafer 100 may be misaligned with the template 200. In this case, at least one of the wafer 100 and the template 200 may be rotated to align the first alignment mark 102 with the center of the through-hole 202 so that the wafer 100 may be aligned with the template 200. That is, step(s) of rotating at least one of the wafer 100 and the template 200 and/or moving at least one of the wafer 100 and the template 200 may be performed to align the wafer 100 and the template 200 with each other.
As described above, although the wafer 100 and the template 200 are aligned with each other using the first distance dl and the second distance d2, which is measured using the first image of the first alignment mark 102 and the second image of the second alignment mark 204, an image of the first alignment mark 102 and the second alignment mark 204 may be acquired by one image section. That is, an image of the through-hole 202, the first alignment mark 102 and the second alignment mark 204 may be acquired by one image section, and a first distance between the through-hole 202 and the second alignment mark 204 and a second distance between the first alignment mark 102 and the second alignment mark 204 may be measured using the image.
Further, the wafer 100 and the template 200 may be aligned with each other by measuring whether the first alignment mark 102 is aligned with the center of the through-hole 202. That is, when the first alignment mark 102 is not aligned with the center of the through-hole 202, the wafer 100 and/or the template 200 may be moved to allow the first alignment mark 102 to be aligned with the center of the through-hole 202 so that the wafer 100 may be aligned with the template 200. Referring to FIG. 4, the first alignment mark 102 may be shown in a first image 302a acquired by the first image section 300. For example, the first image 302a may have the size and/or shape corresponding to those of the through-hole 202. For example, the first image 302a may have the same size and/or shape as those of the through-hole 202. Further, the through-hole 202 and the first image 302a may have a common central axis.
The second alignment mark 204 may be shown in a second image 402a acquired by the second image section 400. The center of the second alignment mark 204 may be disposed on a central portion of the second image 402a. In some example embodiments of the present invention, a distance between the center of the first image 302a and the center of the second alignment mark 204 may be substantially equal to the first distance dl. As shown in figures, the first distance dl and the second distance d2 are different from each other, and the first alignment mark 102 is spaced apart from the center of the through-hole 202.
Referring to FIGS. 5 to 7, at least one of the wafer 100 and the template 200 may be rotated so that the first alignment mark 102 and the second alignment mark 204 may be disposed in the same direction.
At least one of the wafer 100 and the template 200 may be moved in a first direction, and at least one of the wafer 100 and the template 200 may be moved in a second direction perpendicular to the first direction so that the first distance dl and the second distance d2 may be substantially equal to each other, and the center of the first alignment mark 102 may be aligned with the central axis of the through-hole 202. Meanwhile, in accordance with another example embodiment of the present invention, a first alignment mark 102 may have a cross shape, and a second alignment mark 205 may have a rectangular shape as shown in FIG. 8. At least one of the wafer 100 and the template 200 may be moved in the first and second directions perpendicular to each other so that a first distance dl between the first alignment mark 102 and the center of the through-hole 202 may be substantially equal to a second distance d2 between the center of the first alignment mark 102 and the center of the second alignment mark 205.
Alternatively, a first alignment mark may have a rectangular shape, and a second alignment mark may have a cross shape. That is, when one of the first alignment mark and the second alignment mark has a rectangular shape, another one of the first alignment mark and the second alignment mark may have a cross shape. Further, both of the first alignment mark and the second alignment mark may have a rectangular shape. However, the scope of the present invention may not be limited by the shapes of the first alignment mark 102 and the second alignment mark 204 or 205.
As described above, the second distance d2 between the first alignment mark 102 observed through the through-hole 202, which may be formed in the template 200 formed of the opaque material, and the second alignment mark 204 may be compared with the first distance dl between the second alignment mark 204 and the center of the through-hole 202. At least one of the wafer 100 and the template 200 may be moved or rotated so as to allow the second distance d2 to be substantially equal to the first distance dl. As a result, even though the template 200 is formed of the opaque material, the wafer 100 may be precisely aligned with the template 200.
FIGS. 9 to 17 are schematic views illustrating a method of manufacturing a flip chip in accordance with some example embodiments of the present invention.
Referring to FIGS. 9 and 10, a plurality of semiconductor chips 104 are formed on a wafer 100, and bumps pads 106 are formed on each of the semiconductor chips 104. For example, a protective layer 108 may be formed on the wafer 100 such that the bump pads 106 are exposed. The bump pads may be formed of aluminum, copper, and the like. Further, under-bump metallurgy (UBM) pads 110 may be formed on the bump pads 106. For example, solder bumps, which will be described later, may be attached to the UBM pads 110, and the bump pads 106 may thus be electrically connected with the solder bumps. The UBM pads 110 may have a multilayer structure including an adhesive layer, a diffusion barrier layer and a wetting layer.
Referring to FIGS. 11 and 12, a template 200 may be provided to form solder bumps. A plurality of cavities 206 may be formed at surface portions of the template 200 to correspond with positions of the bump pads 106 formed on the wafer 100. Meanwhile, each of the cavities 206 may have a hemispherical shape. However, the scope of the present invention may not be limited by the shape of the cavities 206.
Referring to FIG. 13, the cavities 206 may be filled with a solder material 208. Examples of a method of filling the cavities 206 with the solder material 208 may include a method of filling the cavities 206 with a molten solder material using an injection nozzle, a method using a solder paste and a stencil mask, and the like. Examples of a material that may be used as the solder material 208 may include gold (Au), silver (Ag), tin (Sn), copper (Cu), lead (Pb) or a combination thereof.
Referring to FIG. 14, the solder material 208 filled in the cavities 206 may be heated to form spherical solder bumps 210 or solder balls in the cavities 206. For example, the solder material 208 may be heated to a temperature higher than a melting point of the solder material 208 to thereby form the solder bumps 210.
The spherical solder bumps 210 may be positioned on central portions of the cavities 206 and may be solidified at a temperature lower than the melting point or a room temperature. Referring to FIGS. 15 and 16, the wafer 100 and the template 200 may be arranged in a vertical direction to be opposite to each other. For example, the UBM pads 110 of the wafer 100 and the solder bumps 210 in the cavities 206 may be opposite to each other in the vertical direction. The wafer 100 may be disposed over the template 200 so as to face the UBM pads 110 downward. Then, the wafer 100 may be moved downward to attach the solder bumps 210 to the UBM pads 110. Here, the solder bumps 210 may be attached by an adhesive force of the UBM pads 210. After the solder bumps 210 are attached to the UBM pads 210, the wafer 100 may be moved upward. As a result, the solder bumps 210 may be transferred to the wafer 100. Alternatively, when the wafer 100 is disposed over the template 200 as described above, the template 200 may be moved to transfer the solder bumps 210 to the UBM pads 110 of the wafer 100.
Further, when the template 200 is disposed over the wafer 100, the template 200 or the wafer 100 may be moved upward or downward to transfer the solder bumps 210 to the UBM pads 110 of the wafer 100. In this case, the solder bumps 210 may be easily attached to the UBM pads 110 of the wafer 100 and may be easily removed from the template 200 due to the weight of the solder bumps 210. As described above, the various methods may be used to transfer the solder bumps 210 to the UBM pads 110 of the wafer 100.
Meanwhile, a dicing process may be performed to individualize semiconductor chips 104 from the wafer 100 after the solder bumps 210 are transferred to the wafer 100. Referring to FIG. 17, the solder bumps 210 on the individualized semiconductor chip 104 may be electrically connected to electrodes of a substrate 400 to manufacture a flip chip. The solder bumps 210 are connected to the UBM pads 110 of the semiconductor chip 104, and the semiconductor chip 104 may thus be electrically connected to the substrate 400 through the solder bumps 210.
The semiconductor chip 104 may be attached to the substrate 400 at a solder reflow temperature of about 80 to about 2000C. The solder reflow temperature may be determined on the basis of the melting point of the solder bumps 210. Particularly, the solder reflow temperature may be about 150 to about 1800C.
According to the example embodiments of the present invention as described above, the template 200 formed of the opaque material and the wafer 100 may be precisely arranged with respect to each other, and process efficiency may thus be improved in manufacturing the flip chip. Further, productivity and throughput may be improved in manufacturing the flip chip.
Industrial Applicability
In a method of aligning a wafer and an apparatus for manufacturing a flip chip in accordance with the example embodiments of the present invention, when a template is formed of an opaque material, the template may be aligned with the wafer using an alignment mark observed through a through-hole, which may be formed in the template. Thus, the template and the wafer may be precisely aligned with each other, and the step of transferring solder bumps to the wafer, which may be subsequently performed, may be effectively performed. As a result, process efficiency may be improved as a whole, and productivity and throughput may thus be improved in manufacturing the flip chip.
Although the example embodiments of the present invention have been described, it is understood that the present invention should not be limited to these example embodiments but various changes and modifications can be made by those skilled in the art within the spirit and scope of the present invention as hereinafter claimed.

Claims

[CLAIMS]
[Claim 1]
A method of aligning a wafer, comprising: preparing a wafer on which a first alignment mark is formed; preparing a template formed of an opaque material and having a through-hole formed at a position corresponding to that of the first alignment mark and a second alignment mark formed at a position spaced apart from a center of the through-hole by a first distance; disposing the wafer and the template to be adjacent to each other; measuring a second distance between the first alignment mark observed through the through-hole and the second alignment mark; comparing the second distance with the first distance; and allowing the second distance to be substantially equal to the first distance by moving at least one of the wafer and the template when the second distance is different from the first distance.
[Claim 2]
The method of claim 1, wherein the template is formed of metal.
[Claim 3]
The method of claim 1, wherein at least one of size, shape, brightness and chroma of the first alignment mark is different from that of the second alignment mark.
[Claim 4]
The method of claim 1, wherein measuring the second distance comprises: acquiring a first image of the first alignment mark through the through-hole using a first image section which is disposed under the template; acquiring a second image of the second alignment mark using a second image section which is disposed adjacent to the first image section; and measuring the second distance between a center of the first alignment mark and a center of the second alignment mark using the first image and the second image.
[Claim 5]
The method of claim 4, wherein the first distance is substantially equal to a distance between a center of the first image section and a center of the second image section.
[Claim 6]
The method of claim 1, wherein allowing the second distance to be substantially equal to the first distance comprises at least one of following steps: rotating at least one of the wafer and the template, and moving at least one of the wafer and the template.
[Claim 7]
The method of claim 1, wherein one of the first alignment mark and the second alignment mark has a rectangular shape, and another one of the first alignment mark and the second alignment mark has a cross shape.
[Claim 8]
A method of manufacturing a flip chip, comprising: preparing a wafer on which a first alignment mark is formed, the wafer having a plurality of bump pads; preparing a template formed of an opaque material and having cavities formed at surface portions thereof to correspond the bump pads, a through-hole formed at a position corresponding to that of the first alignment mark and a second alignment mark formed at a position spaced apart from a center of the through-hole by a first distance; filling the cavities with a solder material; forming spherical solder bumps in the cavities by heating the solder material; disposing the wafer and the template to be adjacent to each other; aligning the bump pads of the wafer to the solder bumps; and attaching the solder bumps to the bump pads by moving at least one of the wafer and the template.
[Claim 9]
The method of claim 8, wherein aligning the bump pads of the wafer to the solder bumps comprises: measuring a second distance between the first alignment mark observed through the through-hole and the second alignment mark; comparing the second distance with the first distance; and allowing the second distance to be substantially equal to the first distance by moving at least one of the wafer and the template when the second distance is different from the first distance.
[Claim 10]
The method of claim 9, wherein measuring the second distance comprises: acquiring a first image of the first alignment mark through the through-hole using a first image section which is disposed under the template; acquiring a second image of the second alignment mark using a second image section which is disposed adjacent to the first image section; and measuring the second distance between a center of the first alignment mark and a center of the second alignment mark using the first image and the second image. [Claim 11]
The method of claim 9, wherein allowing the second distance to be substantially equal to the first distance comprises at least one of following steps: rotating at least one of the wafer and the template, and moving at least one of the wafer and the template.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102934216A (en) * 2010-05-04 2013-02-13 韩美半导体株式会社 Method for aligning semiconductor materials
CN103198035A (en) * 2013-02-28 2013-07-10 北京优纳科技有限公司 Position alignment method and position alignment system
CN105489620A (en) * 2014-10-03 2016-04-13 株式会社东芝 Method for manufacturing solid-state imaging device and method for manufacturing camera module
US20190279892A1 (en) * 2016-06-01 2019-09-12 Micron Technology, Inc. Systems and methods for wafer alignment
US20200118964A1 (en) * 2018-10-11 2020-04-16 Samsung Electronics Co., Ltd. Method of aligning wafers, method of bonding wafers using the same, and apparatus for performing the same
CN114628299A (en) * 2022-03-16 2022-06-14 江苏京创先进电子科技有限公司 Wafer centering confirmation method and Taizhou ring cutting method

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100981097B1 (en) * 2008-04-24 2010-09-09 엘아이지에이디피 주식회사 Template having Opaque Layer Coating and Manufacturing Method thereof
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CN115295534B (en) * 2022-10-08 2023-02-03 合肥本源量子计算科技有限责任公司 Flip chip and alignment method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000200751A (en) * 1998-12-30 2000-07-18 Samsung Electronics Co Ltd Semiconductor wafer containing alignment mark for aligning wafer on aligner, aligning system for generating alignment signal from alignment mark, and method of determining wafer alignment
KR20030092914A (en) * 2002-05-31 2003-12-06 삼성전자주식회사 Device and mark alignment method for flip chip bonder comprising up and down mark
US6946322B2 (en) * 2002-07-25 2005-09-20 Hrl Laboratories, Llc Large area printing method for integrating device and circuit components

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000200751A (en) * 1998-12-30 2000-07-18 Samsung Electronics Co Ltd Semiconductor wafer containing alignment mark for aligning wafer on aligner, aligning system for generating alignment signal from alignment mark, and method of determining wafer alignment
KR20030092914A (en) * 2002-05-31 2003-12-06 삼성전자주식회사 Device and mark alignment method for flip chip bonder comprising up and down mark
US6946322B2 (en) * 2002-07-25 2005-09-20 Hrl Laboratories, Llc Large area printing method for integrating device and circuit components

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102934216A (en) * 2010-05-04 2013-02-13 韩美半导体株式会社 Method for aligning semiconductor materials
CN102934216B (en) * 2010-05-04 2016-08-03 韩美半导体株式会社 For the method being directed at semi-conducting material
CN103198035A (en) * 2013-02-28 2013-07-10 北京优纳科技有限公司 Position alignment method and position alignment system
CN105489620A (en) * 2014-10-03 2016-04-13 株式会社东芝 Method for manufacturing solid-state imaging device and method for manufacturing camera module
US20190279892A1 (en) * 2016-06-01 2019-09-12 Micron Technology, Inc. Systems and methods for wafer alignment
US10600667B2 (en) * 2016-06-01 2020-03-24 Micron Technology, Inc. Systems and methods for wafer alignment
US20200118964A1 (en) * 2018-10-11 2020-04-16 Samsung Electronics Co., Ltd. Method of aligning wafers, method of bonding wafers using the same, and apparatus for performing the same
KR20200041070A (en) * 2018-10-11 2020-04-21 삼성전자주식회사 Method of aligning wafers, method of bonding wafers using the same, and apparatus for performing the same
CN111048459A (en) * 2018-10-11 2020-04-21 三星电子株式会社 Method for aligning wafer, method for bonding wafer, and apparatus for aligning wafer
KR102409885B1 (en) 2018-10-11 2022-06-16 삼성전자주식회사 Method of aligning wafers, method of bonding wafers using the same, and apparatus for performing the same
CN111048459B (en) * 2018-10-11 2024-03-22 三星电子株式会社 Method for aligning wafer, method for bonding wafer and device for aligning wafer
CN114628299A (en) * 2022-03-16 2022-06-14 江苏京创先进电子科技有限公司 Wafer centering confirmation method and Taizhou ring cutting method
CN114628299B (en) * 2022-03-16 2023-03-24 江苏京创先进电子科技有限公司 Wafer alignment confirmation method and Taizhou ring cutting method

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