CN110943439A - 一种h桥短路保护电路 - Google Patents

一种h桥短路保护电路 Download PDF

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Publication number
CN110943439A
CN110943439A CN201911412986.2A CN201911412986A CN110943439A CN 110943439 A CN110943439 A CN 110943439A CN 201911412986 A CN201911412986 A CN 201911412986A CN 110943439 A CN110943439 A CN 110943439A
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pmos
tube
terminal
drain
pmos transistor
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CN201911412986.2A
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张南阳
蒋赛尖
马辉
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Hangzhou Sitai Microelectronics Co.,Ltd.
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STEADICHIPS Inc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/26—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents
    • H02H3/28—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at two spaced portions of a single system, e.g. at opposite ends of one line, at input and output of apparatus
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electronic Switches (AREA)

Abstract

本发明涉及模拟集成电路领域，具体为一种H桥短路保护电路，其能够让H桥没有短路电流流过，保护PMOS管，其包括比较器COMP1和比较器COMP，比较器COMP1的输入端连接电阻R0一端、PMOS管PM2的漏端，PM2的源端连接VDD和PMOS管PM0的源端，PMOS管PM2的栅端和PMOS管PM0的栅端相连，PMOS管PM0的漏端连接NMOS管NM0的漏端、NMOS管NM2的漏端、电阻R0另一端，NMOS管NM2的栅端和NMOS管NM0的栅端相连，NMOS管NM0的源端连接电阻R1一端并接地，电阻R1另一端连接NMOS管NM2的源端和比较器COMP的输入端，比较器COMP1的输出端与比较器COMP的输出端连接或门的输出端，或门的输出端为OUT端口，其特征在于，比较器COMP1包括PMOS管PM10、PMOS管PM1、PMOS管PM9、PMOS管PM3。

Description

一种H桥短路保护电路
技术领域
本发明涉及模拟集成电路领域，具体为一种H桥短路保护电路。
背景技术
随着技术的发展，现在对低压下的马达的应用越来越多，就需要的低压马达驱动越来越多。马达驱动电路一般采用H桥输出的方式，在使用时要防止H桥的输出短接，输出短路到电源或者到地，图1为H桥原理图，因此，输出短路保护电路就很重要了。
H桥分为上管和下管，低压的H桥高边管一般采用PMOS，低边管一般采用NMOS。高边管和低边管都有要短路保护机制。低边管保护机制如图2所示，低边NMOS管NM0通过并联sensor管NM2，同时sensor管NM2的电流流过电阻R1，在电阻R1上产生电压。OUT端短路到电源或两个输出短路时，这个电压比参考电压VREF_1高，则比较器COMP翻转，OUT端输出翻转，同时关闭H桥。保护输出H桥上长时间没有短路电流流过。
高边的PMOS管PM0通过并联检测电流的sensor管PM2，同时sensor管PM2的电流流过电阻R0，电阻R0上有一定的电压。如果只是检测电阻R0一端的电压，如图2所示，那么在H桥正常工作时这端口的电压会随着PMOS管PM0的开或关在0和VDD之间变化，如果参考电压VREF设置成为固定值时，比较器COMP1的输出也随着PMOS管PM0的开或关变化，因此这个电压无法确定。
发明内容
为了解决现有低压H桥的方案中高边管采用的PMOS管输出短路到地，PMOS管电流会过大损坏PMOS管的问题，本发明提供了一种H桥短路保护电路，其能够让H桥没有短路电流流过，保护PMOS管。
其技术方案是这样的：一种H桥短路保护电路，其包括比较器COMP1和比较器COMP，所述比较器COMP1的输入端连接电阻R0一端、PMOS管PM2的漏端，所述PM2的源端连接VDD和PMOS管PM0的源端，所述PMOS管PM2的栅端和所述PMOS管PM0的栅端相连，所述PMOS管PM0的漏端连接NMOS管NM0的漏端、NMOS管NM2的漏端、所述电阻R0另一端，所述NMOS管NM2的栅端和所述NMOS管NM0的栅端相连，所述NMOS管NM0的源端连接电阻R1一端并接地，所述电阻R1另一端连接所述NMOS管NM2的源端和所述比较器COMP的输入端，所述比较器COMP1的输出端与所述比较器COMP的输出端连接或门的输出端，所述或门的输出端为OUT端口，其特征在于，所述比较器COMP1包括PMOS管PM10、PMOS管PM1、PMOS管PM9、PMOS管PM3，所述PPMOS管PM10、PMOS管PM1、PMOS管PM9、PMOS管PM3的栅端分别为所述比较器COMP1的输入端，所述PMOS管PM10的源端与所述PMOS管PM1的源端相连后连接所述PMOS管PM4的漏端，所述PMOS管PM9的源端与所述PMOS管PM3的源端相连后连接所述PMOS管PM5的漏端，所述PMOS管PM1的漏端与所述PMOS管PM9的漏端相连后连接PMOS管PM7的漏端、NMOS管NM1的漏端、NMOS管NM4的栅端，所述PMOS管PM10的漏端与所述PMOS管PM3的漏端相连后连接PMOS管PM6的漏端、NMOS管NM3的漏端和栅端、所述NMOS管NM1的栅端，所述NMOS管NM3的源端、NMOS管NM1的源端、NMOS管NM2的源端均接地，所述NMOS管NM2的漏端连接PMOS管PM8的漏端并为所述比较器COMP1的输出端，所述PMOS管PM4、PMOS管PM5、PMOS管PM8的栅端相连，所述PMOS管PM4、PMOS管PM5、PMOS管PM6 、PMOS管PM7、PMOS管PM8的源端相连后连接VDD。
采用本发明后，重新设计了比较器COMP1的内部电路结构，通过检测电阻R0两端的压差和比较器COMP1的两个参考电压差值进行比较来确定是否要关闭H桥，让H桥没有短路电流流过，从而保护PMOS管。
附图说明
图1为H桥原理图；
图2为现有的H桥短路保护电路；
图3为本发明的H桥短路保护电路；
图4为本发明比较器COMP1电路原理图。
具体实施方式
见图3和图4所示，一种H桥短路保护电路，其包括比较器COMP1和比较器COMP，比较器COMP1的输入端连接电阻R0一端、PMOS管PM2的漏端，PM2的源端连接VDD和PMOS管PM0的源端，PMOS管PM2的栅端和PMOS管PM0的栅端相连，PMOS管PM0的漏端连接NMOS管NM0的漏端、NMOS管NM2的漏端、电阻R0另一端，NMOS管NM2的栅端和NMOS管NM0的栅端相连，NMOS管NM0的源端连接电阻R1一端并接地，电阻R1另一端连接NMOS管NM2的源端和比较器COMP的输入端，比较器COMP1的输出端与比较器COMP的输出端连接或门的输出端，或门的输出端为OUT端口，比较器COMP1包括PMOS管PM10、PMOS管PM1、PMOS管PM9、PMOS管PM3，PPMOS管PM10、PMOS管PM1、PMOS管PM9、PMOS管PM3的栅端分别为比较器COMP1的输入端，PMOS管PM10的源端与PMOS管PM1的源端相连后连接PMOS管PM4的漏端，PMOS管PM9的源端与PMOS管PM3的源端相连后连接PMOS管PM5的漏端，PMOS管PM1的漏端与PMOS管PM9的漏端相连后连接PMOS管PM7的漏端、NMOS管NM1的漏端、NMOS管NM4的栅端，PMOS管PM10的漏端与PMOS管PM3的漏端相连后连接PMOS管PM6的漏端、NMOS管NM3的漏端和栅端、NMOS管NM1的栅端，NMOS管NM3的源端、NMOS管NM1的源端、NMOS管NM2的源端均接地，NMOS管NM2的漏端连接PMOS管PM8的漏端并为比较器COMP1的输出端，PMOS管PM4、PMOS管PM5、PMOS管PM8的栅端相连并输入Vbias，PMOS管PM4、PMOS管PM5、PMOS管PM6 、PMOS管PM7、PMOS管PM8的源端相连后连接VDD。
本发明是通过检测电阻R0两端的电压差， 并同时和比较器COMP1的参考电压VREF_2与VREF_1的差值进行比较。在正常工作时PMOS管PM0开启或关闭，电阻R0两端的电压比VREF_2与VREF_1的差值小，比较器COMP1不会翻转。当电阻R0两端的电压比VREF_2与VREF_1的差值大时，比较器COMP1翻转，OUT端输出变化，同时OUT端信号使H桥关闭。保护H桥长时间没有短路电流流过。比较器COMP1的INPUT1端（即IN1N端和IN1P端）是接电阻R0两端进行电压检测，INPUT1端（即IN2N端和IN2P端）是接VREF_2和VREF_1，作为参考电压。VREF_2和VREF_1有固定的压差，当IN1N端和IN1P端的两个输出之间的压差大于VREF_2和VREF_1之间的压差，此比较器COMP1就翻转。

Claims (1)

1.一种H桥短路保护电路，其包括比较器COMP1和比较器COMP，所述比较器COMP1的输入端连接电阻R0一端、PMOS管PM2的漏端，所述PM2的源端连接VDD和PMOS管PM0的源端，所述PMOS管PM2的栅端和所述PMOS管PM0的栅端相连，所述PMOS管PM0的漏端连接NMOS管NM0的漏端、NMOS管NM2的漏端、所述电阻R0另一端，所述NMOS管NM2的栅端和所述NMOS管NM0的栅端相连，所述NMOS管NM0的源端连接电阻R1一端并接地，所述电阻R1另一端连接所述NMOS管NM2的源端和所述比较器COMP的输入端，所述比较器COMP1的输出端与所述比较器COMP的输出端连接或门的输出端，所述或门的输出端为OUT端口，其特征在于，所述比较器COMP1包括PMOS管PM10、PMOS管PM1、PMOS管PM9、PMOS管PM3，所述PPMOS管PM10、PMOS管PM1、PMOS管PM9、PMOS管PM3的栅端分别为所述比较器COMP1的输入端，所述PMOS管PM10的源端与所述PMOS管PM1的源端相连后连接所述PMOS管PM4的漏端，所述PMOS管PM9的源端与所述PMOS管PM3的源端相连后连接所述PMOS管PM5的漏端，所述PMOS管PM1的漏端与所述PMOS管PM9的漏端相连后连接PMOS管PM7的漏端、NMOS管NM1的漏端、NMOS管NM4的栅端，所述PMOS管PM10的漏端与所述PMOS管PM3的漏端相连后连接PMOS管PM6的漏端、NMOS管NM3的漏端和栅端、所述NMOS管NM1的栅端，所述NMOS管NM3的源端、NMOS管NM1的源端、NMOS管NM2的源端均接地，所述NMOS管NM2的漏端连接PMOS管PM8的漏端并为所述比较器COMP1的输出端，所述PMOS管PM4、PMOS管PM5、PMOS管PM8的栅端相连，所述PMOS管PM4、PMOS管PM5、PMOS管PM6 、PMOS管PM7、PMOS管PM8的源端相连后连接VDD。
CN201911412986.2A 2019-12-31 2019-12-31 一种h桥短路保护电路 Pending CN110943439A (zh)

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