CN110914962A - 封装装置以及半导体装置的制造方法 - Google Patents

封装装置以及半导体装置的制造方法 Download PDF

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CN110914962A
CN110914962A CN201880046237.XA CN201880046237A CN110914962A CN 110914962 A CN110914962 A CN 110914962A CN 201880046237 A CN201880046237 A CN 201880046237A CN 110914962 A CN110914962 A CN 110914962A
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substrate
stage
semiconductor chip
package
electromagnetic wave
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中村智宣
前田彻
高野彻朗
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Shinkawa Ltd
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Shinkawa Ltd
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Abstract

一种封装装置，其将半导体芯片12接合于作为基板30或其它半导体芯片12的被封装体而制造半导体装置，所述封装装置包括：平台120，载置有所述基板30；封装头124，相对于所述平台120可进行相对移动，并将所述半导体芯片12接合于所述被封装体；照射单元108，透射所述平台，并且自平台120的下侧照射对所述基板30进行加热的电磁波，所述平台120具有形成于上表面侧的第一层122，且第一层122的面方向上的热阻力大于厚度方向上的热阻力。

Description

封装装置以及半导体装置的制造方法
技术领域
本发明书公开一种将半导体芯片接合于作为基板或其它半导体芯片的被封装体而制造半导体装置的封装装置以及半导体装置的制造方法。
背景技术
在将半导体芯片接合于基板或其它半导体芯片上的情况下，通常利用已加热的封装头对半导体芯片进行加热加压。但是仅利用来自封装头的热，难以对作为接合对象的半导体芯片进行适当的加热。尤其，近年来为了实现半导体装置的更高功能化、小型化，而提出将多个半导体芯片层叠而进行封装。所述情况下，为了缩短封装处理的时间，存在一边将多个半导体芯片进行暂时压接一边进行层叠后，对所述多个半导体芯片成批地进行正式压接的情况。即，存在对多个半导体芯片以暂时压接状态进行层叠而形成暂时层叠体后，利用已加热的封装头对所述暂时层叠体的上表面进行加热加压而进行正式压接的情况。所述情况下，仅利用来自封装头的热，难以适当地加热至暂时层叠体的最下层的半导体芯片。因此，自以前开始，在对半导体装置进行接合时，对载置有基板的平台整体进行加热。由此，可自半导体芯片的上下两侧进行加热。
现有技术文献
专利文献
专利文献1：国际公开第2010/050209号
专利文献2：日本专利第3833531号公报
专利文献3：日本专利第4001341号公报
发明内容
发明所要解决的问题
但是，在对平台整体进行加热的情况下，配置于与作为接合对象(加热对象)的半导体芯片不同部位的半导体芯片也被持续加热。结果在半导体芯片中被长时间输入热。此种长期的热输入会导致半导体芯片，尤其是设置于半导体芯片的底面的非导电性膜(NonConductive Film)等树脂的劣化，甚至导致封装质量的下降。
为了避免所述问题，也考虑在平台的多个部位预先设置脉冲式加热器(pulseheater)等局部加热用的加热器，且仅接通所需部位的加热器。但是，在将此种局部加热用的加热器埋入平台的情况下，难以维持平台的平坦度，甚至会导致封装质量的下降。
另外，在专利文献1-专利文献3中，公开有一种利用自平台的背侧照射的光来对基板进行光加热的技术，但这些技术均未充分考虑对基板进行局部加热。
因此，本说明书中提供一种能对作为接合对象的半导体芯片进行适当的加热，另一方面能抑制向其它半导体芯片的热输入的封装装置以及半导体装置的制造方法。
解决问题的技术手段
本说明书中公开的封装装置将半导体芯片接合于作为基板或其它半导体芯片的被封装体而制造半导体装置，所述封装装置的特征在于包括：平台，具有直接或经由中间构件载置所述基板的第一面、以及与所述第一面为相反侧的第二面；封装头，相对于所述平台能够进行相对移动，并将所述半导体芯片接合于所述被封装体；以及照射单元，透射所述平台，并且自所述第二面侧照射对所述基板或所述中间构件进行加热的电磁波，所述平台具有形成于所述第一面侧的第一层，且所述第一层的面方向上的热阻力大于厚度方向上的热阻力。
可为：所述基板热压接有多个所述半导体芯片，所述照射单元包括变更部件，所述变更部件对所述第一面的所述电磁波的照射区域、以及所述第一面的所述电磁波的照射位置的至少一者进行变更。
另外，可为：所述封装头包括加热器，所述加热器对多个所述半导体芯片以暂时压接的状态经层叠而成的暂时层叠体进行加热来进行正式压接，所述照射单元与所述加热器一起对所述暂时层叠体进行加热。
另外，可为：所述平台还具有比所述第一层而形成于更靠所述第二面侧的第二层，且所述第一层的面方向上的热阻力比所述第二层大。
另外，可为：所述第二层的刚性比所述第一层高。
另外，可为：所述第二层是包含所述电磁波能够透射的材料的实心部位，所述第一层是在上表面形成有多个槽或在层内形成有多个细孔的部位。
另外，可为：所述基板为硅晶片，且被直接载置于所述平台，所述电磁波为波长1200nm以下，且所述基板利用所述电磁波被局部加热。
另外，可为：所述基板经由所述中间构件被载置于所述平台，所述电磁波具有被所述中间构件吸收且不被所述基板吸收的波长，通过来自利用所述电磁波被局部加热的所述中间构件的传热，对所述基板进行局部加热。
本说明书中公开的半导体装置的制造方法将半导体芯片接合于作为基板或其它半导体芯片的被封装体而制造半导体装置，所述半导体装置的制造方法的特征在于包括：载置步骤，将所述基板直接或经由中间构件载置于平台的第一面；接合步骤，利用相对于所述平台能够进行相对移动的封装头，将所述半导体芯片接合于所述被封装体；基板加热步骤，与所述接合步骤的至少一部分并行地，自隔着所述平台而配置于所述封装头的相反侧的照射单元照射被所述基板或所述中间构件吸收且透射所述平台的电磁波，由此对所述基板或所述中间构件进行加热，所述平台具有形成于所述第一面侧的第一层，且所述第一层的面方向上的热阻力大于厚度方向上的热阻力。
所述接合步骤可包括：暂时压接步骤，利用所述封装头，在所述基板的多个部位依序形成暂时层叠体，所述暂时层叠体是一边将一个以上的所述半导体芯片暂时压接于所述基板上一边进行层叠而成；正式压接步骤，在所述暂时压接步骤后，在所述基板的多个部位依序进行如下处理：所述处理是对一个暂时层叠体自其上表面进行加热加压，由此对构成所述暂时层叠体的一个以上的所述半导体芯片成批地进行正式压接，所述基板加热步骤可与对所述半导体芯片成批地进行正式压接的处理并行地，对所述基板或所述中间构件中的与所述正式压接执行部位对应的部位照射所述电磁波。
发明的效果
根据本说明书中公开的装置以及方法，因利用电磁波对基板进行局部加热，因此能对作为接合对象的半导体芯片进行适当的加热。另外，因平台第一层的面方向上的热阻力比厚度方向上的热阻力高，因此朝向在面方向上相离而配置的其它半导体芯片的传热得到抑制，进而向其它半导体芯片的热输入得到抑制。
附图说明
图1是表示封装装置的构成的图。
图2是表示半导体装置的一例的图。
图3是表示基板的一例的图。
图4是表示半导体芯片的一例的图。
图5是表示对基板进行局部加热时的情形的图。
图6是图5的X部放大图。
图7是表示平台的另一例的图。
图8是表示平台的另一例的图。
图9是表示平台的另一例的图。
图10是表示平台的另一例的图。
具体实施方式
以下，参照附图对半导体装置的制造方法以及封装装置100进行说明。图1是表示封装装置100的构成的图。所述封装装置100是将半导体芯片12封装于基板30上的装置。所述封装装置100是在将多个半导体芯片12层叠来进行封装的情况下尤其优选的构成。再者，在以下的说明中，在多个半导体芯片12层叠而成的层叠体中，将构成层叠体的多个半导体芯片12处于暂时压接状态的层叠体称为“暂时层叠体STt”、将多个半导体芯片12处于正式压接状态的层叠体称为“芯片层叠体STc”来进行区分。
封装装置100包括：芯片供给单元102、芯片搬送单元104、接合单元106、照射单元108、以及对这些单元的驱动进行控制的控制部130。芯片供给单元102是自芯片供给源将半导体芯片12取出并供给至芯片搬送单元104的部位。所述芯片供给单元102包括上推部110、晶粒拾取机(die picker)114、以及移送头116。
在芯片供给单元102中，多个半导体芯片12被载置于切割带TE上。此时，半导体芯片12以凸块18朝向上侧的面朝上状态被载置。上推部110自所述多个半导体芯片12中将仅一个半导体芯片12保持着面朝上的状态朝上方上推。晶粒拾取机114利用其下端对由上推部110所上推的半导体芯片12进行抽吸保持并予以接收。接收到半导体芯片12的晶粒拾取机114原地进行180度旋转，以使所述半导体芯片12的凸块18朝向下方，即，使半导体芯片12成为面朝下的状态。成为所述状态后，移送头116自晶粒拾取机114接收半导体芯片12。
移送头116在上下方向及水平方向上可移动，且可利用其下端对半导体芯片12进行吸附保持。晶粒拾取机114进行180度旋转而使半导体芯片12成为面朝下状态后，移送头116利用其下端对所述半导体芯片12进行吸附保持。之后，移送头116在水平方向及上下方向上进行移动，而移动至芯片搬送单元104。
芯片搬送单元104具有以铅垂的旋转轴Ra为中心进行旋转的旋转台118。移送头116将半导体芯片12载置于旋转台118的规定位置。载置有半导体芯片12的旋转台118以旋转轴Ra为中心进行旋转，由此，所述半导体芯片12被搬送至位于芯片供给单元102的相反侧的接合单元106。
接合单元106包括对基板30进行支撑的平台120、以及将半导体芯片12安装于基板30的封装头124。平台120具有载置基板30的上表面(第一面)、以及与所述第一面为相反侧的下表面(第二面)。另外，平台120在水平方向上可移动，对所载置的基板30与封装头124的相对位置关系进行调整。平台120如后文所详述那样包含能够使自照射单元108照射的电磁波134透射的材料。另外，平台120为具有面方向上的热阻力比厚度方向上的热阻力高的的第一层、以及配置于第一层的下侧的第二层的多层构造，关于所述方面也将于后文说明。
封装头124将多个半导体芯片12层叠并封装于基板30。封装头124能够将半导体芯片12保持于其下端，另外，可绕铅垂的旋转轴Rb进行旋转、升降。所述封装头124将半导体芯片12压接于基板30或其它的半导体芯片12上。具体而言，封装头124下降以便将所保持的半导体芯片12按压至基板30等，由此来进行半导体芯片12的暂时压接或正式压接。在所述封装头124内置有温度可变的加热器(未图示)，封装头124在执行暂时压接时被加热至第一温度T1，在执行正式压接时被加热至比第一温度T1高的第二温度T2。另外，封装头124在执行暂时压接时将第一负荷F1附加至半导体芯片12，在执行正式压接时将第二负荷F2附加至半导体芯片12。
在封装头124的附近设置有照相机(未图示)。在基板30及半导体芯片12分别附有成为定位基准的对准标记。照相机以拍摄入所述对准标记的方式对基板30以及半导体芯片12进行拍摄。控制部130基于由所述拍摄所得到的图像数据，把握基板30以及半导体芯片12的相对位置关系，并根据需要对封装头124绕着轴Rb的旋转角度以及平台120的水平位置进行调整。
照射单元108自平台120的背侧照射特定波长的电磁波134，由此对基板30进行局部加热。照射单元108至少具有照射电磁波134的电磁波源132。电磁波134只要具有容易透射平台120、且容易被基板30吸收的波长则并无特别限定，但若考虑到输出、指向性，电磁波134理想的是激光光。作为电磁波源132，只要能以所期望的功率照射所期望的波长、功率的光，则并无特别限定，例如，可使用激光振荡器或激光二极管(Laser Diode，LD)、发光二极管(light-emitting diode，LED)、卤素灯(halogen lamp)等。为了仅对基板30的特定范围照射电磁波134，照射单元108可还具有光圈或透镜、反射镜、光纤等光学构件，对这些光学构件进行驱动而使电磁波扫描的驱动构件等。
控制部130对各部的驱动进行控制，例如包括进行各种运算的中央处理器(Central Processing Unit，CPU)、以及存储各种数据或程序的存储部。控制部130依照存储于存储部的程序，对各部进行驱动来执行半导体芯片的封装处理。例如，控制部130对封装头124以及平台120进行驱动而将半导体芯片封装于基板30。另外，控制部130与后述的正式压接处理并行地，对照射单元108进行驱动而使基板30被局部加热。
接着，参照图3～图5对由所述封装装置100所制造的半导体装置10进行说明。图3是表示半导体装置10的一例的示意图，图4是基板30的示意图，图5是半导体芯片12的示意图。再者，在图3中，半导体芯片12与基板30的边界、以及两个半导体芯片12的边界的粗线表示已被正式压接。
如图3所示，本例中所处理的半导体装置10在基板30的上表面层叠封装有多个(图示的例子中为4个)半导体芯片12。另外，本例中使用硅晶片作为基板30。因此，本说明书中公开的封装工艺是将半导体芯片12层叠封装于硅晶片的电路形成面的“晶片上芯片工艺(chip-on-wafer process)”。
作为硅晶片的基板30主要包含硅，与包含树脂或玻璃的通常的电路基板相比，热传导率高。如图2所示，在基板30，设定有呈格子状排列的多个封装分区34。在各封装分区34层叠封装有多个半导体芯片12。封装分区34以规定的配置间距P进行配设。所述配置间距P的值根据作为封装对象的半导体芯片12的尺寸等适宜地设定。另外，本实施方式中，将封装分区34设为大致正方形，但也可适宜地设为其它形状，例如大致长方形。在各封装分区34的表面，在与被封装的半导体芯片12的凸块18对应的位置形成有电极36(参照图3)。
接着，关于半导体芯片12的构成如图4所示，在半导体芯片12的上下面形成有电极端子14、电极端子16。另外，在半导体芯片12的单面形成有与电极端子14相连的凸块18。凸块18包含导电性金属，并在规定的熔融温度Tm下熔融。
另外，在半导体芯片12的单面，以覆盖凸块18的方式贴附有非导电性膜(以下称为“NCF”)20。NCF 20作为将半导体芯片12与基板30或其它半导体芯片12加以粘合的粘合剂而发挥功能，且包含非导电性的热硬化性树脂，例如聚酰亚胺树脂、环氧树脂、丙烯酸树脂、苯氧基树脂、聚醚砜(Polyethersulfone，PES)树脂等。所述NCF 20的厚度比凸块18的平均高度大，凸块18被所述NCF 20大致完全覆盖。NCF 20在常温下是固体的膜，但若超过规定的软化起始温度Ts，则慢慢且可逆地软化而发挥流动性，若超过规定的硬化起始温度Tt，则开始不可逆地硬化。
此处，软化起始温度Ts比硬化起始温度Tt以及凸块18的熔融温度Tm低。暂时压接用的第一温度T1比所述软化起始温度Ts高，且比熔融温度Tm以及硬化起始温度Tt低。另外，正式压接用的第二温度T2比熔融温度Tm以及硬化起始温度Tt高。即，成为Ts＜T1＜(Tm、Tt)＜T2。
在将半导体芯片12暂时压接于基板30或下侧的半导体芯片12(以下，当不对两者进行区分时称为“被封装体”)时，将封装头124加热至第一温度T1后对半导体芯片12进行加压。此时，半导体芯片12的NCF 20利用来自封装头124的传热而被加热至第一温度T1附近，从而软化而具有流动性。而且，由此，NCF 20流入至半导体芯片12与被封装体的间隙，从而能确实地填埋所述间隙。
在将半导体芯片12正式压接于被封装体时，将封装头124加热至第二温度T2后对半导体芯片12进行加压。此时，半导体芯片12的凸块18以及NCF20利用来自封装头124的传热而被加热至第二温度T2附近。由此，凸块18熔融并可熔接于相向的被封装体。另外，通过所述加热，NCF 20以将半导体芯片12与被封装体的间隙填埋的状态进行硬化，因此半导体芯片12与被封装体得以牢固地固定。即，在正式压接时，半导体芯片12被热压接于基板30等。
此处，将封装头124的温度自第一温度T1切换为第二温度T2、或自第二温度T2切换为第一温度T1需花费一定的时间。因此，为了对半导体装置10缩短制造时间，有效的是减少封装头124的温度切换次数。因此，提出了如下工艺：在对多个半导体芯片12进行层叠封装的情况下，将全部的半导体芯片12进行暂时压接后，对所述经暂时压接的半导体芯片12进行正式压接。具体而言，首先，使用加热至第一温度T1的封装头124，在多个封装分区34形成一边对多个半导体芯片12进行暂时压接一边进行层叠而成的暂时层叠体STt。继而，利用切换成第二温度T2的封装头124对暂时层叠体STt的上表面进行加压，由此，对构成暂时层叠体STt的多个半导体芯片12成批地进行正式压接。通过以所述顺序对半导体芯片12进行封装，能大幅减少封装头124的温度切换次数，从而能大幅缩短半导体装置10的制造时间。
此外，如根据至此为止的说明而明确那样，为了对半导体芯片12进行适当的封装，理想的是作为封装对象的半导体芯片12被加热至与其处理过程相对应的适当的温度。例如，在进行正式压接时，半导体芯片12必须被加热至NCF 20的硬化起始温度Tt以上，且必须被加热至凸块18的熔融温度Tm以上。但是，也存在仅利用来自封装头124的热难以将全部的半导体芯片12加热至适当的温度的情况。尤其，在对构成暂时层叠体STt的多个半导体芯片12成批地进行正式压接的情况下，若仅利用来自封装头124的热，难以对最下层的半导体芯片12进行适当的加热。
另外，理想的是在一个暂时层叠体STt中，最上层的半导体芯片12的温度与最下层的半导体芯片12的温度差(以下为“层叠体内温度差”)ΔT小。若层叠体内温度差ΔT大，则会导致封装质量的不均。但是，若仅利用来自封装头124的热，难以使层叠体内温度差ΔT变小。
因此，以前，在多数情况下预先将加热器内置于供基板30载置的平台120而也对基板30整体进行加热。根据所述构成，暂时层叠体STt也自下侧受到加热，因此最下层的半导体芯片12也容易地被加热至适当的温度，另外，能使层叠体内温度差ΔT在某种程度上变小。
其中，在对平台120整体进行加热的情况下，当然必须使所述平台120的温度充分低于NCF 20的硬化起始温度Tt。其原因在于：若平台120的温度比硬化起始温度Tt高，则暂时压接后、正式压接前的半导体芯片12的NCF20会进行热硬化。因此，不能使平台120的温度过高，从而难以使层叠体内温度差ΔT变得充分小。
另外，平台120即使处于比硬化起始温度Tt更低的温度，在对所述平台120整体进行加热的情况下，在暂时压接或正式压接于基板30的半导体芯片12会被长时间地持续输入热。此种长时间的热的输入会导致半导体芯片12尤其是NCF 20的劣化，甚至是封装质量的劣化。
因此，如已述那样，本说明书中公开的封装装置100中，在平台120的下侧配置照射单元108，从而利用电磁波134对基板30进行局部加热。图5是表示对基板30进行局部加热时的情形的概念图。再者，在图5中，图示有三个封装分区34，但在以下的说明中，将这些封装分区34自图示左侧起依次称为“分区A”、“分区B”、“分区C”来进行区分。另外，在图5中，半导体芯片12与被封装体(基板30或其它半导体芯片12)的边界的粗线表示已被正式压接，虚线表示已被暂时压接。因此，在图5中，分区A的层叠体是经正式压接的芯片层叠体STc，分区B、分区C的层叠体是暂时压接后且正式压接前的暂时层叠体STt。图5是表示对分区B的暂时层叠体STt进行正式压接时的情形。
如图5所示，在对一个暂时层叠体STt进行正式压接时，利用被加热至第二温度T2的封装头124对所述暂时层叠体STt进行加热/加压。另外，对基板30中的配置有作为正式压接对象的暂时层叠体STt的分区B照射电磁波134，从而利用电磁波134对所述分区B进行加热。
此处，如已述那样，电磁波134具有容易透射平台120且容易被基板30吸收的波长。本例中，基板30是硅晶片。当波长低于1200nm时硅的透射率急剧下降。因此，在使用硅晶片作为基板30的情况下，理想的是将电磁波134的波长设为1200nm以下。但是，若波长过度小，则电磁波的能量也下降，因此理想的是电磁波134的波长比可见光大，即为750nm以上。
另外，对于平台120，理想的是电磁波134的透射率高。另外，对于平台120，也理想的是缺乏传热性的材料。此是为了防止由电磁波134加热的封装分区34的热经由平台120传递至其它的封装分区34。为了满足此种条件，平台120理想的是例如包含石英或氟化钡、氟化镁、氟化钙等。
电磁波134的照射范围理想的是与半导体芯片12的外形大致相同的范围。另外，为了仅对所期望的范围照射电磁波134，照射单元108理想的是具有对电磁波134的照射范围以及照射位置的至少一者进行变更的变更部件。作为变更部件的构成，可考虑有多种，变更部件例如可具有使电磁波源132相对于平台120的位置移动的移动机构。作为所述移动机构，例如包括使平台120移动的XY移动机构。另外，为了仅对所期望的照射范围进行照射，例如，如图5所示，变更部件可具有光圈135，所述光圈135设置于直径充分大于照射范围的电磁波134的路径中途，且形成有与照射范围对应的开口。所述光圈135可根据作为对象的半导体装置适宜地进行更换。
另外，作为另一实施方式，可利用在基板30附近直径充分小于照射范围的电磁波134，对照射范围进行扫描。为了在基板30附近获得小直径的电磁波134，可使用射出小直径的平行电磁波(例如平行光)的电磁波源132，也可使用光学构件(透镜等)使大直径的电磁波134在基板30周边对焦。另外，为了使电磁波134进行扫描，可移动电磁波132自身，也可移动使电磁波134弯曲的反射镜等。作为移动反射镜的形态，例如，可使用利用振镜马达(galvanometer motor)使两个以上的反射镜驱动的振镜反射镜(galvanometer mirror)机构。另外，作为对反射镜或电磁波源132进行驱动的机构，可使用线圈马达或凸轮等。
另外，作为另一实施方式，为了仅对所期望的照射范围进行照射，可使用各种光学构件来使电磁波134的轮廓(profile)(尺寸、外形等)产生变化。例如，可使用具有几何学的光束成形功能的矩形芯纤维。另外，作为另一实施方式，可在电磁波134的路径中途配置在筒体的内表面贴附有多个反射镜的万花筒(kaleidoscope)。进而，也可代替所述的光学构件、或者除此之外也使用衍射透镜或复眼透镜(fly-eye lens)、其它光学透镜来使电磁波134的轮廓变化。
另外，图1中仅图示了一个电磁波源132，但是电磁波源132可设置两个以上，所述两个以上的电磁波源132可为彼此同种的电磁波源，也可为彼此不同种类的电磁波源。另外，电磁波134的功率理想的是可以所期望的时间将基板30加热至所期望的温度。例如，理想的是：在对暂时层叠体STt成批地进行正式压接时，将最下层的半导体芯片12加热至与最上层的半导体芯片12相同的温度。通常，正式压接的运行时间为几秒，因此电磁波134理想的是具有如下程度的功率：能在所述正式压接的执行过程中(几秒以内)将基板30加热至接近第二温度T2。
总之，通过照射容易透射平台120且容易被基板30吸收的波长的电磁波134，在基板30中电磁波134被吸收。而且，通过将所吸收的电磁波的能量转换成热，可仅对基板30中的照射有电磁波134的范围进行局部加热。而且，通过基板被局部加热，位于所述加热部分(照射部分)上的半导体芯片12也被加热。通过仅在进行正式压接处理的封装分区34中进行此种局部加热(电磁波134的照射)，也可对最下层的半导体芯片12进行适当的加热，从而可获得良好的封装质量。另外，通过对进行正式压接处理的封装分区34进行局部加热，可减小层叠体内温度差ΔT，从而可使构成一个层叠体的多个半导体芯片12的封装质量均匀化。
另一方面，在不进行正式压接处理的封装分区34不照射电磁波134，因此能够有效防止所述封装分区的温度上升，进而防止并非正式压接处理的对象的半导体芯片12的由热所引起的劣化或变质。
但是，在利用电磁波134仅对作为正式压接对象的封装分区34进行加热的情况下，所述封装分区34中所产生的热的一部分经由基板30、平台120而传递至其它封装分区34。例如，在图5中，即便在利用电磁波134仅对分区B进行加热的情况下，所述分区B中所产生的热的一部分也经由基板30以及平台120而向分区A或分区C流出。此种热流出有可能导致热效率变差、并非正式压接处理的对象的分区A或分区B的半导体芯片12的热劣化。
因此，在本说明书中公开的封装装置100中，为了减少向作为加热对象的封装分区以外的封装分区的传热，如上所述，使平台120包含缺乏传热性的材料，例如石英等。进而，本例中，为了减少向经由平台120的面方向传热，在平台120的表面形成有多个槽。通过形成所述槽，在朝向面方向的路径中途存在多个空气层(槽部分)，从而面方向上的热阻力变高。以下，在平台120中，将形成有所述槽的部分称为“第一层122”，将配置于第一层122的下侧的实心部分称为“第二层123”。第一层122因在其表面形成有多个槽，因此面方向上的热阻力比厚度方向上的热阻力高。另外，第二层123是实心构造，因此与第一层122相比，面方向上的热阻力低，另一方面强度高而难以挠曲。
形成于第一层122的槽的间距并无特别限定，例如可充分小于半导体芯片12的一边(例如，槽间距为半导体芯片的一边的1/10以下等)。槽的间距小而槽的数量变多，由此可缓和槽的边缘与基板30的抵接部位所产生的应力集中，进而，在进行接合(暂时压接、正式压接)时，可使施加至半导体芯片12整体的压力均匀化。另外，作为另一实施方式，可将槽的间距设为与封装分区34的配置间距P相同，以将所述槽配置于与封装分区34的边界线大致相同的位置。换言之，可设为：在半导体芯片12的正下方不存在槽，仅在于面方向上邻接的两个半导体芯片12之间存在槽。若设为所述构成，则在进行接合(暂时压接、正式压接)时，可使施加至半导体芯片12整体的压力更均匀化。另外，所述形成于第一层122的槽可与用以对所载置的基板30进行抽吸保持的抽吸机构(未图示)连通。
如此，通过在平台120的表层设置面方向上的热阻力比厚度方向上的热阻力高的第一层122，可有效防止经由所述平台120的向面方向的传热。关于此，参照图6进行说明。图6是图5的X部放大图。设为通过照射单元108而利用电磁波134仅对分区B进行加热。所述情况下，分区B中所产生的热向上方(半导体芯片12侧)、面方向(分区A、分区C侧)、下方(平台120侧)传递。此处，为了提高热效率，理想的是使分区B中所产生的热中的、传递至上方(半导体芯片12侧)的热量增加，传递至面方向(分区A、分区C侧)以及下方(平台120侧)的热量减少。在基板30为传热性高的硅晶片的情况下，难以使向面方向(分区A、分区C侧)的传热量减少。另一方面，本例中使平台120包含绝热性高的材料，进而在所述平台120的表面形成多个槽来减少与基板30的接触面积，因此可有效减少向下方(平台120侧)的传热量。即，通过使平台120包含绝热性高的材料，并且减少平台120与基板30的接触面积，可提高利用照射单元108对半导体芯片12进行加热时的热效率。
但是，向平台120的传热量虽说少，但不能成为零。若传递至平台120的热经由所述平台120而被传递至面方向(分区A、分区C侧)，则输入至加热对象以外的半导体芯片12的热量增加。但是，本例的平台120因具有向面方向的热阻力高的第一层122，因此可有效防止热经由平台120而被传递至面方向(分区A、分区C侧)。结果，可减少输入至加热对象以外的半导体芯片12的热量，从而可防止半导体芯片12的由热所引起的劣化或变质。
此外，在对半导体芯片12进行接合(暂时压接、正式压接)时，使用封装头124对所述半导体芯片12赋予压力。在平台120仅具有面方向热阻力高的第一层122的情况下，有可能无法耐受接合时被附加的负荷而基板30的平面度无法维持。因此，本例中，在第一层122之下设置有刚性比第一层122高的第二层123。由此，即便在被附加有大的负荷的情况下，也难以挠曲而可维持基板30的平面度。
接着，对使用所述封装装置100的半导体装置10的制造流程进行说明。在制造半导体装置10的情况下，首先执行将基板30直接载置于平台120的载置步骤。继而，执行使用封装头124将半导体芯片12接合于基板30的上表面的接合步骤。所述接合步骤进而大致分为暂时压接步骤、以及正式压接步骤。
在暂时压接步骤中，封装头124在全部的封装分区34中，一边对多个半导体芯片12进行暂时压接一边进行层叠来形成暂时层叠体STt。具体而言，封装头124预先加热至第一温度T1。在所述状态下，首先，使平台120进行水平移动，将一个封装分区34配置于封装头124的正下方。然后，封装头124将由芯片搬送单元104所搬送的半导体芯片12吸附保持于其前端后下降，并将所述半导体芯片12载置于被封装体(基板30或其它半导体芯片12)上，且以第一负荷F1进行按压。由此，半导体芯片12的NCF 20软化，从而半导体芯片12被暂时压接。重复进行多次所述暂时压接作业，在一个封装分区34形成暂时层叠体STt。若可在一个封装分区34形成暂时层叠体STt，则平台120在水平方向上移动，以使另一封装分区34位于封装头124的正下方。然后，再次使用封装头124进行暂时层叠体STt的形成。以后，对全部的封装分区34进行同样的处理。
若可在全部的封装分区34中形成暂时层叠体STt，则继而执行正式压接步骤。在正式压接步骤中，对多个暂时层叠体STt依序进行正式压接处理。具体而言，封装头124将温度自第一温度T1切换成第二温度T2。另外，在所述状态下，使平台120进行水平移动，将一个封装分区34配置于封装头124的正下方。若成为所述状态，则封装头124下降并以第二负荷F2对一个暂时层叠体STt的上表面进行加压。由此，构成所述一个暂时层叠体STt的多个半导体芯片12被成批地正式压接。
此处，与所述正式压接处理并行地，也进行对配置有所述一个暂时层叠体STt的封装分区34进行局部加热的基板加热步骤。具体而言，对作为对象的封装分区34(封装头124的正下方领域)照射电磁波134，从而仅对所述封装分区34进行局部加热。由此，作为对象的封装分区34的温度上升，配置于所述封装分区上的半导体芯片12也被加热。而且，由此，能以暂时层叠体STt的上层与下层的温度差(层叠体内温度差ΔT)小的状态进行正式压接处理。结果，可进一步提高半导体芯片12的封装质量。
若一个暂时层叠体STt被正式压接，则平台120在水平方向上进行移动以使另一封装分区34位于封装头124的正下方。然后，再次进行使用封装头124的暂时层叠体STt的加热加压以及利用电磁波134的基板30的局部加热。而且，对全部的封装分区34进行同样的处理后，半导体装置10的制造处理完成。
如由以上的说明而明确那样，根据本说明书中公开的半导体装置10的制造方法，对基板30中的载置有作为加热对象的半导体芯片12的封装分区34照射电磁波134，由此利用电磁波134仅对所述封装分区34进行加热。由此，能对作为加热对象的半导体芯片12进行适当的加热，另一方面能防止对并非加热对象的半导体芯片12长时间地输入热。另外，在平台120设置面方向上的热阻力比厚度方向上的热阻力高的第一层122、以及刚性高的第二层123，由此基板30的平面度得到维持，并且可减少经由平台120向并非加热对象的半导体芯片12的传热。结果，可进一步提高半导体芯片12的封装质量。
再者，至此为止所说明的构成均为一例，可适宜进行变更。例如，在所述的说明中，作为基板30，使用了硅晶片，但是也可使用例如包含碳化硅(SiC)或氮化镓(GaN)、蓝宝石等的晶片作为基板30。另外，也可不使用晶片，而使用树脂基板或玻璃基板等作为基板30。
此外，在此种基板、晶片中，也有难以进行利用电磁波134的加热者。所述情况下，只要不将基板30直接载置于平台120，而在平台120与基板30之间配置对电磁波134进行吸收的中间构件140即可。中间构件140只要包含容易吸收电磁波134的材料则并无特别限定。因此，如图7所示，中间构件140可为配置于平台120的上表面的大致平板状构件。另外，作为另一实施方式，中间构件140若包含对电磁波134进行吸收的材料，则也可如图8所示那样为被覆平台120的表面的被膜(例如黑体被膜)。
总之，通过在平台120与基板30之间设置对电磁波134进行吸收的中间构件140，无论基板30的种类如何，可一直利用电磁波134对基板30进行加热。再者，在设置中间构件140的情况下，平台120可为不具有第一层122的结构。例如，可设为在实心块状的平台120上载置中间构件140，并在所述中间构件140上载置基板30。
另外，至此为止的说明中，将设置于平台120的第一层122作为形成有多个槽的部位进行了说明，但第一层122只要面方向上的热阻力比厚度方向上的热阻力高，则也可为其它构成。例如，如图9所示，第一层122与第二层123可为独立构件。其中，在所述情况下，也理想的是第一层122以及第二层123均容易使电磁波134透射。另外，理想的是构成第一层122的原材料的热传导率为构成第二层123的原材料的热传导率以下。因此，例如，在电磁波134的波长为1200nm以下且第二层123包含石英的情况下，第一层122可包含使近红外线透射的光学用塑料材料。
另外，作为另一实施方式，可为了使第一层122的面方向上的热阻力高于厚度方向上的热阻力而将第一层122加工成规定的形状。再者，此处的所谓“加工”并不限定于利用铣刀等将材料的一部分去除之类的机械加工，也包括塑料射出成型之类的成形加工。因此，例如，通过如上所述那样第一层122中形成多个槽，或者如图10所示那样在层内形成孔，可使面方向上的热阻力提高。所述情况下，第一层122与第二层123可经一体化，也可为独立的构件。
另外，在所述的说明中，仅在对暂时层叠体STt成批地进行正式压接的情况下，利用电磁波134对基板30进行加热，但若有必要，在暂时压接时也可利用电磁波134进行加热。另外，在所述的说明中，仅例示了对多个半导体芯片12进行层叠封装的情况，但本说明书中公开的技术当然也可适用于并非进行层叠封装的情况。
另外，在所述的说明中，将封装头124、照射单元108均设为一个，但根据需要，这些也可设为多个，在多个部位同时进行压接处理、基板30的利用电磁波134的加热。
符号的说明
10：半导体装置
12：半导体芯片
14、16：电极端子
18：凸块
30：基板
34：封装分区
36：电极
100：封装装置
102：芯片供给单元
104：芯片搬送单元
106：接合单元
108：照射单元
110：上推部
114：晶粒拾取机
116：移送头
118：旋转台
120：平台
122：第一层
123：第二层
124：封装头
130：控制部
132：电磁波源
134：电磁波
140：中间构件
A、B、C：分区
STc：芯片层叠体
STt：暂时层叠体。

Claims (10)

1.一种封装装置，将半导体芯片接合于作为基板或其它半导体芯片的被封装体而制造半导体装置，所述封装装置的特征在于包括：
平台，具有直接或经由中间构件载置所述基板的第一面、以及与所述第一面为相反侧的第二面；
封装头，相对于所述平台能够进行相对移动，并将所述半导体芯片接合于所述被封装体；以及
照射单元，透射所述平台，并且自所述第二面侧照射对所述基板或所述中间构件进行加热的电磁波，
所述平台具有形成于所述第一面侧的第一层，
所述第一层的面方向上的热阻力大于厚度方向上的热阻力。
2.根据权利要求1所述的封装装置，其中
所述基板热压接有多个所述半导体芯片，
所述照射单元包括变更部件，所述变更部件对所述第一面的所述电磁波的照射区域、以及所述第一面的所述电磁波的照射位置的至少一者进行变更。
3.根据权利要求1所述的封装装置，其中
所述封装头包括加热器，所述加热器对多个所述半导体芯片以暂时压接的状态经层叠而成的暂时层叠体进行加热来进行正式压接，
所述照射单元与所述加热器一起对所述暂时层叠体进行加热。
4.根据权利要求1所述的封装装置，其中
所述平台还具有比所述第一层而形成于更靠所述第二面侧的第二层，
所述第一层的面方向上的热阻力比所述第二层大。
5.根据权利要求4所述的封装装置，其中
所述第二层的刚性比所述第一层高。
6.根据权利要求4或5所述的封装装置，其中
所述第二层是包含所述电磁波能够透射的材料的实心部位，
所述第一层是在上表面形成有多个槽或在层内形成有多个细孔的部位。
7.根据权利要求1至5中任一项所述的封装装置，其中
所述基板为硅晶片，且被直接载置于所述平台，
所述电磁波为波长1200nm以下，
所述基板利用所述电磁波被局部加热。
8.根据权利要求1至4中任一项所述的封装装置，其中
所述基板经由所述中间构件被载置于所述平台，
所述电磁波具有被所述中间构件吸收且不被所述基板吸收的波长，
通过来自利用所述电磁波被局部加热的所述中间构件的传热，对所述基板进行局部加热。
9.一种半导体装置制造方法，将半导体芯片接合于作为基板或其它半导体芯片的被封装体而制造半导体装置，所述半导体装置的制造方法的特征在于包括：
载置步骤，将所述基板直接或经由中间构件载置于平台的第一面；
接合步骤，利用相对于所述平台能够进行相对移动的封装头，将所述半导体芯片接合于所述被封装体；以及
基板加热步骤，与所述接合步骤的至少一部分并行地，自隔着所述平台而配置于所述封装头的相反侧的照射单元照射被所述基板或所述中间构件吸收且透射所述平台的电磁波，由此对所述基板或所述中间构件进行加热，
所述平台具有形成于所述第一面侧的第一层，
所述第一层的面方向上的热阻力大于厚度方向上的热阻力。
10.根据权利要求9所述的半导体装置的制造方法，其中所述接合步骤包括：
暂时压接步骤，利用所述封装头，在所述基板的多个部位依序形成暂时层叠体，所述暂时层叠体是一边将一个以上的所述半导体芯片暂时压接于所述基板上一边进行层叠而成；以及
正式压接步骤，在所述暂时压接步骤后，在所述基板的多个部位依序进行如下处理：所述处理是对一个暂时层叠体自其上表面进行加热加压，由此对构成所述暂时层叠体的一个以上的所述半导体芯片成批地进行正式压接，
所述基板加热步骤与对所述半导体芯片成批地进行正式压接的处理并行地，对所述基板或所述中间构件中的与所述正式压接执行部位对应的部位照射所述电磁波。
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Publication number Priority date Publication date Assignee Title
JP6349539B2 (ja) * 2016-09-30 2018-07-04 株式会社新川 半導体装置の製造方法および実装装置
US11469207B2 (en) * 2020-05-11 2022-10-11 Micron Technology, Inc. Mitigating thermal impacts on adjacent stacked semiconductor devices
CN114597138A (zh) * 2020-12-03 2022-06-07 群创光电股份有限公司 半导体封装的制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1614760A (zh) * 2003-11-07 2005-05-11 国际显示技术株式会社 搭接方法及其搭接装置
JP2005203691A (ja) * 2004-01-19 2005-07-28 Shinkawa Ltd ダイボンディング方法及びその装置
CN102204419A (zh) * 2008-10-31 2011-09-28 东丽株式会社 电子部件和挠性薄膜基板的接合方法及接合装置
US20150050778A1 (en) * 2012-03-07 2015-02-19 Toray Industries, Inc. Method and apparatus for producing semiconductor device
JP2016162920A (ja) * 2015-03-03 2016-09-05 東レエンジニアリング株式会社 実装装置および実装方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5634742A (en) 1979-08-31 1981-04-07 Mitsubishi Plastics Ind Ltd Mat film of rigid vinyl chloride resin
GB2189944B (en) 1986-04-21 1990-06-06 Johnson Electric Ind Mfg Cooling in electric motors
JP3189331B2 (ja) * 1991-11-22 2001-07-16 セイコーエプソン株式会社 接合方法および接合装置
JP3833531B2 (ja) 2001-12-20 2006-10-11 Ｊｕｋｉ株式会社 ダイボンディング方法及びダイボンディング装置
KR101165029B1 (ko) * 2007-04-24 2012-07-13 삼성테크윈 주식회사 칩 가열장치, 이를 구비한 플립 칩 본더 및 이를 이용한플립 칩 본딩 방법
JP2011199184A (ja) * 2010-03-23 2011-10-06 Fujifilm Corp 基板実装装置及び基板実装方法
JP2014007328A (ja) * 2012-06-26 2014-01-16 Shibuya Kogyo Co Ltd ボンディング装置
JP6044885B2 (ja) * 2012-08-08 2016-12-14 パナソニックＩｐマネジメント株式会社 実装方法
CN107112248B (zh) * 2015-11-05 2021-07-27 古河电气工业株式会社 芯片接合装置以及芯片接合方法
US9916989B2 (en) * 2016-04-15 2018-03-13 Amkor Technology, Inc. System and method for laser assisted bonding of semiconductor die
WO2018148275A1 (en) * 2017-02-07 2018-08-16 Rohinni, LLC Apparatus and method for stacking semiconductor devices
US10636761B2 (en) * 2017-08-29 2020-04-28 Electronics And Telecommunications Reearch Institute Method of fabricating a semiconductor package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1614760A (zh) * 2003-11-07 2005-05-11 国际显示技术株式会社 搭接方法及其搭接装置
JP2005203691A (ja) * 2004-01-19 2005-07-28 Shinkawa Ltd ダイボンディング方法及びその装置
CN102204419A (zh) * 2008-10-31 2011-09-28 东丽株式会社 电子部件和挠性薄膜基板的接合方法及接合装置
US20150050778A1 (en) * 2012-03-07 2015-02-19 Toray Industries, Inc. Method and apparatus for producing semiconductor device
JP2016162920A (ja) * 2015-03-03 2016-09-05 東レエンジニアリング株式会社 実装装置および実装方法

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