CN110896103B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN110896103B
CN110896103B CN201910112527.6A CN201910112527A CN110896103B CN 110896103 B CN110896103 B CN 110896103B CN 201910112527 A CN201910112527 A CN 201910112527A CN 110896103 B CN110896103 B CN 110896103B
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insulating film
semiconductor region
region
semiconductor device
semiconductor
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CN110896103A (zh
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井野户秀和
高田修
田村至
寺田直纯
北原宏良
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Abstract

本发明提供能够实现小型化的半导体装置。半导体装置具备：第一导电型的第一半导体区域；第二导电型的第二半导体区域及第三半导体区域，与所述第一半导体区域相接，且相互隔离；所述第二导电型的第四半导体区域，与所述第一半导体区域相接，配置于所述第二半导体区域与所述第三半导体区域之间，被从所述第二半导体区域及所述第三半导体区域隔离；第一绝缘膜，与所述第一半导体区域中的所述第二半导体区域与所述第四半导体区域之间的第一部分相接；第二绝缘膜，与所述第一半导体区域中的所述第三半导体区域与所述第四半导体区域之间的第二部分相接，且比所述第一绝缘膜厚；第一电极，与所述第一绝缘膜相接；以及第二电极，与所述第二绝缘膜相接。

Description

半导体装置
相关申请
本申请享受以日本专利申请2018－170740号(申请日：2018年9月12日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
实施方式涉及半导体装置。
背景技术
在半导体装置中，大多使用了对电压进行转换的电平移位电路。在电平移位电路中，要求在确保规定的耐压及接通电流的基础上尽可能地实现小型化。
发明内容
实施方式提供能够实现小型化的半导体装置。
实施方式的半导体装置具备：第一导电型的第一半导体区域；第二导电型的第二半导体区域及第三半导体区域，与所述第一半导体区域相接，且相互隔离；所述第二导电型的第四半导体区域，与所述第一半导体区域相接，配置于所述第二半导体区域与所述第三半导体区域之间，被从所述第二半导体区域及所述第三半导体区域隔离；第一绝缘膜，与所述第一半导体区域中的所述第二半导体区域与所述第四半导体区域之间的第一部分相接；第二绝缘膜，与所述第一半导体区域中的所述第三半导体区域与所述第四半导体区域之间的第二部分相接，且比所述第一绝缘膜厚；第一电极，与所述第一绝缘膜相接；以及第二电极，与所述第二绝缘膜相接。
实施方式的半导体装置具备：第一导电型的第一半导体区域；第二导电型的第二半导体区域及第三半导体区域，与所述第一半导体区域相接，且相互隔离；第一绝缘膜，与所述第一半导体区域中的所述第二半导体区域与所述第三半导体区域之间的部分相接；电极，与所述第一绝缘膜相接；第二绝缘膜，与所述第三半导体区域相接，且比所述第一绝缘膜厚；以及第三绝缘膜，覆盖所述电极及所述第二绝缘膜。
附图说明
图1是表示第一实施方式的半导体装置的剖面图。
图2是在横轴上表示栅极电压、在纵轴上表示漏极电流来表示晶体管的类型的曲线图。
图3的(a)及(b)是表示第一实施方式的半导体装置的电路图。
图4是表示第一实施方式的半导体装置的制造方法的剖面图。
图5是表示第一实施方式的半导体装置的制造方法的剖面图。
图6是表示第一实施方式的半导体装置的制造方法的剖面图。
图7是表示第一实施方式的半导体装置的制造方法的剖面图。
图8是表示第一实施方式的半导体装置的制造方法的剖面图。
图9是表示第一实施方式的半导体装置的制造方法的剖面图。
图10是表示第一实施方式的半导体装置的制造方法的剖面图。
图11是表示第一实施方式的半导体装置的制造方法的剖面图。
图12是表示第一实施方式的半导体装置的制造方法的剖面图。
图13是表示第一实施方式的半导体装置的制造方法的剖面图。
图14是表示第一实施方式的半导体装置的制造方法的剖面图。
图15是表示第一实施方式的半导体装置的制造方法的剖面图。
图16是表示第一实施方式的半导体装置的制造方法的剖面图。
图17是表示第一比较例的半导体装置的剖面图。
图18是表示第二比较例的半导体装置的剖面图。
图19是表示第二实施方式的半导体装置的剖面图。
具体实施方式
(第一实施方式)
以下，对第一实施方式进行说明。
图1是表示本实施方式的半导体装置的剖面图。
图2是在横轴上表示栅极电压、在纵轴上表示漏极电流来表示晶体管的类型的曲线图。
图3的(a)及(b)是表示本实施方式的半导体装置的电路图。
如图1所示，在本实施方式的半导体装置1中，例如在由单晶的硅(Si)构成的半导体基板10上设有导电型为p型的低电压用p阱11和导电型为p型的高电压用p阱12。低电压用p阱11的上层部分的杂质浓度(载流子浓度)比高电压用p阱12的上层部分的杂质浓度(载流子浓度)高。另外，两个p阱的上层部分包含后述的沟道区域26及27。低电压用p阱11的中层部分及下层部分的杂质浓度与高电压用p阱12的中层部分及下层部分的杂质浓度实质上相等。由低电压用p阱11及高电压用p阱12形成了一个连续的p型半导体区域13。
在低电压用p阱11上设有导电型为n型的源极区域15、LDD区域16及17。源极区域15、LDD区域16及17与低电压用p阱11相接。LDD区域16及17的杂质浓度比源极区域15的杂质浓度低。LDD区域16与源极区域15相接。由源极区域15及LDD区域16形成了一个连续的n型半导体区域18。LDD区域17被从n型半导体区域18隔离。
在高电压用p阱12上设有导电型为n型的漏极区域20、LDD区域21及22。漏极区域20、LDD区域21及22与高电压用p阱12相接。LDD区域21及22的杂质浓度比漏极区域20的杂质浓度低，比LDD区域16及17的杂质浓度低。LDD区域21与漏极区域20相接。由漏极区域20及LDD区域21形成了一个连续的n型半导体区域23。LDD区域22被从n型半导体区域23隔离。
LDD区域22与LDD区域17相接。由LDD区域22及LDD区域17形成了一个连续的n型半导体区域24。n型半导体区域24被从n型半导体区域18及n型半导体区域23隔离。在n型半导体区域18与n型半导体区域24之间夹设有低电压用p阱11的上层部分的一部分，成为沟道区域26。在n型半导体区域23与n型半导体区域24之间夹设有高电压用p阱12的上层部分的一部分，成为沟道区域27。
在LDD区域16、沟道区域26及LDD区域17上设有栅极绝缘膜31。栅极绝缘膜31例如由硅氧化物(SiO)构成，其厚度例如为2.5nm(纳米)以下。栅极绝缘膜31与LDD区域16、沟道区域26及LDD区域17相接。在栅极绝缘膜31上、且沟道区域26的正上方区域设有例如由多晶硅构成的栅极电极32。在栅极绝缘膜31上、且LDD区域16及17的正上方区域设有例如由多晶硅构成的侧壁33。侧壁33与栅极电极32相接。
在LDD区域21、沟道区域27及LDD区域22上设有栅极绝缘膜36。栅极绝缘膜36由与栅极绝缘膜31相同的绝缘材料构成，比栅极绝缘膜31厚。例如，栅极绝缘膜36由硅氧化物构成，厚度为12.5nm以上。栅极绝缘膜36与LDD区域21、沟道区域27及LDD区域22相接。在栅极绝缘膜36上、且沟道区域27的正上方区域设有例如由多晶硅构成的栅极电极37。在栅极绝缘膜36上、且LDD区域21及22的正上方区域设有例如由硅氧化物构成的侧壁38。侧壁38与栅极电极37相接。
栅极绝缘膜36与栅极绝缘膜31相接，其边界成为台阶35。台阶35位于栅极电极32与栅极电极37之间，被从栅极电极32及栅极电极37隔离。换言之，栅极电极32被从栅极绝缘膜31中的栅极绝缘膜36侧的端缘隔离，栅极电极37被从栅极绝缘膜36中的栅极绝缘膜31侧的端缘隔离。
由包含沟道区域26的低电压用p阱11、源极区域15、LDD区域16及17、栅极绝缘膜31、栅极电极32和侧壁33形成了晶体管41。晶体管41是n沟道型MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor：金属氧化物半导体场效应晶体管)，并且是图2所示的E型的晶体管。
由包含沟道区域27的高电压用p阱12、漏极区域20、LDD区域21及22、栅极绝缘膜36、栅极电极37和侧壁38形成了晶体管42。晶体管42是n沟道型MOSFET，并且是图2所示的I型或者D型的晶体管。晶体管42的栅极－漏极耐压比晶体管41的栅极－漏极耐压高。
栅极电极37与栅极电极32连接。栅极电极32及37被施加栅极电位Vg。另一方面，源极区域15被施加源极电位Vs，漏极区域20被施加漏极电位Vd。栅极电位Vg是使晶体管41为导通状态的接通电位Von、或者使晶体管41为非导通状态的关断电位Voff。在一个例子中，源极电位Vs及关断电位Voff是0V(伏特)，漏极电位Vd是5V，接通电位Von是1.5V。另一方面，无论施加到栅极电极37的栅极电位Vg是接通电位Von(例如1.5V)还是关断电位Voff(例如0V)，晶体管42都成为导通状态。
因此，半导体装置1在构造上如图3的(a)所示，为晶体管41与晶体管42以串联的方式连接的电路构成，但若以上述的条件动作，则晶体管42始终成为导通状态，因此如图3的(b)所示，晶体管42作为电阻元件而并非开关元件来发挥功能。由晶体管41及42，构成例如将1.5V的电压转换为5V的电压的电平移位电路。
接下来，对本实施方式的半导体装置的制造方法进行说明。
图4～图16是表示本实施方式的半导体装置的制造方法的剖面图。
如图4所示，例如在由硅的单晶构成的半导体基板10上设定低耐压晶体管区域RL及高耐压晶体管区域RH。然后，在半导体基板10的上层部分，在低耐压晶体管区域RL形成低电压用p阱11，并且在高耐压晶体管区域RH形成高电压用p阱12。
接下来，如图5所示，形成高耐压晶体管区域RH开口的抗蚀剂掩模81。接下来，以抗蚀剂掩模81作为掩模，对成为受体的杂质进行离子注入。由此，在高电压用p阱12的上层部分形成沟道区域27。接下来，将抗蚀剂掩模81除去。
接下来，如图6所示，在氧化环境中进行热处理。由此，在整个面形成栅极绝缘膜36。
接下来，如图7所示，形成低耐压晶体管区域RL开口的抗蚀剂掩模82。接下来，以抗蚀剂掩模82作为掩模而实施RIE(Reactive Ion Etching：反应性离子蚀刻)等蚀刻处理，从而从低耐压晶体管区域RL除去栅极绝缘膜36。
接下来，如图8所示，以抗蚀剂掩模82作为掩模，对成为受体的杂质进行离子注入。由此，在低电压用p阱11的上层部分形成沟道区域26。接下来，将抗蚀剂掩模82除去。
接下来，如图9所示，在氧化环境中进行热处理。由此，在低耐压晶体管区域RL中，在沟道区域26上形成栅极绝缘膜31。栅极绝缘膜31形成为比栅极绝缘膜36薄。另外，在该工序中，在高耐压晶体管区域RH中热氧化也进展，栅极绝缘膜36进一步变厚。在栅极绝缘膜31与栅极绝缘膜36的边界形成台阶35。
接下来，如图10所示，在整个面形成多晶硅膜70。
接下来，如图11所示，以将低耐压晶体管区域RL的一部分及高耐压晶体管区域RH的一部分覆盖的方式，形成抗蚀剂掩模83。接下来，以抗蚀剂掩模83作为掩模实施RIE等蚀刻处理。由此，多晶硅膜70被图案化，在低耐压晶体管区域RL形成栅极电极32，并且在高耐压晶体管区域RH形成栅极电极37。接下来，将抗蚀剂掩模83除去。
接下来，如图12所示，形成使高耐压晶体管区域RH开口的抗蚀剂掩模84。接下来，以抗蚀剂掩模84及栅极电极37作为掩模，对成为供体的杂质进行离子注入。由此，在高电压用p阱12的上层部分中的除了栅极电极37的正下方区域之外的部分形成n型的LDD区域21及22。接下来，将抗蚀剂掩模84除去。
接下来，如图13所示，形成使低耐压晶体管区域RL开口的抗蚀剂掩模85。接下来，以抗蚀剂掩模85及栅极电极32作为掩模，对成为供体的杂质进行离子注入。由此，在低电压用p阱11的上层部分中的除了栅极电极32的正下方区域之外的部分形成n型的LDD区域16及17。接下来，将抗蚀剂掩模85除去。
接下来，如图14所示，在整个面形成绝缘膜71。绝缘膜71例如通过使硅氧化物堆积而形成。
接下来，如图15所示，将绝缘膜71蚀刻。由此，在栅极电极32的侧面上及栅极电极37的侧面上残留绝缘膜71，形成侧壁33及38。
接下来，如图16所示，以栅极电极32及37、侧壁33及38作为掩模，对成为供体的杂质进行离子注入。由此，在低电压用p阱11的上层部分中的除了栅极电极32及侧壁33的正下方区域之外的部分形成n型的源极区域15，并且在高电压用p阱12的上层部分中的除了栅极电极37及侧壁38的正下方区域之外的部分形成n型的漏极区域20。
接下来，在源极区域15、漏极区域20、栅极电极32及37各自的上层部分形成硅化物层(未图示)。接下来，在整个面形成由硅氮化物构成的阻挡膜55(参照图19)。接下来，通过在整个面堆积硅氧化物，形成层间绝缘膜56(参照图19)。接下来，在层间绝缘膜56内，形成到达源极区域15、漏极区域20、栅极电极32及37的各个的接触器(contact)57、58及59(参照图19)。接下来，形成上层布线(未图示)，将栅极电极37与栅极电极32连接。这样，制造出本实施方式的半导体装置1。
接下来，对本实施方式的效果进行说明。
如图1所示，例如，对源极区域15作为源极电位Vs而施加0V，对漏极区域20作为漏极电位Vd而施加5V，对栅极电极32及37作为关断电位Voff而施加0V。由此，晶体管41成为非导通状态。另外，晶体管42是导通状态。
此时，低电压用p阱11与栅极电极32之间及高电压用p阱12与栅极电极37之间被施加电压。栅极电位Vg与源极电位Vs相等，因此施加到高电压用p阱12与栅极电极37之间的电压比施加到低电压用p阱11与栅极电极32之间的电压高。然而，由于在高电压用p阱12与栅极电极37之间夹设有较厚的栅极绝缘膜36，因此能够实现足够的耐压。
另一方面，若对栅极电极32及37作为接通电位Von而施加1.5V，则晶体管41成为导通状态。另外，晶体管42也仍然是导通状态。由此，在源极区域15与漏极区域20之间流过接通电流。此时，由于在低电压用p阱11与栅极电极32之间夹设有较薄的栅极绝缘膜31，因此能够流过较大的电流。换言之，能够在确保一定的接通电流的同时缩短晶体管41及42的栅极宽度、即与图1的纸面垂直的方向上的晶体管41及42的长度。其结果，能够使晶体管41及42小型化。这样，根据本实施方式，能够在确保规定的耐压及接通电流的同时缩小晶体管41及42的栅极宽度，实现半导体装置1的小型化。
另外，根据本实施方式，栅极电极32及37被从栅极绝缘膜31与栅极绝缘膜36之间的台阶35隔离。由此，能够抑制在台阶35的附近形成捕获点(trap site)，能够使半导体装置1的可靠性提高。
(第一比较例)
图17是表示本比较例的半导体装置的剖面图。
如图17所示，在本比较例的半导体装置101中，仅由晶体管41构成了电平移位电路。在该情况下，由于栅极绝缘膜31较薄，因此难以在栅极－漏极间确保必要的耐压。
(第二比较例)
图18是表示本比较例的半导体装置的剖面图。
如图18所示，在本比较例的半导体装置102中，仅由晶体管42构成了电平移位电路。在该情况下，由于栅极绝缘膜36较厚，因此虽然栅极－漏极间的耐压能够确保，但接通电流的电流密度变小。因而，为了确保规定的接通电流而需要加宽栅极宽度。在一个例子中，在半导体装置102中，与第一实施方式的半导体装置1(参照图1)相比，需要约4倍的栅极宽度。
(第二实施方式)
接下来，对第二实施方式进行说明。
图19是表示本实施方式的半导体装置的剖面图。
如图19所示，本实施方式的半导体装置2与前述的第一实施方式的半导体装置1(参照图1)相比，就未设有晶体管42这一点不同。另外，在栅极长度方向上，漏极侧的n型半导体区域53比半导体装置1中的n型半导体区域23(参照图1)长。由此，可实现图3的(b)所示的电路。
具体而言，在半导体装置2未设有LDD区域21、沟道区域27、栅极绝缘膜36、栅极电极37及侧壁38，另一方面，设有导电型为n型的半导体区域51及绝缘膜52。
半导体区域51跨着低电压用p阱11的上层部分与高电压用p阱12的上层部分而设置，并与LDD区域17及22相接。由漏极区域20、LDD区域22、半导体区域51及LDD区域17形成了一个连续的n型半导体区域53。另外，绝缘膜52设于LDD区域22上，与LDD区域22相接。绝缘膜52比栅极绝缘膜31厚。绝缘膜52的组成与侧壁33的组成在实质上相同。
另外，在半导体装置2中，以覆盖源极区域15、栅极电极32、侧壁33、半导体区域51、绝缘膜52及漏极区域20的方式设有例如由硅氮化物(SiN)构成的阻挡膜55。在阻挡膜55上设有例如由硅氧化物构成的层间绝缘膜56。阻挡膜55的组成与绝缘膜52的组成及层间绝缘膜56的组成不同。
在层间绝缘膜56内设有与源极区域15连接的接触器57、与栅极电极32连接的接触器58、以及与漏极区域20连接的接触器59。接触器57与栅极电极32之间的距离D1比接触器59与栅极电极32之间的距离D2短。即，D1＜D2。另外，第一实施方式的半导体装置1中也设有阻挡膜55、层间绝缘膜56、接触器57、58及59，但在图1中省略了图示。
接下来，对本实施方式的效果进行说明。
在半导体装置2中，也在沟道区域26与栅极电极32之间设有较薄的栅极绝缘膜31，因此能够提高接通电流的电流密度。另外，接触器57与栅极电极32之间的距离D1比接触器59与栅极电极32之间的距离D2短，因此在使晶体管41为非导通状态时，沟道区域26的电位相比于漏极电位Vd更接近源极电位Vs。由此，在使栅极电位Vg与源极电位Vs相同而设为关断电位Voff时，能够避免栅极绝缘膜31被施加较高的电压。其结果，半导体装置2的耐压较高。这样，根据本实施方式，也能够在确保规定的耐压与接通电流的同时缩短栅极宽度。本实施方式中的上述以外的构成、动作及效果与第一实施方式相同。
根据以上说明的实施方式，能够实现可小型化的半导体装置。
以上，说明了本发明的几个实施方式，但这些实施方式是作为例子而提出的，并不意图限定发明的范围。这些新的实施方式能够以其他各种方式实施，在不脱离发明的主旨的范围内能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围及主旨中，并且包含在权利要求书所记载的发明及其等同的范围内。
例如，在上述的各实施方式中，说明了晶体管41及42为n沟道型MOSFET的例子，但晶体管41及42也可以是p沟道型MOSFET。另外，除了上述的各构成要素之外，也可以根据需要追加杂质扩散层、绝缘膜、STI(Shallow Trench Isolation：元件分离绝缘膜)等。

Claims (6)

1.一种半导体装置，具备：
第一导电型的第一半导体区域；
第二导电型的第二半导体区域及第三半导体区域，与所述第一半导体区域相接，且相互隔离；
所述第二导电型的第四半导体区域，与所述第一半导体区域相接，配置于所述第二半导体区域与所述第三半导体区域之间，被从所述第二半导体区域及所述第三半导体区域隔离；
第一绝缘膜，与所述第一半导体区域中的所述第二半导体区域与所述第四半导体区域之间的第一部分相接；
第二绝缘膜，与所述第一半导体区域中的所述第三半导体区域与所述第四半导体区域之间的第二部分相接，且比所述第一绝缘膜厚；
第一电极，与所述第一绝缘膜相接；以及
第二电极，与所述第二绝缘膜相接，
所述第一部分的杂质浓度比所述第二部分的杂质浓度高，
所述第二电极与所述第一电极连接，
由所述第一部分、所述第二半导体区域、所述第四半导体区域、所述第一绝缘膜以及所述第一电极形成第一晶体管，
由所述第二部分、所述第三半导体区域、所述第四半导体区域、所述第二绝缘膜以及所述第二电极形成第二晶体管，
所述第一晶体管被切换为导通状态或者非导通状态，所述第二晶体管始终被设为导通状态，
在将所述第一晶体管设为非导通状态时，对所述第三半导体区域施加的电位与对所述第一电极以及所述第二电极施加的电位之差，比对所述第一电极以及所述第二电极施加的电位与对所述第二半导体区域施加的电位之差大。
2.如权利要求1所述的半导体装置，其中，
所述第一晶体管是E型，所述第二晶体管是I型或者D型。
3.如权利要求1所述的半导体装置，其中，
所述第二晶体管的栅极－漏极耐压比所述第一晶体管的栅极－漏极耐压高。
4.如权利要求1所述的半导体装置，其中，
所述第一绝缘膜与所述第二绝缘膜相接。
5.如权利要求1所述的半导体装置，其中，
所述第一电极被从所述第一绝缘膜中的所述第二绝缘膜侧的端缘隔离，
所述第二电极被从所述第二绝缘膜中的所述第一绝缘膜侧的端缘隔离。
6.如权利要求1至5中任一项所述的半导体装置，其中，
所述第一绝缘膜的厚度为2.5nm以下。
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