CN110875284A - 具有部分emi屏蔽的半导体器件以及制作其的方法 - Google Patents

具有部分emi屏蔽的半导体器件以及制作其的方法 Download PDF

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CN110875284A
CN110875284A CN201910806462.5A CN201910806462A CN110875284A CN 110875284 A CN110875284 A CN 110875284A CN 201910806462 A CN201910806462 A CN 201910806462A CN 110875284 A CN110875284 A CN 110875284A
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substrate
film
sip
cover
devices
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CN110875284B (zh
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C.金
K.朴
K.邱
S.赵
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及具有部分EMI屏蔽的半导体器件以及制作其的方法。半导体器件具有衬底。在衬底上设置盖。在衬底上沉积密封剂。将薄膜掩模设置在密封剂上，其中盖从薄膜掩模和密封剂露出。在薄膜掩模、密封剂和盖上形成导电层。在形成导电层之后去除薄膜掩模。

Description

具有部分EMI屏蔽的半导体器件以及制作其的方法
技术领域
本发明一般涉及半导体器件，并且更具体地涉及具有针对电磁干扰（EMI）的部分屏蔽的半导体器件和形成半导体器件的方法。
背景技术
半导体器件常见于现代电子产品中。半导体器件执行广泛范围的功能，诸如信号处理、高速计算、发送和接收电磁信号、控制电子设备、将太阳光变换为电力、以及创建用于电视显示器的视觉图像。半导体器件存在于通信、功率转换、网络、计算机、娱乐和消费者产品的领域中。半导体器件也存在于军事应用、航空、汽车、工业控制器和办公设备中。
半导体器件通常包括处理射频（RF）信号的一些电路。最近的技术进步允许使用系统级封装（SiP）技术以小尺寸、低高度、高时钟频率和良好便携性集成的高速数字和RF半导体封装。SiP器件包括在单个半导体封装中集成在一起的多个半导体组件，例如半导体管芯、半导体封装、集成无源器件和分立有源或无源电气组件。
图1图示了现有技术的SiP器件30。SiP器件30包括设置在PCB或其他衬底32上的多个组件。衬底32包括一个或多个绝缘层34，其中导电层36形成在绝缘层34之上、形成在绝缘层34之间和形成为通过绝缘层34。
半导体管芯40集成为SiP器件30的一部分。半导体管芯40包括有源表面42，其中接触焊盘44形成在有源表面之上。焊料凸块46用于将半导体管芯40的接触焊盘44电气和机械地耦合到衬底32的导电层36。半导体管芯40通过导电层36电气耦合到半导体封装50。
半导体封装50包括半导体管芯52以提供有源功能。半导体管芯52在半导体管芯的有源表面上具有接触焊盘54。半导体管芯52设置在引线框架56的管芯焊盘上并通过接合线57耦合到引线框架的触点或引线。半导体管芯52、接合线57和引线框架56在集成到SiP器件30中之前模塑在密封剂58中。一旦完成，半导体封装50安装在衬底32上，其中焊料59用于机械和电气耦合。在一个实施例中，焊料59是在安装半导体封装50之前印刷到衬底32上的焊膏。
第二密封剂60在集成之后沉积在半导体管芯40、半导体封装50和衬底32上以环境保护SiP器件30。焊料凸块62设置在衬底32的与半导体管芯40和半导体封装50相对的一侧上。随后使用凸块62将SiP器件30安装到更大的电子设备的衬底上。SiP器件30包括多个半导体器件，它们一起操作以实现期望的电气功能。
由于SiP器件30中的高速数字和RF电路，屏蔽电磁干扰是重要的。共形EMI屏蔽已成为减少电磁干扰（EMI）的优选方法。撞击SiP器件30的来自附近器件的EMI可能导致SiP器件的组件内的故障。来自SiP器件30的EMI也可能导致附近器件中的故障。图1图示了共形EMI屏蔽64。EMI屏蔽64是通过溅射形成的薄金属层，其在沉积密封剂60之后共形地涂布在SiP器件30的顶表面和侧表面上。EMI屏蔽64减小了进入和离开SiP器件30的EMI辐射的量值，以减少干扰。在一些实施例中，EMI屏蔽64通过延伸到衬底的边缘的衬底32中的导电层36耦合到接地。
EMI屏蔽64提供EMI干扰的减少。然而，在整个SiP器件30上的保形涂布EMI屏蔽64导致需要充当收发器天线的SiP器件中的器件或模块的问题。EMI屏蔽64降低了所有电磁辐射的量值，包括通信或其他目的所需的辐射。为了使用天线进行发送和接收，半导体管芯40或半导体封装50必须通过EMI屏蔽64外部的天线耦合到电子设备的单独元件。然而，具有集成在SiP器件内的收发器组件以及受益于EMI保护的其他组件将允许进一步改进电子设备的速度、尺寸和功率要求。因此，存在针对半导体封装的部分EMI屏蔽的需要。
附图说明
图1图示了具有共形涂覆的EMI屏蔽层的SiP器件；
图2a-2l图示了在SiP器件的顶表面和侧表面上形成具有部分EMI屏蔽的SiP器件的过程；
图3a-3f图示了在SiP器件的顶表面上形成具有部分EMI屏蔽的SiP器件的过程；
图4a-4f图示了仅在SiP器件的一部分上形成EMI屏蔽的各种替代方案；
图5a-5c图示了使用夹具（jig）将薄膜掩模涂覆到SiP器件的侧表面；
图6图示了将SiP器件安装到薄膜片材，其中在片材中具有开口以形成部分EMI屏蔽；
图7a和7b图示了使用激光烧蚀去除EMI屏蔽层的一部分；
图8a-8f图示了形成部分EMI屏蔽，其中金属盖或柱包围受保护的组件；
图9a和9b图示了用于形成部分EMI屏蔽的步骤的替代次序；和
图10a和10b图示了将SiP器件集成到电子设备中。
具体实施方式
在下面的描述中参考附图在一个或多个实施例中描述了本发明，其中相同的数字表示相同或相似的元件。虽然根据用于实现本发明的目的的最佳模式描述了本发明，但是本领域技术人员将理解，其旨在覆盖可以包括在以下公开内容和附图所支持的所附权利要求及其等同物所限定的本发明的精神和范围内的替代方案、修改和等同物。本文使用的术语“半导体管芯”是指词语的单数和复数形式，并且因此，可以指单个半导体器件和多个半导体器件两者。
图2a是在形成部分EMI屏蔽并单个化成单独的SiP器件之前通过锯道102分开的SiP器件的面板100的横截面图。图示了两个SiP器件，但是通常在单个面板中形成多达数百或数千个SiP器件。面板100形成在类似于现有技术中的衬底32的衬底110上。衬底110包括与一个或多个导电层114交错的一个或多个绝缘层112。在一个实施例中，绝缘层112是芯绝缘板，其中导电层114在顶表面和底表面上图案化，例如覆铜层压衬底。导电层114还包括通过绝缘层112电气耦合的导电通孔。衬底110可以包括在彼此上交错的任何数量的导电层和绝缘层。可以在衬底110的任一侧上形成焊料掩模层。
在衬底110的底表面之上的导电层114的接触焊盘上形成焊料凸块116。凸块116可选地在稍后的处理步骤处形成。在其他实施例中，其他类型的互连结构用于将SiP器件集成到电子设备中，诸如柱形凸块、导电引脚、触点阵列封装（LGA）焊盘、或线接合。
在其他实施例中使用任何合适类型的衬底或引线框架。在一个实施例中，在完成SiP器件之前去除的牺牲衬底上形成面板100。去除牺牲衬底露出用于随后互连到更大的系统中的封装器件上的互连结构。
期望实现SiP器件的预期功能的任何组件安装到或设置在衬底110上并电连接到导电层114。图2a图示了安装在衬底110上的半导体管芯124和半导体封装50作为示例。半导体管芯124是收发器设备，其使用天线128在通过无线电波发送或接收的电磁辐射信号与半导体管芯内的电气信号之间进行转换。通过不在天线128上形成可能阻挡期望的信号的共形EMI屏蔽层将有助于半导体管芯124的收发器功能。另一方面，半导体封装50是受益于EMI屏蔽层的示例性器件。
在一个实施例中，半导体管芯124是用于自驱动车辆中的物体检测的雷达设备，并且半导体封装50包括用于支持雷达功能的存储器和逻辑电路。在其他实施例中，可以将任何期望的组件并入到SiP器件中。这些组件可以包括任何类型的半导体封装、半导体管芯、集成无源器件、分立有源或无源组件或其他电气组件的任何组合。
每个SiP器件中的组件（例如半导体管芯124和半导体封装50）通过合适的互连结构（例如焊料凸块46）安装在衬底110上并连接到衬底110，然后被封装。使用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂或其他合适的涂覆器在半导体管芯124、半导体封装50和衬底110上沉积密封剂或模塑料130。密封剂130可以是聚合物复合材料，诸如环氧树脂、环氧丙烯酸酯、或具有或不具有填料的任何合适的聚合物。密封剂130是非导电的，提供结构支承，并且从外部元件和污染物环境保护SiP器件。
在图2b中，穿过半导体管芯124和半导体封装50之间的每个SiP器件形成沟槽140。沟槽140通过利用光刻掩模的化学蚀刻、激光烧蚀、锯切、反应离子蚀刻、或另一合适的成槽过程来形成。在一个实施例中，沟槽140连续延伸整个面板100长度进出图2b的页面。在其他实施例中，沟槽140较短，例如，仅直接形成在半导体管芯124和半导体封装50之间，并且不延伸到SiP器件的边缘。沟槽140完全穿过密封剂130向下形成到衬底110。导电层114的一部分露出在沟槽140内。导电层114可以被图案化以包括延伸沟槽140的长度的条带以减小导电层和随后沉积的导电材料之间的电阻。
图2c图示了面板100的部分横截面。沟槽140填充有导电材料以形成盖150。使用任何合适的金属沉积技术来形成盖150。可以通过用导电墨水或浆料填充沟槽140或者在沟槽内电镀导电材料来形成盖150。在其他实施例中，盖150被预先形成并插入到沟槽140中。盖150是在半导体管芯124和封装50之间延伸以减小直接从天线128向封装50辐射的EMI的量值（反之亦然）的金属层。在一些实施例中，盖150通过导电层114和凸块116电气耦合到接地节点，以帮助EMI阻挡能力。在其他实施例中，盖150在不连接到导电层114或接地节点的情况下降低EMI。
图2d图示了具有一次形成的八个SiP器件的面板100的一部分的透视图。八个SiP器件中的每个包括盖150，其将器件分成两个不同的区域。盖150被示为在相邻的锯道102之间的中途。然而，盖可以形成用于EMI屏蔽的任何期望尺寸和形状的隔离物。每列或每行的器件共同地共享盖150，因为在面板100的整个宽度或长度形成沟槽140和盖150。在其他实施例中，每个器件具有可以或可以不延伸到锯道102的单独的盖150。
图2e和2f分别示出了面板100的横截面和透视图，其中薄膜152设置在每个SiP器件的一半之上。薄膜152是胶带、金属箔膜、金属箔带、聚酰亚胺膜或任何其他合适的薄膜掩模。在其他实施例中，金属、塑料或硅树脂掩模用于薄膜152。任何薄膜152选项可以包括粘合剂以提供薄膜与密封剂130的机械附接。粘合剂可以是紫外（UV）释放、热释放、或以其他方式配置成允许方便去除薄膜152。薄膜152也可以是通过任何适当的薄膜沉积技术而沉积的任何合适的绝缘、钝化或光致抗蚀剂层。薄膜152涂覆在直接在密封剂130上的面板100的顶表面上，并与盖150平行地延伸。盖150保持从薄膜152露出，使得随后涂覆的屏蔽层将接触盖以形成连续的EMI屏蔽。
薄膜152以条带涂覆在半导体管芯124上。薄膜152沿着面板100的整个长度平行于盖150延伸，并且从每个盖到相邻的锯道102垂直地跨越面板100。因此，具有半导体管芯124的每个SiP器件的侧完全被薄膜152覆盖。在其他实施例中，具有半导体管芯124的侧的仅一部分被薄膜152覆盖。薄膜152可以作为小片薄膜直接涂覆在每个半导体管芯124上而不延伸到盖150或任何锯道102。
在图2g中，使用锯条、水射流或激光切割工具154来切穿密封剂130和衬底110并将每个器件分离成单独的SiP器件156而在锯道102处单个化面板100，如图2h中所示。每个SiP器件156通过盖150分成两侧。开放侧156a在开放侧上具有薄膜152，并且屏蔽侧156b没有薄膜。开放侧156a被称为开放侧，因为当形成后续屏蔽层时薄膜152操作为掩模以使开放侧至少部分地没有屏蔽层。理想地发射或接收电磁辐射的任何器件（例如半导体管芯124）放置在薄膜152下面的开放侧156a内。通过屏蔽被保护免受EMI的任何器件（例如半导体封装50）放置在屏蔽侧156b内。开放侧156a和屏蔽侧156b上的器件可以通过导电层114跨越由盖150创建的边界彼此电气耦合，或者通过SiP器件156集成到的更大电子设备的下层衬底彼此电气耦合。
在示出了相同处理步骤的两个不同视图的图2i和2j中，在SiP器件156上形成共形屏蔽层160。通过喷涂、电镀、溅射或任何其他合适的金属沉积过程来形成屏蔽层160。屏蔽层160可以由铜、铝、铁或用于EMI屏蔽的任何其他合适材料来形成。在一些实施例中，在图2g中的单个化期间，面板100被放置在具有可选的热释放或界面层的载体上。单个化的SiP器件156保留在用于涂覆屏蔽层160的相同的载体上。因此，形成屏蔽层160期间的相邻SiP器件156之间的空间等同于切割工具154的锯缝的宽度。然而，屏蔽层160的厚度足够低，使得相邻SiP器件156的屏蔽层不会接触，并且封装保持单个化在载体上。在其他实施例中，SiP器件156在单个化之后并且在形成屏蔽层160之前设置在单独的载体上。
屏蔽层160完全覆盖SiP器件156的每个露出表面，包括顶表面和所有四个侧表面。在形成屏蔽层160时用导电材料涂布密封剂130的所有露出表面，薄膜152也是如此。具有衬底110和凸块116的SiP器件156的底表面通常不被屏蔽层160覆盖，这是因为溅射方法是从上到下并且仅覆盖侧向的或面向上的表面，或者因为载体上的界面层完全覆盖底表面并且操作为一种掩模。
在沉积屏蔽层160之后，去除薄膜152，如图2k和2l所示，其是相同处理步骤的两个不同视图。去除薄膜152还去除薄膜上的屏蔽层160的部分并且使密封剂130露出在封装的开放侧156a上。
SiP器件156包括具有封装50的屏蔽侧156b，其具有完全包围屏蔽侧的EMI屏蔽。屏蔽层160和盖150组合地在屏蔽侧156b的侧周围和在其顶部之上完全且连续地延伸。半导体封装50通过导电层114和凸块116保持电气耦合到半导体管芯124、开放侧156a的其他器件和外部世界。
开放侧156a完全被在开放侧的各侧（类似于屏蔽侧156b）周围的EMI屏蔽包围。然而，由于薄膜152已用作掩模，开放侧156a的顶部没有屏蔽层160。半导体管芯124上的屏蔽层160中的开口允许天线128发送和接收电磁信号，而信号不会被屏蔽层显著地抑制或阻挡。盖150允许屏蔽层160具有用于天线128的开口而不会损害半导体封装50的EMI屏蔽，因为屏蔽侧156b中的半导体封装仍然被EMI屏蔽完全包围。
图3a-3f图示了用于形成具有部分EMI屏蔽的半导体封装的替代方法。继续图2f，图3a和3b示出了在涂覆薄膜152之后但在单个化面板之前在面板100上形成的屏蔽层170。正如屏蔽层160一样，屏蔽层170直接形成在盖150的顶表面上以形成连续的屏蔽层。与屏蔽层160不同，屏蔽层170不覆盖最终封装的侧表面，因为层170是以面板级别而不是以单元级别形成。锯道102仍然被密封剂130占据，密封剂130阻挡屏蔽层170在单独的器件的侧表面上形成。图3a和3b仅图示了面板100的一部分。面板100的未图示部分导致屏蔽层170不形成在图3a和3b中的可见侧表面上。屏蔽层170通过任何方法形成，并且由上面针对屏蔽层160提到的任何材料形成。
在图3c和3d中，从面板100去除薄膜152，其还去除半导体管芯124上的屏蔽层170的部分。图3e示出了在形成屏蔽层170之后而不是如上所述在形成屏蔽层160之前通过切割工具172单个化面板100。单个化产生如图3f所示的SiP器件176。SiP器件176包括盖150，以保护屏蔽侧176b免受直接来自天线128或开放侧176a中的其他器件的辐射。屏蔽层170保护屏蔽侧176b免受从上方指向SiP器件176的辐射。
虽然屏蔽侧176b没有像屏蔽层160那样在所有侧上完全受到保护，但是SiP器件176的部分屏蔽在其中主要关注点是来自开放侧176a和从上方的辐射的实施例中是有用的。例如，具有SiP器件176的电子设备可以为SiP器件的侧提供足够的屏蔽，但是由于期望使半导体管芯124发送和接收信号，所以不完全保护顶部。作为另一示例，封装50的主要EMI关注点可以是由天线128广播的雷达或类似信号，其进行反射然后由天线接收。这种反射信号将主要从上方接收，并被屏蔽层170充分阻挡。
图4a-4f图示了在涂覆薄膜152之前单个化面板100然后形成部分屏蔽的各种方式。从图2c和2d继续，在顶表面上不形成薄膜和任何屏蔽层的情况下使用切割工具178沿着锯道102将面板100切割成多个SiP器件180（图4b中所示）。SiP器件180确实具有盖150，其将封装分成开放侧180a和屏蔽侧180b。
在图4c中，多个SiP器件180成行地设置在合适的衬底或载体上，其中每个封装的开放侧180a彼此对准。封装可以在任何方向上定向，即，一行封装可以在开放侧180a朝向左侧的情况下定向，而另一行使开放侧朝向右侧定向，或者一行内的封装可以定向在不同的方向上，如果期望的话，只要开放侧180a被对准用于作为带或其他条带的长度的薄膜190的涂覆。
一旦SiP器件180布置成具有对准的开放侧180a，则在开放侧上涂覆膜190，其中每行共同地共享薄膜的条带。薄膜190类似于上面的薄膜152，但是以单元级别而不是在面板100上涂覆。一片薄膜190覆盖整行开放侧180a。
当SiP器件180处于如图4c所示的状态时，可以涂覆屏蔽层。取决于所使用的电镀方法，一旦去除薄膜190，最终屏蔽层可以看起来像屏蔽层160（图2l中），其中所有侧面都被完全覆盖，或者薄膜190可以操作为阴影掩模并且部分地阻挡侧表面免于被覆盖。
替代地，可以在涂覆屏蔽层之前使用激光或其他切割工具来去除SiP器件180之间的薄膜190，如图4d所示。薄膜190也可以作为单独件涂覆在每个SiP器件180上以直接达到图4d中所示的状态，而不首先跨整行器件涂覆薄膜作为带的条带（如图4c所示）。薄膜190件可以完全覆盖开放侧180a，如图4d所示，或者可以是仅部分覆盖开放侧的更小的件。当薄膜190作为单独件涂覆在每个SiP器件180上时，开放侧180a可以不对准。电镀屏蔽层导致看起来非常类似于图21的最终设备，其中由于存在薄膜190，仅开放侧180a的顶表面没有屏蔽层。薄膜190使盖150的顶部露出，因此屏蔽层直接形成在盖上以形成连续的EMI屏蔽。
图4e示出了使用薄膜200，其类似于上面的薄膜152和190，但是被形成为可以覆盖两行封装的开放侧180a的较宽条带。每行SiP器件180沿与相邻行相反的方向定向，使得一行中的器件具有面向另一行的开放侧180a的开放侧180a。薄膜200足够宽以覆盖两行的开放侧180a，其中行的开放侧朝向彼此定向。屏蔽层可以镀有如图4e所示那样配置的薄膜200，在这种情况下，开放侧180a的侧表面可以保持没有屏蔽。
替代地，切割工具202可以用于去除器件之间的过量的薄膜200，如图4f所示。薄膜200保持延伸在相邻行中的对应SiP器件180之间。薄膜200可以保护在薄膜下面彼此面对的SiP器件180的侧表面，同时允许开放侧180a的面向和远离观察者的侧表面在屏蔽层中被覆盖。切割工具202还可以用于去除其中开放侧180a面对彼此的直接相邻器件之间的薄膜200的部分。在其他实施例中，薄膜200直接以图4f所示的配置涂覆，即，作为单独的件，每个件跨两个相邻器件延伸，而不必在涂覆薄膜200之后切割。
图5a-5c图示了使用夹具将薄膜200涂覆到SiP器件180。从图4e继续的一个选项是在每对器件之间中途切割薄膜200，然后使用夹具204来按压薄膜200向下到SiP器件180的侧表面上，如图5a所示。图5b图示了使用夹具204成对地按压薄膜200向下到SiP器件180上，同时在首先位置（first place）中涂覆薄膜。薄膜200保持为未切割的条带。薄膜200包括从卷轴或薄膜的其他源脱落的尾部210。尾部210保持相对拉紧并且在由处理设备的控制下。薄膜200的源从一对器件移动到下一对，而夹具204将薄膜向下按压到每对器件上。
一旦通过夹具204将薄膜200按压在每个SiP器件180上，就在封装上沉积屏蔽层212，如图5c所示。薄膜200保护开放侧180a的顶表面和所有三个侧表面，使得开放侧在SiP器件180的任何外表面上没有屏蔽层212。薄膜200不在屏蔽侧180b上延伸，因此屏蔽侧具有在所有三个外侧表面上的屏蔽层212。如在上面的其他实施例中，盖150覆盖屏蔽侧180b的第四侧表面，以给予屏蔽侧EMI屏蔽，其在所有侧表面和顶表面上连续延伸。
图6图示了用于掩蔽多个SiP器件180的薄膜220。薄膜220包括对应于屏蔽侧180b的顶部的开口或口袋。将SiP器件180翻转（flip）加载到薄膜220上，使得盖150的顶部和屏蔽侧180b通过薄膜开口而露出。薄膜220可以是任何合适的尺寸并容纳任何数量的SiP器件180。在薄膜220中以任何期望的位置和定向形成开口，以容纳期望数量的封装。替代地，可以在使用激光烧蚀或另一合适过程将SiP器件180安装到薄膜上之后穿过薄膜220形成开口。
通过薄膜220中的开口将屏蔽层电镀到SiP器件180上。如图3f所示，如果开口是小于那些表面的相同尺寸，则屏蔽层仅限于盖150的顶表面和屏蔽侧180b。在其他实施例中，穿过薄膜220的开口足够大以允许电镀屏蔽侧180b的侧表面。在一些实施例中，一旦安装SiP器件180，就翻转薄膜220，使得从上方发生屏蔽层的溅射。
图7a-7b图示了使用激光烧蚀而不是使用薄膜掩模去除屏蔽层的一部分。在图7a中，SiP器件180在顶部和所有侧表面上被屏蔽层230完全覆盖，类似于图2j。然而，与图2j不同，在屏蔽层230下面没有薄膜掩模。在图7b中用激光器232通过激光烧蚀去除开放侧180a上的屏蔽层230。可以在开放侧180a上完全或部分地去除屏蔽层230。激光烧蚀也可以用于去除开放侧180a的一些或所有侧表面上的屏蔽层230。屏蔽层230保持延伸在盖150的顶部上，使得屏蔽侧180b被顶部和侧面上的EMI屏蔽完全且连续地围绕。
图8a-8f图示了形成SiP器件，其具有包围要从EMI被保护的组件的盖，而不是仅将SiP器件分成两个部分，如上面的盖150的情况那样。图8a开始说明制造过程，其中面板240处于与图2b所示的类似状态。受益于EMI保护的一些组件（例如封装50）与其他组件（例如半导体管芯124）一起设置在衬底110上，其将EMI辐射用于其预期功能。不是如图2b所示在两者之间形成沟槽140，图8a示出了完全在每个半导体封装50周围形成的沟槽242。沟槽242在其他方面类似于沟槽140，并向下延伸到衬底110以露出接触焊盘或衬底的导电层。沟槽242可以是不仅仅是正方形或矩形的任何合适的形状以及任何合适的尺寸，包括包围每个器件的整个侧面以被屏蔽并与锯道102重叠。在一个实施例中，沟槽242与沟槽140一样沿每个器件的中部向下延伸，并且还沿着锯道102完全在器件的一侧周围。当器件被单个化时，单个化部分地穿过形成在沟槽242中的盖。
在图8b中，盖250被形成或设置在沟槽242内。盖250类似于盖150，并且可以通过在沟槽242内沉积导电膏、导电墨水或另一导电材料来形成。替代地，盖250可以单独形成，然后插入沟槽中。
在图8c中，在面板240的顶表面上涂覆薄膜256。薄膜256类似于上面的薄膜152，并且覆盖除了盖250和盖所围绕的区域之外的面板240的所有顶表面。薄膜256可以具有预先切割的与盖250的形状对应的开口，或者薄膜可以完全覆盖面板240，然后通过激光烧蚀、蚀刻或另一合适过程来形成开口。
在图8d中，屏蔽层260形成在面板240上，包括薄膜256。屏蔽层260类似于上面的屏蔽层160。在图8e中去除薄膜256以仅在盖250和盖250所围绕的区域上方留下屏蔽层260。沿锯道102的单个化产生如图8f所示的SiP器件266。SiP器件266的屏蔽区域被盖250完全包围并被屏蔽层260覆盖。盖250内的器件（例如半导体封装50）被很好地保护免受EMI，而盖250外部的器件能够广播和接收电磁信号。
使用包围要屏蔽的区域的盖250而不是盖150以将半导体封装分成两个区域与以上说明的处理方法兼容。例如，SiP器件266可以在涂覆薄膜256之前被单个化，然后如图6中那样翻转加载到薄膜上。在一些实施例中，薄膜256形成在盖250所围绕的区域外部，而不是在盖250内。然后，当去除薄膜256时，盖250外部的区域保持被屏蔽，而盖250内的器件在其上方没有屏蔽，从而允许传输电磁信号。在封装的侧表面上形成的屏蔽层（诸如图21中的屏蔽层160）将导致盖250外部的区域在顶部和所有侧面上被完全包围，而由盖250包围的组件在上方没有盖。
图9a和9b图示了其中在沉积密封剂之前形成盖的处理步骤的替代次序。在图9a中，盖270被形成、设置或安装在半导体管芯124和半导体封装50之间的衬底110上。盖270可以在其他组件安装在衬底110上之前或之后提供。盖270可以单独形成并且设置在衬底110上或者直接形成在衬底110上，这例如通过使用掩模层。盖270可以是线性的并且如上面的盖150那样将每个器件分成两个，或者可以像盖250一样包围要保护的区域。
在图9b中，密封剂130沉积在半导体管芯124、封装50、盖270和衬底110上。在一些实施例中，密封剂130的顶表面被平坦化以露出盖270。一旦沉积密封剂130，则可以执行上述过程中的任何一个以在封装上形成部分屏蔽层。图9b与上面的图2c或图8b处于相同的状态。任何上述器件都可以在沉积密封剂130之前形成盖150或250。
图10a和10b图示了将任何上述SiP器件（例如，SiP器件156）并入电子设备中。图10a图示了作为电子设备的一部分安装到PCB或其他衬底342上的来自图21的SiP器件156的部分横截面。凸块116回流到PCB 342的导电层344上，以将SiP器件156物理地附接并电气连接到PCB。在其他实施例中，使用热压缩或其他合适的附接和连接方法。可以通过柱形凸块、焊区（land）、引脚、接合线或任何其他合适的结构来提供互连，而不是凸块。在一些实施例中，在SiP器件156和PCB 342之间使用粘合剂或底部填充层（underfill layer）。半导体管芯124和封装50通过导电层114和凸块116电气耦合到导电层344并且彼此电气耦合。
图10b图示了包括PCB 342的电子设备340，其中多个半导体封装安装在PCB的表面上，包括SiP器件156。电子设备340可以具有一种类型的半导体封装，或者多种类型的半导体封装，这取决于涂覆。
电子设备340可以是使用半导体封装来执行一个或多个电气功能的独立系统。替代地，电子设备340可以是更大系统的子组件。例如，电子设备340可以是平板计算机、蜂窝电话、数字相机、通信系统或其他电子设备的一部分。电子设备340也可以是图形卡、网络接口卡或插入计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、ASIC、逻辑电路、模拟电路、RF电路、分立有源或无源器件、或其他半导体管芯或电气组件。
在图10b中，PCB 342提供用于安装在PCB上的半导体封装的结构支承和电气互连的通用衬底。使用蒸发、电解电镀、无电电镀、丝网印刷或其他合适的金属沉积过程来在PCB342的表面上或层内形成导电信号迹线344。信号迹线344提供半导体封装、安装的组件和其他外部系统或组件之间的电气通信。迹线344还根据需要提供到半导体封装的电源和接地连接。
在一些实施例中，半导体器件具有两个封装级别。第一级别封装是用于将半导体管芯机械地和电气地附接到中间衬底的技术。第二级别封装涉及将中间衬底机械地和电气地附接到PCB 342。在其他实施例中，半导体器件可以仅具有第一级别封装，其中管芯机械地和电气地直接安装到PCB 342。
出于说明的目的，在PCB 342上示出了几种类型的第一级别封装，包括接合线封装346和倒装芯片348。另外，包括球栅阵列（BGA）350、凸块芯片载体（BCC）352、LGA 356、多芯片模块（MCM）358、四方扁平无引线封装（QFN）360和晶片级别芯片规模封装（WLCSP）366的几种类型的第二级别封装被示出与SiP器件156一起安装在PCB 342上。导电迹线344将设置在PCB 342上的各种封装和组件电气耦合到SiP器件156，从而将SiP器件内的组件用于PCB上的其他组件。
取决于系统要求，配置有第一和第二级别封装类型的任何组合的半导体封装的任何组合以及其他电子组件可以连接到PCB 342。在一些实施例中，电子设备340包括单个附接的半导体封装，而其他实施例要求多个互连的封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预制组件并入到电子设备和系统中。因为半导体封装包括复杂的功能，所以可以使用较便宜的组件和简化的制造过程来制造电子设备。由此产生的器件不太可能发生故障并且制造得更便宜，从而导致消费者的更低成本。
虽然已经详细说明了本发明的一个或多个实施例，但是本领域技术人员将理解，在不脱离以下权利要求中所阐述的本发明的范围的情况下，可以对那些实施例进行修改和改编。

Claims (15)

1.一种制作半导体器件的方法，包括：
提供衬底；
在衬底上设置盖；
在衬底上沉积密封剂；
将薄膜掩模设置在密封剂上，其中盖从薄膜掩模和密封剂露出；
在薄膜掩模、密封剂和盖上形成导电层；和
在形成导电层之后去除薄膜掩模。
2.根据权利要求1所述的方法，还包括在沉积密封剂之后并且在设置薄膜掩模之前单个化衬底。
3.根据权利要求1所述的方法，还包括在设置薄膜掩模之后并且在形成导电层之前单个化衬底。
4.根据权利要求1所述的方法，还包括在形成导电层之后单个化衬底。
5.根据权利要求1所述的方法，还包括形成盖以包围设置在衬底上的组件。
6.根据权利要求1所述的方法，还包括用夹具涂覆薄膜掩模。
7.一种制作半导体器件的方法，包括：
提供衬底，包括设置在衬底上的盖和密封剂；
在密封剂上设置薄膜掩模；
在薄膜掩模、密封剂和盖上形成导电层；和
在形成导电层之后去除薄膜掩模。
8.根据权利要求7所述的方法，还包括在密封剂的侧表面上形成导电层。
9.根据权利要求7所述的方法，其中，还包括将薄膜掩模设置在密封剂上，其中盖从密封剂和薄膜掩模露出。
10.根据权利要求7所述的方法，还包括在将密封剂沉积在衬底上之前在衬底上形成盖。
11.一种半导体器件，包括：
衬底；
设置在衬底上的盖；
沉积在衬底上并在盖周围的密封剂；和
形成在密封剂的顶表面的第一部分和盖上的导电层。
12.根据权利要求11所述的半导体器件，其中导电层在密封剂的侧表面上延伸。
13.根据权利要求11所述的半导体器件，其中导电层接触盖的顶表面和侧表面。
14.根据权利要求11所述的半导体器件，其中密封剂的顶表面的第二部分没有导电层。
15.根据权利要求11所述的半导体器件，其中盖包围设置在衬底上的组件。
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