CN110729249A - 一种焊盘下器件的双顶层金属cmos工艺 - Google Patents
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Abstract
本发明一种焊盘下器件的双顶层金属CMOS工艺,在硅衬底上形成有源区,之后在NMOS的有源区上形成P阱,在PMOS的有源区上形成N阱,然后形成场氧化层和进行阈值注入,形成栅氧层和多晶栅,接下来按照0.13~0.8μm硅栅CMOS工艺和大于0.8μm且小于3μm硅栅CMOS工艺得到钝化刻蚀的硅衬底,完成现有标准厚度顶层金属CMOS工艺,最后通过增加一次金属淀积、光刻和刻蚀工艺,再配合合金操作得到焊盘处金属厚度加厚的电路,将焊盘金属厚度进行了增加;可以充分缓冲键合过程中存在的应力,对任意金属层数的产品均适用,适用范围广,既提高了设计的灵活性,对电路版图的排布没有任何限制,又减小了芯片面积。
Description
技术领域
本发明涉及硅微电子技术领域,特别是涉及超大规模集成电路加工技术领域,具体为一种焊盘下器件的双顶层金属CMOS工艺。
背景技术
在大于3μm的大尺寸CMOS工艺中,焊盘的数量较少,在芯片中所占面积较小,但随着CMOS工艺按照摩尔定律等比例缩小,器件尺寸会快速缩小,而受键合工艺的限制,焊盘尺寸变小的速度却很慢;同时,芯片功能的复杂化导致输入输出焊盘数量不断增加,因此焊盘在芯片中所占面积越来越大。对于0.13~3μm CMOS工艺,顶层金属的厚度在0.9~1.5μm左右,无法缓冲键合过程中存在较大的应力,因此,设计规则往往规定焊盘下不允许排布器件,且焊盘距离器件10~15μm以上;但如果焊盘下允许排布器件,即焊盘下器件,(英文名称为Device Under Pad,简写为DUP),便可以极大地提升芯片设计的灵活性,同时会节省芯片面积,从而降低单个芯片的费用。
为了实现DUP,可以简单地将顶层金属加厚以缓冲键合应力从而避免对器件的损伤,但是顶层金属加厚后芯片尺寸将急剧增大,因为顶层金属纵向尺寸越大,相应的横向最小尺寸,即线宽和间距,也越大。例如,顶层金属厚度3μm所允许的横向最小尺寸为1.5μm,远大于厚度0.8μm的横向最小尺寸0.6μm。现有的方法是在不增加顶层金属厚度和最小尺寸的情况下实现DUP。国内外一些工艺中规定当金属层数≥3层时可以实现DUP,如文献“ESDprotection under grounded-up bond pads in 0.13μm eight-level copper metal,fluorinated silicate glass low-k international dielectric CMOS processtechnology”(IEEE Electron Device Letters,2001年第22期第342页),但这种方法实际上通过保证焊盘上累加足够厚度的金属和氧化层来缓冲键合应力,对于金属层数较少的产品则无法实现DUP。另外,对于功率芯片可以采用双金属工艺,见美国专利“Method forforming a patterned thick metallization atop a power semiconductor chip”(专利号8067304,2010年7月6日),通过工艺将整个芯片的金属厚度加厚以满足大电流的要求。
综上所述,在0.13~3μm CMOS工艺中,金属层数较少的产品无法实现DUP。
发明内容
针对现有技术中存在的问题,本发明提供一种焊盘下器件的双顶层金属CMOS工艺,通过增加焊盘金属的厚度缓解压焊应力以实现DUP,既提高了设计的灵活性,又减小了芯片面积。
本发明是通过以下技术方案来实现:
一种焊盘下器件的双顶层金属CMOS工艺,包括如下步骤,
步骤1,在硅衬底上依次生长垫氧和氮化硅,通过光刻和刻蚀在无氮化硅的区域形成场区,在有氮化硅覆盖的区域形成有源区,有源区分为NMOS的有源区和PMOS的有源区;
在NMOS的有源区上形成P阱,在PMOS的有源区上形成N阱;
步骤2,在步骤1得到的硅衬底无氮化硅覆盖的区域上通过氧化和推阱形成场氧化层,然后将有源区表面的氮化硅剥离,最后在所得的硅衬底上进行阈值注入;
步骤3,在步骤2得到的硅衬底的有源区上形成栅氧层,之后在栅氧层的表面上形成多晶栅;
步骤4,步骤3得到的硅衬底中,对于0.13~0.8μm硅栅CMOS工艺,先在形成P阱的NMOS有源区进行N型轻掺杂源漏注入,并在形成N阱的PMOS有源区进行P型轻掺杂源漏注入,之后在所得的硅衬底表面形成侧墙,最后按硅栅CMOS工艺依次进行源漏注入、形成孔层、金属化和钝化,得到钝化刻蚀的硅衬底;
对于大于0.8μm且小于3μm硅栅CMOS工艺,先在形成P阱的NMOS有源区进行N+源漏注入,并在形成N阱的PMOS有源区进行P+源漏注入,最后按硅栅CMOS工艺,在轻掺杂源漏注入的硅衬底上先形成孔层,之后进行金属化和钝化,得到钝化刻蚀的硅衬底;
步骤5,在钝化刻蚀的硅衬底表面溅射形成厚铝,然后进行厚铝光刻,定义出焊盘厚铝,之后对焊盘厚铝进行刻蚀,最后对焊盘厚铝刻蚀的硅衬底进行合金操作,得到焊盘处金属厚度加厚的电路。
优选的,步骤5中,所述的厚铝为AlSiCu金属层。
优选的,步骤5中,在350~450℃下对焊盘厚铝刻蚀的硅衬底进行合金操作。
优选的,步骤5中,焊盘厚铝刻蚀的硅衬底合金的时间为30~60min。
优选的,步骤5中,焊盘厚铝刻蚀的硅衬底在体积比为(3~10):1的N2:H2气氛中进行合金。
优选的,步骤1中,所述的硅衬底为电阻率为1~20Ohm·cm、晶向为(100)的硅晶圆。
优选的,步骤5中,采用湿法工艺对焊盘厚铝进行刻蚀。
与现有技术相比,本发明具有以下有益的技术效果:
本发明焊盘下器件的双顶层金属CMOS工艺,先在硅衬底上形成有源区,之后在NMOS的有源区上形成P阱,在PMOS的有源区上形成N阱,然后形成场氧化层和进行阈值注入,形成栅氧层和多晶栅,接下来按照0.13~0.8μm硅栅CMOS工艺和大于0.8μm且小于3μm硅栅CMOS工艺得到钝化刻蚀的硅衬底,至此完成了现有标准厚度顶层金属CMOS工艺,最后通过增加一次金属淀积、光刻和刻蚀工艺,再配合合金操作得到焊盘处金属厚度加厚的电路,这样最终将焊盘金属厚度进行了增加。由于焊盘金属厚度变厚,可以充分缓冲键合过程中存在的应力,对任意金属层数的产品均适用,适用范围广,既提高了设计的灵活性,对电路版图的排布没有任何限制,又减小了芯片面积;对原有基线工艺的产品设计规则没有更改,并与原有基线设计规则完全一致,版图生成时可以规定钝化图层的反版,适当放大一定尺寸作为焊盘厚铝光刻图层,不需要进行专门的设计;在原有CMOS工艺仅仅增加一道光刻工艺,成本可控。
附图说明
图1为本发明所述的标准工艺顶层金属淀积示意图。
图2为本发明所述的标准工艺顶层金属光刻示意图。
图3为本发明所述的标准工艺顶层金属刻蚀示意图。
图4为本发明所述的标准工艺顶层金属刻蚀去胶后示意图。
图5为本发明所述的标准工艺钝化层淀积示意图。
图6为本发明所述的标准工艺钝化光刻示意图。
图7为本发明所述的标准工艺钝化刻蚀示意图。
图8a为本发明所述的标准工艺钝化刻蚀去胶后示意图。
图8b为本发明所述的焊盘厚铝工艺钝化刻蚀去胶后示意图。
图9为本发明所述的焊盘厚铝工艺焊盘厚铝淀积示意图。
图10为本发明所述的焊盘厚铝工艺焊盘厚铝光刻示意图。
图11为本发明所述的焊盘厚铝工艺焊盘厚铝刻蚀示意图。
图12为本发明所述的焊盘厚铝工艺焊盘厚铝刻蚀去胶后示意图。
图13a为基于0.5μmCMOS工艺的焊盘厚铝湿法刻蚀扫描电子显微镜形貌图。
图13b为图13a的局部放大图。
图14a为0.5μm CMOS的电学参数测试NMOS阈值的对比结果图。
图14b为0.5μm CMOS的电学参数测试PMOS阈值的对比结果图。
图14c为0.5μm CMOS的电学参数测试NMOS漏电的对比结果图。
图14d为0.5μm CMOS的电学参数测试PMOS漏电的对比结果图。
图中:10-衬底,11-层间介质层,12-多晶栅,13-接触孔,14-Ti粘附层,14a-焊盘Ti粘附层,14b-电路Ti粘附层,15-TiN阻挡层,15a-焊盘TiN阻挡层,15b-内部电路TiN阻挡层,16-AlSiCu金属层,16a-焊盘AlSiCu金属层,16b-内部电路AlSiCu金属层,17-第一层光刻胶,17a-焊盘第一层光刻胶,17b-内部电路第一层光刻胶,18-钝化层,19-第二层光刻胶,20-焊盘厚铝,21-第三层光刻胶,31-金属间介质层。
具体实施方式
下面结合具体的实施例对本发明做进一步的详细说明,所述是对本发明的解释而不是限定。
本发明一种焊盘下器件的双顶层金属CMOS工艺,是能提高焊盘金属厚度的双顶层金属工艺,在现有标准厚度顶层金属CMOS工艺基础上增加了焊盘上金属厚度。
如果是多层金属工艺,顶层金属下面还有金属层,但这并不影响本发明内容的陈述。以单层金属工艺为例,现有标准厚度顶层金属和钝化的工艺模块如下步骤,
步骤1,顶层金属的淀积,
顶层金属淀积采用物理气相淀积(英文名称为Physical Vapor Deposition,简写为PVD)方式淀积,金属淀积前进行射频溅射以去除表面的氧化层和沾污;顶层金属采用Ti/TiN/AlSiCu的三层结构,总厚度在0.9~1.5μm;第一层为Ti粘附层14,作用是使得金属和下层的ILD较好地粘附;第二层为TiN阻挡层15,作用是为了避免接触孔Al/Si界面处Si溶解到Al中形成源漏结穿刺;第三层为AlSiCu金属层16,其中Al、Si和Cu的重量比分别为98~99%、0.5~1.5%和0.1~1.0%,Al中加入Si也是为了防止Si溶解到Al中形成源漏结穿刺,Al中加入Cu是为了提高金属的电迁移能力;对于尺寸较大的工艺如3μm CMOS工艺,Ti和TiN层可以省略;另外,为了减少金属表面的光反射以利于金属光刻工艺,0.8μm以下的小尺寸CMOS工艺需要在AlSiCu表面再生长Ti/TiN或TiN的抗反射层;
步骤2,顶层金属的光刻,
如图2所示,光刻步骤包括涂胶、曝光和显影,通过光刻定义出金属图形,第一层光刻胶17包括焊盘第一层光刻胶17a和内部电路第一层光刻胶17b,作为掩蔽阻挡,第一层光刻胶17要保证足够的厚度,否则会出现金属削顶甚至刻蚀的现象;
步骤3,顶层金属的刻蚀;
如图3所示,对顶层金属进行刻蚀,刻蚀工艺分为干法和湿法两种工艺,湿法工艺的选择比较高,但侧向尺寸损失较大;对于0.13~3μm CMOS工艺,由于金属的线宽较小,且采用Ti/TiN/AlSiCu的三层结构,需要采用干法刻蚀工艺刻蚀,刻蚀完成后形成焊盘顶层金属:焊盘Ti粘附层14a/焊盘TiN阻挡层15a/焊盘AlSiCu金属层16a和内部电路处顶层金属布线:内部电路Ti粘附层14b/内部电路TiN阻挡层15b/内部电路AlSiCu金属层16b;
步骤4,顶层金属刻蚀的去胶,
如图4所示,通过体积比为5:1的H2SO4:H2O2清洗去除刻蚀后的第一层光刻胶17,清洗要保证不出现金属的后腐蚀现象;
步骤5,钝化层18淀积,
如图5所示,钝化层18采用Si3N4的单一膜质,也可以采用SiO2/Si3N4的复合膜,通过SiO2缓冲Si3N4的应力;由于AlSiCu熔点较低,金属淀积后的工艺不允许高于450℃的工艺温度,因此采用400℃左右的等离子气相淀积(英文名称为Plasma Enhanced Chemical VaporDeposition,简写为PECVD)形成SiO2和Si3N4;PECVD形成的Si3N4具有优异的防潮、防杂质扩散和防擦伤特性;
步骤6,钝化的光刻,
如图6所示,光刻步骤包括涂胶、曝光和显影,通过第二层光刻胶19定义出焊盘上钝化的开孔;钝化开孔的大小和键合工艺相关,对于0.13~3μm CMOS工艺,钝化开孔尺寸为40~120μm,只在焊盘金属上进行钝化开孔;
步骤7,钝化的刻蚀,
如图7所示,钝化层18的刻蚀一般采用干法刻蚀,如果顶层金属有抗反射层也要通过刻蚀去除;为了保证刻蚀干净,钝化刻蚀通常有过刻蚀,即对AlSiCu有一定的刻蚀损失,刻蚀终点最终停留在顶层金属中AlSiCu的上表面;
步骤8,钝化刻蚀的去胶,
如图8a所示,通过体积比为5:1的H2SO4:H2O2清洗去除钝化刻蚀后的第二层光刻胶19,清洗也要保证不出现金属的后腐蚀现象,至此,现有标准厚度顶层金属和钝化的工艺模块完成,对于0.13~3μm CMOS工艺,焊盘下和焊盘周围10~15μm范围内不允许CMOS器件有源区和多晶栅12的存在;
上述工艺改为焊盘下器件的双顶层金属CMOS工艺后,允许DUP,钝化刻蚀去胶后的示意图如图8b所示,焊盘下和焊盘周围允许CMOS器件有源区和多晶栅12的排布,对电路版图的排布没有任何限制。
在CMOS工艺的顶层金属和钝化工艺模块完成后的晶圆上开始提高焊盘金属厚度的双顶层金属工艺,具体步骤包括如下步骤,
步骤9,焊盘厚铝20的淀积,
如图9所示,由于焊盘厚铝20和顶层金属中AlSiCu接触,因此不需要淀积Ti粘附层和TiN阻挡层;焊盘厚铝20的淀积前进行射频溅射以去除表面的氧化层和沾污;焊盘厚铝20采用的材质为AlSiCu,成分比和顶层金属中的AlSiCu相同以简化工艺;焊盘厚铝20的厚度可以选择为2~2.5μm,这样确保焊盘上的等效叠加金属厚度达到3~3.5μm;之后的封装测试数据表明,焊盘处3~3.5μm的金属加上的ILD可以充分缓解键合应力;因为图形尺寸很大,焊盘厚铝20的表面不需要淀积抗反射层;
步骤10,焊盘厚铝20的光刻,
如图10所示,只在焊盘厚铝处保留第三层光刻胶21作为刻蚀掩蔽,光刻步骤包括涂胶、曝光和显影,通过光刻定义出焊盘厚铝;焊盘厚铝20的光刻图层为运算层(英文名称为Generation Layer);可以规定钝化图层的反版放大一定尺寸,比如单边放大5μm,通过简单运算生成焊盘厚铝图层,不需要进行专门的设计;
步骤11,焊盘厚铝20的刻蚀,
如图11所示,因为铝的厚度较厚,且焊盘铝的尺寸较大,焊盘厚铝20的刻蚀采用湿法工艺,湿法工艺的等离子损伤较小,并且对铝下钝化层的过刻蚀损失也较小,横向尺寸损失也可忽略不计;
步骤12,焊盘厚铝20刻蚀的去胶,
如图12所示,通过体积比为5:1的H2SO4:H2O2清洗去除刻蚀后的第三层光刻胶21,得到了焊盘金属加厚的双顶层金属,包括焊盘Ti粘附层14a/焊盘TiN阻挡层15a/焊盘AlSiCu金属层16a/焊盘厚铝20。
以下用两个实施例作为示例予以说明。
实施例1,3μm硅栅CMOS双顶层金属工艺制程
修改设计规则,允许DUP。设计时将电路CMOS器件的有源区和多晶的图形放置于金属1焊盘下,实现DUP,并按照以下步骤流片。
步骤1,形成有源区,
使用电阻率为1Ohm·cm、晶向为(100)的N型掺杂晶圆作为硅衬底,该电阻率对应的掺杂浓度较大,首先在该晶圆表面依次生长厚度为的垫氧和的氮化硅,然后,通过光刻和刻蚀氮化硅定义出场区,氮化硅被刻蚀掉的区域将来形成场区,有氮化硅覆盖的区域为有源区,有源区分为NMOS的有源区和PMOS的有源区;
步骤2,形成P阱,
通过光刻和注入,在NMOS的有源区形成P阱,P阱注入为元素为B、能量为120keV、剂量为1.4×1013原子/cm2的阱注入,N阱借用该晶圆本身的浓N型衬底,无需注入;需要说明的是,若步骤1中的晶圆为P型掺杂时,需要进行N阱注入,不需要P阱注入;
步骤3,场区形成和阈值注入,
通过1150℃的高温氧化和推阱,在P阱注入的晶圆表面上无氮化硅覆盖的区域形成厚度为的场氧化层,然后,通过湿法工艺将有源区表面氮化硅剥离;最后对所得的晶圆整个表面进行元素为B、能量为55keV、剂量为4.0×1011原子/cm2的阈值注入;
步骤4,形成栅氧层和多晶栅,
首先,以1000℃下通氧气的干法氧化方式在NMOS的有源区和PMOS的有源区形成厚度为的SiO2栅氧层,然后,在栅氧层表面上淀积厚度为的多晶硅并使用液态磷源POCl3进行950℃多晶硅掺杂,最后,通过多晶栅光刻和刻蚀形成多晶栅;
步骤5,源漏注入,
通过光刻和注入,对已形成P阱的NMOS有源区进行N+源漏注入,注入元素为P,注入能量为90keV,注入剂量为3×1015原子/cm2;
通过光刻和注入,对PMOS有源区进行P+源漏注入,注入元素为B,注入能量为40keV,注入剂量为2×1015原子/cm2;
步骤6,形成孔层,
首先,在源漏注入的晶圆表面上淀积厚度为的氧化硅作为ILD,并进行900℃和60min的致密,然后,通过孔1的光刻和刻蚀在整个有源区和多晶栅上形成大孔,之后,在所得的整个晶圆表面补长厚度为的氧化硅,最后,通过孔2的光刻和刻蚀在大孔内形成接触孔;
步骤7,金属化和钝化,
首先,在接触孔刻蚀的晶圆表面厚度为材料为Ti/TiN/AlSiCu的金属1的淀积、光刻和刻蚀,形成内部电路处金属1布线和焊盘处金属1焊盘,其中金属1焊盘下排布有CMOS器件的有源区和多晶的图形,然后,进行厚度为材料为氧化硅/氮化硅的钝化层的淀积、光刻和刻蚀;
步骤8,焊盘厚铝工艺,
首先,在钝化刻蚀的晶圆表面溅射形成AlSiCu金属层,然后,厚铝光刻,只在焊盘厚铝处保留光刻胶作为刻蚀掩蔽,通过光刻定义出焊盘厚铝,之后是采用湿法工艺对焊盘厚铝的刻蚀,最后,在400℃体积比为10:1的N2:H2气氛中进行40min的合金,测试出片,得到了焊盘处金属厚度加厚的电路。
实施例2,0.5μm硅栅CMOS双顶层金属工艺制程
修改设计规则,允许DUP。设计时将电路完整的CMOS器件,包括有源区、多晶、孔和金属1的图形,放置于金属2焊盘下,实现DUP,并按照以下步骤流片。
步骤1,形成有源区,
使用电阻率为20Ohm·cm、晶向为(100)的P型掺杂晶圆作为硅衬底,首先在该晶圆表面依次生长厚度为的垫氧和的氮化硅,然后,通过光刻和刻蚀氮化硅定义出场区,氮化硅被刻蚀掉的区域将来形成场区,有氮化硅覆盖的区域为有源区,有源区分为NMOS的有源区和PMOS的有源区;
步骤2,形成N阱和P阱,
通过光刻和注入,在NMOS的有源区形成P阱,P阱注入为元素为B、能量为100keV、剂量为8.5×1012原子/cm2;
通过光刻和注入,在PMOS的有源区形成N阱,N阱注入元素为P、能量为180keV、剂量为1.2×1013原子/cm2;
步骤3,场区形成和阈值注入,
通过1150℃的高温氧化和推阱,在双阱注入的晶圆表面上无氮化硅覆盖的区域形成厚度为的场氧化层,然后,通过湿法工艺将有源区表面氮化硅剥离;最后对整片晶圆进行元素为B、能量为11keV、剂量为3.0×1012原子/cm2的阈值注入;
步骤4,形成栅氧和多晶栅,
首先,以850℃下通氧气的干法氧化方式在NMOS的有源区和PMOS的有源区形成厚度为的SiO2栅氧层,然后,在栅氧表面上淀积厚度为的多晶硅并进行多晶硅注入掺杂,注入元素为P,注入能量为30keV,注入剂量为5×1015原子/cm2,最后,通过多晶栅光刻和刻蚀形成多晶栅;
步骤5,N型轻掺杂源漏注入,
通过光刻和注入,对已形成P阱的NMOS有源区进行N型轻掺杂源漏注入,注入元素为P,注入能量为100keV,注入剂量为1.8×1013原子/cm2,P型轻掺杂源漏通过P+源漏横向扩散获得,因此PMOS有源区不需要轻掺杂源漏注入;
步骤6,形成侧墙,
步骤7,源漏注入,
通过光刻和注入,对已轻掺杂源漏注入的NMOS有源区进行N+源漏注入,注入元素为As,注入能量为80keV,注入剂量为2×1015原子/cm2;
通过光刻和注入,对已形成N阱的PMOS有源区进行P+源漏注入,注入元素为B,注入能量为11keV,注入剂量为2.3×1015原子/cm2;
步骤8,形成孔层,
首先,在源漏注入的晶圆表面上淀积厚度为的氧化硅作为ILD,然后,采用CMP的方式平坦化磨掉厚度为氧化硅并补长厚度为的氧化硅,最后,通过孔的光刻和刻蚀在NMOS的有源区、PMOS的有源区和多晶栅上形成接触孔;
步骤9,金属化和钝化,
首先,依次进行孔刻蚀的晶圆表面上厚度为的W的淀积、W的CMP平坦化和厚度为材料为Ti/TiN/AlSiCu/TiN的金属1的淀积、光刻和刻蚀,然后是厚度为的氧化硅金属间介质层1(英文名称为Intermetal Dielectrics,简写为IMD)的淀积,之后CMP平坦化磨掉厚度为氧化硅并补长厚度为的氧化硅,接下来是厚度为材料为Ti/TiN/AlSiCu/TiN的金属2的淀积、光刻和刻蚀,形成内部电路处金属2布线和焊盘处金属2,其中金属2焊盘下排布有完整的CMOS器件的图形,包括有源区、多晶、孔和金属1布线,最后进行厚度为材料为氧化硅/氮化硅的钝化层的淀积、光刻和刻蚀;
步骤10,焊盘厚铝工艺,
首先,在钝化刻蚀的晶圆表面溅射形成AlSiCu金属层,然后,厚铝光刻,只在焊盘厚铝处保留光刻胶作为刻蚀掩蔽,通过光刻定义出焊盘厚铝,之后是采用湿法工艺对焊盘厚铝的刻蚀,最后是400℃体积比为10:1的N2:H2气氛中进行40min的合金,测试出片,得到了焊盘处金属厚度加厚的电路。
最后,本发明按照实施例2的设计方法设计了版图,将电路的CMOS器件放置于焊盘下,按照实施例2的工艺方法采用双顶层金属0.5μm CMOS工艺进行流片。图13a为焊盘厚铝湿法刻蚀后扫描电子显微镜形貌。图13b是图13a的放大图。由于焊盘Ti粘附层14a和焊盘TiN阻挡层15a较薄,图中没有标注。厚度1为焊盘AlSiCu金属层16a的厚度,厚度2为钝化层18的厚度,厚度3为厚铝20的厚度,厚度4为焊盘AlSiCu金属实际厚度。溅射的AlSiCu金属总厚度为厚度1和厚度3的和,为3.4μm,因为钝化刻蚀对AlSiCu金属层有过刻蚀,焊盘AlSiCu金属实际厚度4为3.2μm。由图可见,焊盘形貌良好,对钝化层的过刻蚀量也较小。
将流片后加工完成的晶圆划片,采用标准60μm硅铝丝键合,封装后对DUP器件参数进行测试。图14a、图14b、图14c和图14d分别为NMOS和PMOS的电学参数的相关测试结果。图14a和图14b为阈值测试结果,阈值测试采用跨导法,从图中可见,DUP器件和标准CMOS器件的阈值相当;图14c和图14d为漏电测试结果,测试时漏源电压为VDD,从图中可见,DUP器件和标准CMOS器件漏电都在1×10-11A的同一水平,键合应力对DUP器件的参数没有影响。
Claims (8)
1.一种焊盘下器件的双顶层金属CMOS工艺,其特征在于,包括如下步骤,
步骤1,在硅衬底上依次生长垫氧和氮化硅,通过光刻和刻蚀在无氮化硅的区域形成场区,在有氮化硅覆盖的区域形成有源区,有源区分为NMOS的有源区和PMOS的有源区;
在NMOS的有源区上形成P阱,在PMOS的有源区上形成N阱;
步骤2,在步骤1得到的硅衬底无氮化硅覆盖的区域上通过氧化和推阱形成场氧化层,然后将有源区表面的氮化硅剥离,最后在所得的硅衬底上进行阈值注入;
步骤3,在步骤2得到的硅衬底的有源区上形成栅氧层,之后在栅氧层的表面上形成多晶栅;
步骤4,步骤3得到的硅衬底中,对于0.13~0.8μm硅栅CMOS工艺,先在形成P阱的NMOS有源区进行N型轻掺杂源漏注入,并在形成N阱的PMOS有源区进行P型轻掺杂源漏注入,之后在所得的硅衬底表面形成侧墙,最后按硅栅CMOS工艺依次进行源漏注入、形成孔层、金属化和钝化,得到钝化刻蚀的硅衬底;
对于大于0.8μm且小于3μm硅栅CMOS工艺,先在形成P阱的NMOS有源区进行N+源漏注入,并在形成N阱的PMOS有源区进行P+源漏注入,最后按硅栅CMOS工艺,在轻掺杂源漏注入的硅衬底上先形成孔层,之后进行金属化和钝化,得到钝化刻蚀的硅衬底;
步骤5,在钝化刻蚀的硅衬底表面溅射形成厚铝,然后进行厚铝光刻,定义出焊盘厚铝,之后对焊盘厚铝进行刻蚀,最后对焊盘厚铝刻蚀的硅衬底进行合金操作,得到焊盘处金属厚度加厚的电路。
2.根据权利要求1所述的一种焊盘下器件的双顶层金属CMOS工艺,其特征在于,步骤5中,所述的厚铝为AlSiCu金属层。
4.根据权利要求1所述的一种焊盘下器件的双顶层金属CMOS工艺,其特征在于,步骤5中,在350~450℃下对焊盘厚铝刻蚀的硅衬底进行合金操作。
5.根据权利要求1所述的一种焊盘下器件的双顶层金属CMOS工艺,其特征在于,步骤5中,焊盘厚铝刻蚀的硅衬底合金的时间为30~60min。
6.根据权利要求1所述的一种焊盘下器件的双顶层金属CMOS工艺,其特征在于,步骤5中,焊盘厚铝刻蚀的硅衬底在体积比为(3~10):1的N2:H2气氛中进行合金。
7.根据权利要求1所述的一种焊盘下器件的双顶层金属CMOS工艺,其特征在于,步骤1中,所述的硅衬底为电阻率为1~20Ohm·cm、晶向为(100)的硅晶圆。
8.根据权利要求1所述的一种焊盘下器件的双顶层金属CMOS工艺,其特征在于,步骤5中,采用湿法工艺对焊盘厚铝进行刻蚀。
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