CN102074564A - 用于cmos图像传感器的结合处理 - Google Patents

用于cmos图像传感器的结合处理 Download PDF

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CN102074564A
CN102074564A CN2010102834419A CN201010283441A CN102074564A CN 102074564 A CN102074564 A CN 102074564A CN 2010102834419 A CN2010102834419 A CN 2010102834419A CN 201010283441 A CN201010283441 A CN 201010283441A CN 102074564 A CN102074564 A CN 102074564A
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twv
front side
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CN102074564B (zh
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刘人诚
杨敦年
郭正铮
陈承先
伍寿国
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种用于CMOS图像传感器的结合处理。本发明还提供了一种制造集成电路(IC)的方法。该方法包括:在衬底的前侧上形成电器件;在衬底的前侧上形成顶部金属焊盘,该顶部金属焊盘连接至电器件;在衬底的前侧上形成钝化层,顶部金属焊盘被嵌入钝化层中;在钝化层中形成开口,使顶部金属焊盘暴露;在衬底中形成深沟槽;将导电材料填充在深沟槽和开口中,得到深沟槽中的晶圆通孔(TWV)部件和开口中的焊盘-TWV部件,其中,顶部金属焊盘通过焊盘-TWV部件连接至TWV部件;以及进行抛光处理以去除多余的导电材料,形成基本平坦的表面。

Description

用于CMOS图像传感器的结合处理
交叉参考
本申请是2008年9月8日提交的序列号为No.12/206,349的美国部分继续申请,其全部内容结合于此作为参考。当前公开涉及以下共同指定的US专利申请,其全部内容结合于此作为参考:由发明人Chen-Cheng Kuo等人于2008年5月14日提交的名为“Structure and Process for the Formationof TSVs”的美国序列第12/152,381号;以及由发明人Kuo-Ching Hsu等人于2008年9月8日提交的名为“INTRODUCING A METAL LAYERBETWEEN SIN AND TIN TO IMPROVE CBD CONTACT RESISTANCEFOR P-TSB”的美国序列第No.12/206,349号。
技术领域
本发明涉及一种集成电路,更具体地说,涉及一种用于CMOS图像传感器的结合处理。
背景技术
存在多种类型的半导体集成电路器件,其中,外部连接(例如,接合焊盘)被放置在器件的“后侧”上,即,在半导体衬底的与具有最多金属化层的一侧相对的一侧上。
图1a提供包括CMOS图像传感器的两个芯片尺寸封装(CSP)器件10、12的侧截面图。图1a示出了经由适当连接件连接至载体衬底14(诸如,晶圆载具)的两个器件10、12。器件10、12进一步包括分别在器件的后侧上的接合焊盘20、22以及对应的焊锡块24、26。金属互连件30、32分别将接合焊盘20、22连接至器件10、12的前侧。
图1b提供了两个CSP器件10、12以及它们之间的划线区域40的顶视图。每个器件10、12实际上包括多个接合焊盘,分别包括一行焊盘42、44和延伸焊盘46、48。划线区域40包括划线50和一对密封环52、54。
上述器件存在多个问题。一个问题在于,焊盘数量必须是双数,这是由于延伸焊盘,其要求额外空间和放大的芯片尺寸。另一个问题在于,外部电介质膜开裂和受潮。金属互连件还存在可靠性问题。
图1c和图1d进一步提供了更详细的CSP器件10的截面图。互连件64和钝化层66形成在衬底62上。金属焊盘68形成在布线64上。然后,诸如干膜的电介质膜70形成在钝化层上并且被进一步图案化。金属结构72形成在图案化电介质膜的开口中。金属结构72包括与金属焊盘68接触的金属柱74以及硅通孔(TSV)金属柱76。然后,去除图案化的电介质膜70,留下从钝化层66伸出的金属结构72,如图1d所示。金属结构72的顶面和钝化层66的顶面具有阶梯高度,导致封装问题和所涉及的器件性能相关问题。
发明内容
本公开在特定实施例中提供了一种制造集成电路(IC)的方法。该方法包括:在衬底的前侧上形成电器件;在衬底的前侧上形成顶部金属焊盘,该顶部金属焊盘连接至电器件;在衬底的前侧上形成钝化层,该顶部金属焊盘被嵌入钝化层中;在钝化层中形成开口,使顶部金属焊盘暴露;在衬底中形成深沟槽;将导电材料填充到深沟槽和开口中,得到深沟槽中的晶圆通孔(TWV)部件和开口中的焊盘-TWV部件,其中,顶部金属焊盘通过焊盘-TWV部件连接至TWV部件;以及进行抛光处理以去除多余的导电材料,形成基本平坦的表面。
本公开在另一个实施例中还提供了一种形成集成电路的方法。该方法包括:在硅衬底的前表面中形成半导体器件;在半导体器件上从硅衬底的前侧形成多层布线(MLI);在MLI上形成金属焊盘,该金属焊盘与半导体器件连接;在金属焊盘和硅衬底上形成电介质层,该金属焊盘被嵌入电介质层中;蚀刻电介质层以在电介质层中形成沟槽,使沟槽中的金属焊盘暴露;执行电介质蚀刻以在MLI中形成通孔;执行硅蚀刻,以使通孔继续通过硅衬底,以形成硅通孔(TSV);对TSV和沟槽执行铜金属化;以及之后进行化学机械抛光(CMP)处理。
根据多种实施例,本公开还提供了一种集成电路。该集成电路包括:电器件,形成在衬底的前侧上;钝化层,形成在衬底的前侧上;金属焊盘,被嵌入钝化层中并且与电器件连接;晶圆通孔(TWV)特征,形成在衬底中并且延伸至衬底的后侧;以及焊盘-TWV金属部件,被嵌入钝化层中并且接触金属焊盘和TWV部件,其中,焊盘-TWV和钝化层具有公共顶面。
附图说明
当阅读附图时,从以下详细描述可以最好地明白本公开的各个方面。需要强调的是,根据工业中的标准惯例,多种特征不按比例绘制。实际上,为了描述清楚,多种特征的尺寸可以任意增加或减小。
图1a是两个芯片尺寸封装(CSP)器件的侧截面图。
图1b是两个CSP器件的顶视图。图1a是两个现有技术的传感器器件的侧截面图以及图1b是与图1a对准的两个现有技术的传感器器件的顶视图。
图1c和图1d是CSP器件的截面图;
图2至图15是根据本发明的一个或多个实施例构建的在多个处理阶段期间的集成电路(IC)器件的多个截面图。
具体实施方式
应该明白,以下公开提供了多个不同实施例或例子,用于实现多种实施例的不同特征。以下描述组件和布置的特定实例,以简化当前公开。当然,这些仅是实例,而并不用于限制本公开。另外,本公开可以在多个实例中重复使用参考标号和/或字母。该重复用于简化和清楚的目的,而其本身不指定多种实施例和/或上述布置之间的关系。
为了举例,将示出示例性器件经过一系列处理操作,以示出本发明的多种实施例。应该明白,多个处理步骤可以仅简单地描述,这样的步骤对于本领域技术人员来说是已知的。而且,可以增加附加处理步骤,并且可以去除和/或改变以下处理步骤中的特定步骤,同时仍然实现所要求的发明。这样,以下描述应该被理解为仅表示实例,而不用于表明所要求的一个或多个步骤。
图2至图15是根据本公开的各个方面构建的在不同制造阶段期间的集成电路器件的截面图。参考图2至图15,共同描述集成电路100及其制造方法。
参考图2,器件100包括衬底102,根据本实施例,该衬底为硅衬底。在一个实例中,硅衬底为8’硅晶圆或12’硅晶圆。衬底102可以可选地或另外地包括其他单体半导体,诸如锗。衬底102还可以包括化合物半导体,诸如碳化硅、砷化镓、砷化铟、以及磷化铟。
在一个实施例中,半导体衬底102包括外延层,例如,衬底可以具有叠加在体半导体上的外延层。在本实施例中,P+硅外延层形成在硅衬底上并且P-硅外延层形成在P+硅外延层上。而且,衬底可以被变形用于性能提高。对于另一个实例,外延层可以包括不同于体半导体的半导体材料,诸如叠加在体硅之上的锗化硅层,或叠加在通过包括选择性外延生长(SEG)的处理形成的体锗化硅上的硅层。而且,衬底102可以包括绝缘体上半导体(SOI)结构。在各种实例中,衬底包括埋氧层(BOX),其通过诸如氧植入隔离(separation by implanted oxygen,SIMOX)的处理来形成。衬底102包括多种掺杂阱和其他掺杂特征,其被配置和连接以形成多种微电子器件,诸如包括互补MOSFET(CMOS)和CMOS成像传感器(CIS)的金属绝缘体半导体场效应晶体管(MOSFET)。另外地或可选地,衬底102包括微型电子机械系统(MEMS)、和/或其他合适的有源和/或无源器件。掺杂阱和其他掺杂特征包括p型掺杂区域和/或n型掺杂区域,通过诸如离子注入的掺杂处理来形成。诸如栅极电介质和多晶硅栅电极的其他结构可以另外形成在衬底上,用于诸如MOSFET器件的器件。衬底102还包括被配置成使多种器件相互分离的多种隔离特征,用于适当隔离。隔离特征可以包括不同结构并且可以通过特定处理技术形成。在一个实例中,隔离特征包括电介质隔离,诸如浅沟槽隔离(STI)。可以通过蚀刻衬底以形成沟槽并且用一个或多个电介质材料层填充沟槽来制造STI。
一个或多个金属层(或互连件)和隔离电介质(共同被称为金属化层104)形成在衬底102之上。在金属化层104上形成顶部金属焊盘104a(举例示出)。在金属化层104和顶部金属焊盘106上进一步形成电介质层108。在本发明实施例中,顶部金属焊盘106包括铜、铝、钨或其他合适的导电材料。
互连件被配置成适当地连接衬底中的多个掺杂区域。在本实施例中,互连件包括多层互连件(MLI),其具有设置在多个金属层处的水平导电部件(金属线)和垂直导电部件,诸如接点和通孔。通孔被配置成连接在不同金属层处的两条金属线。接点被配置成连接金属线和衬底。多层互连件包括铜。铜互连件可以包括铜、铜合金、钛、氮化钛、钽、氮化钽、钨、多晶硅、金属硅化物、或其结合。铜互连件可以通过诸如CVD、溅射、电镀、或其他合适的处理等技术来形成。在多层互连件中使用的金属硅化物可以包括硅化镍、硅化钴、硅化钨、硅化钽、硅化钛、硅化铂、硅化铒、硅化钯或其结合。可选地,多层互连件可以包括铝互连件中的铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅化物、或其结合。铝互连件可以通过包括物理气相沉积(PVD或溅射)、化学气相沉积(CVD)、或其结合的处理来形成。形成铝互连件的其他制造技术可以包括光刻处理和蚀刻,以图案化用于垂直(通孔和接点)和水平连接(导电线)的导电材料。还可以使用诸如热退火的其他制造工艺来形成金属硅化物,以减少接点阻抗(或接触电阻)。
隔离电介质被设置在互连件结构中,以隔离多个导电部件。隔离电介质包括位于衬底和第一金属层之间的层间电介质(ILD)。隔离电介质还包括位于相邻金属层之间的金属间电介质(IMD)。隔离电介质包括诸如氧化硅、氮化硅、氮氧化硅、或旋涂玻璃(SOG)等电介质材料。电介质材料可选地包括诸如电介质常量小于约3.2的低电介质常量(低k)的材料。在多种实例中,电介质材料可以包括二氧化硅、氮化硅、氮氧化硅、旋涂玻璃(SOG)、掺氟硅酸盐玻璃(FSG)、掺碳氧化硅、黑钻
Figure BSA00000272371000051
(加利福尼亚的圣克拉拉(Santa Clara)的应用材料)、干凝胶、气凝胶、氟化非晶碳、聚对二甲苯、BCB(bisbenzocyclobutenes,苯并环丁烯)、SiLK(密歇根州中部地区的陶氏化学公司)、聚酰亚胺、和/或其他合适的材料。隔离电介质通过包括旋转涂布、CVD、或其他合适的工艺来形成。
在一个实施例中,电介质层108包括钝化层。在一个实例中,钝化层包括氧化硅。氧化硅钝化层可以具有范围在约100nm和约2000nm之间的厚度。在另一实例中,氧化硅层通过离子增强CVD(PECVD)工艺来形成。可选地,钝化层包括在金属化层104上形成的第一钝化膜、以及在第一钝化膜上形成的第二钝化膜。在一个实例中,第一钝化膜包括氧化硅。在另一实例中,第二钝化膜包括氮化硅和/或氮氧化硅。第二钝化层可以具有范围在约2K埃和约15K埃之间的厚度。在一个实例中,氮化硅钝化层通过离子增强CVD(PECVD)工艺来形成。
钝化层108被进一步图案化,以形成开口110,通过蚀刻过程使顶部金属焊盘106暴露。在一个实例中,通过光刻处理在钝化层108上形成光刻胶图案,然后进行一个或多个蚀刻步骤,以在钝化层中形成开口110。然后,通过诸如剥离或灰化等工艺去除光刻胶图案。
参考图3,通过包括光刻图案化和蚀刻的处理,在钝化层108和金属化层104中形成沟槽112。在一个实施例中,通过光刻工艺在钝化层108上形成光刻胶图案,在光刻胶图案中限定开口。然后,执行一个或多个蚀刻步骤,以在钝化层108和金属化层104中形成沟槽112。然后,通过诸如剥离或灰化等工艺去除光刻胶图案。在另一实施例中,通过光刻工艺在钝化层108上形成光刻胶图案。然后,执行一个或多个蚀刻步骤,以在钝化层中形成沟槽112。然后,去除光刻胶图案。通过使用适当的蚀刻化学药品的蚀刻工艺将沟槽112进一步延伸至金属化层。在多种实施例中,在金属化层和钝化层上进行金属/氧化蚀刻(例如,干蚀刻),以形成下至衬底102的沟槽112的第一部分。例如,进行利用蚀刻剂CF4、C3F8、C4F8、CHF3、和/或CH2F2的干蚀刻工艺,以蚀刻氧化硅。
参考图4,执行硅蚀刻,以使沟槽112继续到衬底102。对于一个实例,执行利用蚀刻剂HBr、Cl2、SF6、和/或O2的干蚀刻工艺蚀刻硅衬底,以形成沟槽112。从而,所形成的深沟槽112还可以被称为硅通孔(TSV)或一般晶圆通孔(TWV),以包括其他非硅衬底。
在图5中,隔离层120被设置在器件100之上,包括沟槽110。在一个实施例中,在开口110中,以及在沟槽112中,特别是在其侧壁上,隔离层120被形成为与钝化层108上的器件是共形的。在一个实施例中,隔离层120包括扩散阻挡层。在一个实施例中,隔离层包括氮和/或TEOS。在另一实施例中,层120可以可选地使用有效用于扩散阻挡层的其他材料,诸如氮化钽或氮化钛。
在图6中,随后去除隔离层120的多个部分,使得沟槽112的底部和顶部金属焊盘116通过合适的蚀刻工艺暴露。例如,可以进行干蚀刻工艺去除隔离层的多个部分,用于形成具有到顶部金属焊盘的连接件的硅通孔金属结构。应该明白,可以通过本领域中已知的多种技术来实现。
参考图7,然后在器件100的表面之上沉积铜晶种层122。特别地,在顶部金属焊盘106上和沟槽112的底部/侧壁上形成铜晶种层。在本实施例中,铜晶种层122在约1000至约10000
Figure BSA00000272371000072
之间。在一个实施例中,通过物理汽相沉积(PVD或溅射)来执行。
在图8中,在铜晶种层122上形成块体铜(bulk copper)124。在一个实施例中,通过电镀处理形成块体铜层124。在本实施例中,块体铜124填充器件100的整个上表面,特别是填充在沟槽112(或TSV)、以及开口110中。沟槽112中填充的块体铜被称为TSV(或TWV)部件,填充在开口110中的块体铜被称为焊盘-TWV部件。焊盘-TWV部件连接至金属焊盘106和TWV部件。TWV部件可以具有范围在约10微米和约600微米之间的长度。在另一实施例中,TWV部件在俯视图中具有范围在约5微米和约100微米之间的尺寸。
在图9中,抛光处理被应用至器件100以去除多余的铜,包括在钝化层的顶面之上的块体铜和铜层。在本实施例中,抛光处理是化学机械抛光(CMP)。从而,焊盘-TWV部件的顶面与电介质层108的顶面基本上共面。消除或基本减少了焊盘-TWV部件和电介质层108之间的阶梯高度。例如,焊盘-TWV部件和电介质层108之间的阶梯高度小于约5微米。
在图10中,在器件的顶面上、铜层124之上、以及钝化层108之上沉积保护层126。请注意,在本实施例中,由于焊盘-TWV部件和电介质层108是共面的,从而不存在保护层126中的阶梯高度问题。保护层对于成像光是透明的,使得来自物体的光能够通过透明的保护层照明,以达到图像传感器。在一个实施例中,保护层是氮化硅(SiN)并且可以通过CVD工艺(诸如,PECVD)形成。在实施例的深化中,形成SiN层的CVD工艺包括前体六氯乙硅烷(Si2Cl6)、二氯硅烷(SiH2Cl2)、双(叔丁基氨基)硅烷(Bis(TertiaryButyAmino)Silane)(C8H22N2Si)以及乙硅烷(Si2H6)。在一个实施例中,保护层126用作钝化层。保护层126具有范围在约100nm和约20000nm之间的厚度。
通过以上描述的方法,TSV部件被形成并通过钝化层108中的焊盘-TWV部件连接至顶部金属焊盘106。消除或减少了阶梯高度问题,并且减小了整体厚度。
现在参考图11,示出了在同一衬底102上的两个典型器件。在本实施例中,两个器件是类似的,并且一个器件100使用在图2至图10中使用的参考标号。虽然利用200标记,其他器件使用类似参考标号,其中,器件和/或层是不同的。应该明白,每个典型器件可以包括多个CMOS图像传感器和其他合适的电气元件。而且,每个器件作为管芯都将通过切割从晶片与其他器件分离。
继续本实施例,器件100、200包括多个微透镜和滤色器130、230。在一个实例中,滤色器包括通过旋转涂布形成的有机材料。在另一实施例中,滤色器包括红、绿、和蓝滤色器。坝(或障碍物)或隔离结构300位于器件100、200的边缘附近,并且外延层302保护到载体衬底(玻璃或晶片)304的坝(以及这样的器件)。坝结构300被插入相邻图像传感器之间用于分离。坝结构300包括电介质材料。在多种实施例中,电介质材料包括氮化硅、氮氧化硅、氧化硅、树脂、聚合物、其结合、和/或其他合适的材料。坝结构可以通过沉积电介质材料层并且然后使用光刻图案化处理来形成。电介质层可以通过CVD、PVD、ALD、旋转涂布、和/或其他合适的方法来形成。在一个实例中,电介质层可以具有包括平坦化层、和/或分隔层的多层结构。电介质层可以通过以上描述的方法形成,并且可以基本上是平坦的,可能是化学机械抛光(CMP)的结果。在一个实施例中,坝结构300具有范围在约0.2μm和50μm之间的厚度。透镜和滤色器可以被定位成使得入射光直接射到其上并且从其通过。在一个实施例中,这样的透色层可以包括聚合材料(例如,基于丙烯酸类聚合物的负性光刻胶)或树脂。
在图12中,然后,衬底102的后侧被向下接地,使得沟槽112中的铜层124、224形成硅通孔(TSV或晶圆通孔)140、240。而且,形成划线沟槽320,以在组装期间使两个器件100、200分离。划线沟槽320通过从衬底102的后侧施加的蚀刻处理来形成。光刻工艺可以被施加至衬底的后侧,以限定划线区域,并且然后,实现蚀刻工艺来蚀刻划线区域,以形成划线沟槽。
在图13中,隔离材料层306被沉积在器件100、200的后侧上,并且进一步被图案化以使TSV 140、240暴露。隔离材料层还形成在划线沟槽的侧壁中。然后,下面的CSM(涂布阻焊模)焊盘150、250被附着到衬底102的后侧。
在图14中,从焊盘150、250到各自的TSV 140和240提供导线152和252。
在图15中,阻焊层160和对应焊球(或块)162、262形成在器件100、200的后侧上,从而提供通过TSV 140、150到器件的电连接。然后,施加切割处理,以沿切割线分离器件100和200。
本实施例提供了多个益处。通过使用嵌入式工艺来形成连接TSV和顶部金属焊盘的导电部件,晶片厚度被减小并且阶梯高度被消除。嵌入式工艺包括:蚀刻钝化层以形成开口;在开口中填充铜,并且施加CMP处理以去除多余的铜,得到平坦表面。由于诸如更少的接合焊盘和双密封环的消除等多种因素,整个器件尺寸被减小。而且,改善了芯片尺寸封装(CSP)的可靠性(例如,减少了电介质膜开裂),并且提供很好的平面化。
本公开提供了CMOS图像传感器器件及其制造方法。虽然提供了多种实施例,但是在该精神和范围内的其他改变被认为是与本披露一致的,并且可作为参考。例如,成像器件可以可选地或共同地包括光电二极管或针扎光电二极管。在实例的深化中,成像器件的每个像素均包括光电二极管和MOS晶体管;针扎光电二极管和4个晶体管;或非针扎光电二极管和4个晶体管。在另一实例中,对划线沟槽执行切割处理,以将多种器件分成用于进一步封装的独立芯片。
从而,本公开提供了一种制造集成电路(IC)的方法。该方法包括:在衬底的前侧上形成电器件;在衬底的前侧上形成顶部金属焊盘,该顶部金属焊盘连接至电器件;在衬底的前侧形成钝化层,该顶部金属焊盘被嵌入钝化层;在钝化层中形成开口,使顶部金属焊盘暴露;在衬底中形成深沟槽;将导电材料填充在深沟槽和开口中,得到在深沟槽中的晶圆通孔(TWV)部件和开口中的焊盘-TWV部件,其中,顶部金属焊盘通过焊盘-TWV部件连接至TWV部件;以及进行抛光处理,诸如化学机械抛光,以去除多余的导电材料,形成基本平坦的表面。
在一个实施例中,本方法可以包括:在进行抛光处理之后,在衬底的前侧上形成电介质层;从后侧研磨衬底,以使TWV部件暴露;以及从后侧蚀刻划线区域中的衬底,以形成划线沟槽。该方法进一步包括:在划线沟槽的表面上形成电介质材料层;以及在电介质材料层上形成涂布阻焊模(CSM)。该方法可以进一步包括:在衬底的后侧以及CSM上形成外部导线,外部导线连接至TWV部件;以及在CSM上形成焊块,其中外部导线位于CSM和焊块之间。导电材料的填充可以包括:在开口和深沟槽中形成隔离层;对隔离层执行干蚀刻,以去除开口的第一底面和深沟槽的第二底面上的隔离层;使用物理汽相沉积(PVD)在隔离层、第一底面和第二底面上形成铜晶种层;以及通过电镀在铜晶种层上形成块体铜。电器件的形成可以包括:在衬底的前侧上形成互补金属氧化物半导体(CMOS)图像感应元件。该方法可以进一步包括在衬底的前侧上形成多个滤色器和多个透镜。该方法可以进一步包括在衬底的前侧上在划线区域内形成环氧树脂部件。该方法可以进一步包括将衬底从前侧附着到晶圆载具上。该方法可以进一步包括切割划线沟槽中的集成电路。
本公开还提供了在另一实施例中的一种形成集成电路的方法。该方法包括:在硅衬底的前表面中形成半导体器件;在半导体器件上从硅衬底的前侧形成多层互连件(MLI);在MLI上形成金属焊盘,金属焊盘与半导体器件连接;在金属焊盘和硅衬底上形成电介质层,金属焊盘被嵌入电介质层中;蚀刻电介质层以在电介质层中形成沟槽,使沟槽中的金属焊盘暴露;执行电介质蚀刻以在MLI中形成通孔;执行硅蚀刻,以继续使通孔通过硅衬底,形成硅通孔(TSV);在TSV和沟槽上执行铜金属化层;以及之后执行化学机械抛光(CMP)处理。
在本方法中,执行铜金属化可以包括:通过溅射形成铜晶种层;以及通过电镀在铜晶种层上形成块体铜。执行铜金属化可以进一步包括:在形成铜晶种层和形成块体铜之前,在沟槽和TSV中形成隔离层;以及对隔离层执行干蚀刻,以去除沟槽的第一底面和TSV的第二底面上的隔离层。该方法可以进一步包括:在CMP处理之后,形成钝化层;在钝化层上形成滤色器;从后侧研磨硅衬底;以及在集成电路的后侧上提供结合机构,结合机构连接至TSV。提供结合机构可以包括:在衬底的后侧上形成涂布阻焊模(CSM);形成从CSM延伸到TSV的导电部件;以及在导电部件上形成焊球,导电部件位于焊球和CSM之间。该方法可以进一步包括将硅衬底从前表面附着至载体衬底。
本公开还提供了一种集成电路。该集成电路包括:电器件,形成在衬底的前侧上;钝化层,形成在衬底的前侧上;金属焊盘,被嵌入钝化层中并且与电器件连接;晶圆通孔(TWV)部件,形成在衬底中并且延伸至衬底的后侧;以及焊盘-TWV金属部件,被嵌入钝化层中并且与金属焊盘和TWV部件接触,其中,焊盘-TWV和钝化层具有共面的顶面。
在一个实施例中,该集成电路进一步包括在衬底的后侧上与TWV部件电连接的焊球以及从前侧附着于衬底的载体衬底。在另一实施例中,电器件包括选自以下组的成像元件,该组由金属氧化物半导体(CMOS)图像传感器、光电二极管、以及针扎光电二极管构成;以及该集成电路进一步包括位于衬底的前侧并且与成像元件对准的微透镜和滤色器。在另一实施例中,TWV部件包括铜,并且通过嵌入式工艺来形成。
虽然详细地描述了本公开的多个实施例,但是本领域技术人员应该明白,在不脱离本公开的精神和范围的情况下,它们在此可以有多种改变、替换和变化。从而,所有这样的改变、替换和变换均被认为包括在权利要求所限定的本公开的范围内。在权利要求中,功能性限定项被认为覆盖了在此描述的结构,看作执行所述功能并且不仅是结构等价,而且是等效结构。

Claims (15)

1.一种制造集成电路(IC)的方法,包括:
在衬底的前侧上形成电器件;
在所述衬底的所述前侧上形成顶部金属焊盘,所述顶部金属焊盘连接至所述电器件;
在所述衬底的所述前侧上形成钝化层,所述顶部金属焊盘被嵌入所述钝化层中;
在所述钝化层中形成开口,使所述顶部金属焊盘暴露;
在所述衬底中形成深沟槽;
将导电材料填充在所述深沟槽和所述开口中,得到所述深沟槽中的晶圆通孔(TWV)部件和开口中的焊盘-TWV部件,其中,所述顶部金属焊盘通过所述焊盘-TWV部件连接至所述TWV部件;以及
去除多余的导电材料,形成基本平坦的表面。
2.根据权利要求1所述的方法,进一步包括:
在去除所述多余的导电材料之后,在所述衬底的所述前侧上形成介电层;
从后侧研磨所述衬底,以使所述TWV部件暴露;以及
从所述后侧蚀刻划线区域中的所述衬底以形成划线沟槽。
3.根据权利要求1所述的方法,进一步包括:
在所述划线沟槽的表面上形成电介质材料层;
在所述电介质材料层上形成涂布阻焊模(CSM);
在所述衬底的所述后侧和所述CSM上形成外接引线,所述外接引线连接至所述TWV部件;以及
在所述CSM上形成焊块。
4.根据权利要求1所述的方法,其中,所述导电材料的填充包括:
在所述开口和所述深沟槽中形成隔离层;
对所述隔离层执行干蚀刻,以去除所述开口的第一底面和所述深沟槽的第二底面上的隔离层;
使用物理汽相沉积(PVD)在所述隔离层、所述第一底面和所述第二底面上形成铜晶种层;以及
通过电镀在所述铜晶种层上形成块体铜。
5.根据权利要求1所述的方法,其中,所述电器件的所述形成包括:在所述衬底的前侧上形成互补金属氧化物半导体(CMOS)图像感测元件;以及
在所述衬底的所述前侧上形成多个滤色器和多个透镜。
6.根据权利要求1所述的方法,进一步包括:在所述衬底的所述前侧的划线区域中形成环氧树脂部件;
将所述衬底从所述前侧附着到晶圆载具上;以及
切割所述划线沟槽中的所述集成电路。
7.一种形成集成电路的方法,包括:
在硅衬底的前表面中形成半导体器件;
从所述硅衬底的所述前侧在所述半导体器件上形成多层互连层(MLI);
在所述MLI上形成金属焊盘,所述金属焊盘与所述半导体器件连接;
在所述金属焊盘和所述硅衬底上形成电介质层,所述金属焊盘被嵌入所述电介质层;
蚀刻所述电介质层以在所述电介质层中形成沟槽,露出所述沟槽中的所述金属焊盘;
执行电介质蚀刻以在所述MLI中形成通孔;
执行硅蚀刻以继续使所述通孔通过所述硅衬底,以形成硅通孔(TSV);
在所述TSV和所述沟槽上使铜金属化;以及
之后进行化学机械抛光(CMP)处理。
8.根据权利要求7所述的方法,其中,所述使铜金属化包括:
通过溅射形成铜晶种层;以及
通过电镀在所述铜晶种层上形成块体铜。
9.根据权利要求8所述的方法,其中,所述使铜金属化进一步包括:在形成所述铜晶种层和形成所述块体铜之前:
在所述沟槽和所述TSV中形成隔离层;以及
对所述隔离层执行干蚀刻,以去除所述沟槽的第一底面和所述TSV的第二底面上的隔离层。
10.根据权利要求7所述的方法,进一步包括:
在所述CMP处理之后形成钝化层;
在所述钝化层上形成滤色器;
从后侧研磨所述硅衬底;以及
在所述集成电路的后侧设置结合机构,所述结合机构连接至所述TSV,
其中,设置所述结合机构包括:
在所述衬底的所述后侧上形成涂布阻焊模(CSM);
形成从所述CSM延伸到所述TSV的导电部件;以及
在所述导电部件上形成焊球,所述导电部件位于所述焊球和所述CSM之间。
11.根据权利要求7所述的方法,进一步包括:将所述硅衬底从所述前表面附着到载体衬底上。
12.一种集成电路,包括:
电器件,形成在衬底的前侧上;
钝化层,形成在所述衬底的所述前侧上;
金属焊盘,被嵌入所述钝化层中并且与所述电器件连接;
晶圆通孔(TWV)部件,形成在所述衬底中并且延伸至所述衬底的后侧;以及
焊盘-TWV金属部件,被嵌入所述钝化层中并且使所述金属焊盘和所述TWV部件相接触,其中,所述焊盘-TWV和所述钝化层具有共面的顶面。
13.根据权利要求12所述的集成电路,进一步包括:在所述衬底的所述后侧上与所述TWV部件电连接的焊球以及从所述前侧附着到所述衬底上的载体衬底。
14.根据权利要求12所述的集成电路,其中,所述电器件包括选自以下组中的成像元件,所述组包括:互补金属氧化物半导体(CMOS)图像传感器、光电二极管、以及针扎光电二极管;并且所述集成电路进一步包括位于所述衬底的所述前侧上并且与所述成像元件对准的微透镜和滤色镜。
15.根据权利要求12所述的集成电路,其中,所述TWV部件包括铜并且通过嵌入式工艺来形成。
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