CN110648998A - 半导体封装的制造方法 - Google Patents

半导体封装的制造方法 Download PDF

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Publication number
CN110648998A
CN110648998A CN201910256661.3A CN201910256661A CN110648998A CN 110648998 A CN110648998 A CN 110648998A CN 201910256661 A CN201910256661 A CN 201910256661A CN 110648998 A CN110648998 A CN 110648998A
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package substrate
shield
package
shield wall
wall
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CN201910256661.3A
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CN110648998B (zh
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朴永祐
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明提供一种制造半导体封装的方法，该方法包括：将至少一个半导体芯片安装到封装基板；在所述至少一个半导体芯片周围形成屏蔽壁；在由屏蔽壁围绕的空间中在封装基板上形成模制主体；以及形成屏蔽盖，该屏蔽盖覆盖模制单元并与屏蔽壁接触。

Description

半导体封装的制造方法
技术领域
发明构思涉及半导体封装以及制造半导体封装的方法。
背景技术
半导体封装的半导体芯片可能由于电磁干扰(EMI)而异常地操作。在本上下文中的电磁干扰(EMI)指的是这样的现象，其中在封装外部但与该封装相邻的电子器件产生电场，该电场被强加于封装的芯片上并因此改变封装的芯片的操作。已经建立电磁干扰屏蔽以减轻EMI的影响。随着半导体封装之间的距离根据对更小的电子产品的需求而变小，半导体封装中的这样的电磁干扰屏蔽变得越来越重要。已经通过电镀或物理气相沉积(PVD)制造半导体封装的电磁干扰屏蔽结构。
发明内容
根据发明构思的一方面，提供一种制造半导体封装的方法，该方法包括：将至少一个半导体芯片安装到封装基板的上表面；在封装基板之上形成围绕所述至少一个半导体芯片的侧面延伸的屏蔽壁；在由屏蔽壁和封装基板界定的空间中形成模制主体；以及形成覆盖模制主体并接触屏蔽壁的屏蔽盖。
根据发明构思的另一方面，提供一种制造半导体封装的方法，该方法包括：提供封装基板，该封装基板包括具有上表面的基底、在基底的上表面上的阻焊层以及接触基底并延伸到阻焊层中的突起；在基底的上表面顶上将至少一个半导体芯片安装到封装基板；将屏蔽壁附接到封装基板，该屏蔽壁在突起之上并环绕所述至少一个半导体芯片延伸；在由屏蔽壁和封装基板界定的空间中形成模制主体；以及形成覆盖模制主体并与屏蔽壁接触的屏蔽盖。
根据发明构思的另一方面，提供一种制造半导体封装的方法，该方法包括：将半导体芯片安装在封装基板的上表面上成水平阵列，其中该水平阵列的各个芯片在与封装基板的上表面平行的方向上彼此横向地间隔开；在封装基板之上形成围绕每个半导体芯片延伸的屏蔽壁；在由屏蔽壁和封装基板界定的空间中沉积模制材料；固化模制材料从而形成模制主体，该模制主体分别将半导体芯片封装在所述空间内的封装基板上；在该水平阵列的半导体芯片之间的区域中切开屏蔽壁和封装基板；以及形成覆盖每个模制主体的屏蔽盖。
根据发明构思的另一方面，提供一种制造半导体封装的方法，该方法包括：形成封装基板，该封装基板包括电绝缘材料的基底、在该基底的上表面处的导电材料的上焊盘、以及在该基底的上表面上垂直地延伸的导电材料的突起；在半导体封装的位于封装基板之上的芯片安装区域中设置至少一个半导体芯片，并将所述至少一个半导体芯片电连接到封装基板的上焊盘；形成电磁辐射屏蔽壁，该电磁辐射屏蔽壁通过用导电材料的围栏(fence)在半导体封装的芯片安装区域中形成壁而与封装基板的上表面一起界定芯片安装区域，该围栏设置为与封装基板的突起接触；在所述至少一个半导体芯片已经设置在芯片安装区域中并电连接到封装基板的上焊盘之后，在由电磁辐射屏蔽壁和封装基板的上表面界定的芯片安装区域中沉积模制化合物；固化模制化合物或允许模制化合物固化，从而形成模制主体，该模制主体将所述至少一个半导体芯片封装在封装基板上；以及在模制主体之上形成用作电磁辐射屏蔽盖的导电材料盖，设置为与电磁辐射屏蔽壁接触。
附图说明
从以下结合附图进行的详细描述，发明构思将被更清楚地理解，附图中：
图1是根据发明构思的半导体封装的一示例的剖视图；
图2是图1的半导体封装的区域A的放大图；
图3A是封装基板的突出单元的平面图；
图3B是封装基板的突出单元的平面图；
图3C是封装基板的突出单元的平面图；
图4是根据发明构思的半导体封装的另一示例的剖视图；
图5是根据发明构思的半导体封装的另一示例的剖视图；
图6是根据发明构思的半导体封装的另一示例的剖视图；
图7是根据发明构思的半导体封装的另一示例的剖视图；
图8A、图8B、图8C和图8D是半导体封装在其制造的过程中的剖视图，并一起示出了根据发明构思的制造半导体封装的方法的示例；
图9是根据发明构思的大量生产半导体封装的方法的一示例的阶段中的中间产品的剖视图；以及
图10是半导体封装在其制造的过程中的剖视图，示出了根据发明构思的制造半导体封装的方法的示例。
具体实施方式
现在将参照附图更详细地描述根据发明构思的半导体封装及其制造方法的示例。注意，为了方便起见，单个元件或特征可以在下面的描述中被提及，尽管根据发明构思的半导体封装可以如附图所示地具有多个这样的元件或特征。
图1是根据发明构思的半导体封装100的剖视图。图2是图1所示的半导体封装100的区域A的放大图。
一起参照图1和图2，半导体封装100可以包括封装基板110、外部连接单元170、至少一个半导体芯片120、模制单元130、屏蔽壁140以及屏蔽盖150。
封装基板110可以是例如印刷电路板(PCB)。封装基板110可以包括电绝缘材料的至少一个基底层111(其层或多个层可以简称为封装基板的“基底”)、阻焊层112、上焊盘113、下焊盘114和突出单元115。基底层111可以由环氧树脂、聚酯树脂、聚酰亚胺树脂或其组合形成。基底层111可以由例如玻璃纤维环氧复合材料形成。阻焊层112可以覆盖基底层111的上表面和下表面。上焊盘113可以位于基底层111的上表面处，更具体地，位于基底层111的上表面之上，并可以不被阻焊层112覆盖。下焊盘114可以位于基底层111的下表面处，更具体地，位于基底层111的下表面上，并可以不被阻焊层112覆盖。上焊盘113和下焊盘114包括诸如铜(Cu)的导电材料。上焊盘113和下焊盘114可以通过基底层111中的互连(未示出)彼此连接。突出单元115可以从基底层111延伸到屏蔽壁140的下端表面。也就是，突出单元115的一端可以与基底层111接触，突出单元115的另一端可以与屏蔽壁140的下端表面接触。突出单元115可以包括导电材料，诸如铜(Cu)。突出单元115可以与封装基板110的边缘相邻地定位。突出单元115在与封装基板110的上表面平行的方向上具有宽度W。此外，突出单元115从阻焊层112突出距离h。
外部连接单元170可以布置在封装基板110的下焊盘114上。外部连接单元170可以包括金(Au)、铜(Cu)、镍(Ni)、锡(Sn)、铅(Pb)或其组合。外部连接单元170可以包括多个端子，例如焊球。
半导体芯片120可以是逻辑芯片或存储器芯片。在前者的情况下，逻辑芯片可以是例如存储器控制器芯片、中央处理单元(CPU)芯片、图形处理单元(GPU)芯片、或应用处理器(AP)芯片。在后者的情况下，存储器芯片可以是例如动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、快闪存储器芯片、电可擦除可编程只读存储器(EEPROM)芯片、相变随机存取存储器(PRAM)芯片、磁随机存取存储器(MRAM)芯片、或电阻随机存取存储器(RRAM)芯片。在任何情况下，半导体芯片120可以通过芯片粘合层123附接到封装基板110的上表面，在封装的“芯片安装区域”内。半导体芯片120可以通过接合线121电连接到封装基板110。在另一些示例中，半导体芯片120通过导电凸块连接到封装基板110。半导体芯片120可以与屏蔽壁140和屏蔽盖150间隔开。
在一些示例中，所述至少一个半导体芯片120可以包括第一半导体芯片120a和多个第二半导体芯片120b。第一半导体芯片120a和第二半导体芯片120b可以是不同的类型。例如，第一半导体芯片120a可以是逻辑芯片，第二半导体芯片120b可以是存储器芯片。然而，半导体封装100的半导体芯片的数量和类型不限于图中示出的和/或以上描述的那些。
模制单元130可以覆盖封装基板110的上表面并将所述至少一个半导体芯片120封装在封装基板110顶上的芯片安装区域中。模制单元130可以由热固性树脂、热塑性树脂、UV可固化树脂或其组合形成。模制单元130可以包括例如环氧树脂、硅树脂或其组合。模制单元130可以由例如环氧模制化合物(EMC)形成。
屏蔽壁140可以环绕模制单元130延伸。因此，屏蔽壁可以围住芯片安装区域，在该芯片安装区域内所述至少一个芯片120安装到封装基板。屏蔽壁140的一端可以接触封装基板110的突出单元115，屏蔽壁140的另一端可以与屏蔽盖150接触。屏蔽壁140由导电材料诸如铜(Cu)、镍(Ni)、银(Ag)、金(Au)、铁(Fe)或其组合形成。屏蔽壁140可以在平行于封装基板110的上表面(即，封装基板110的基底层11的上表面)的方向上具有第一厚度t1。屏蔽壁140的第一厚度t1可以为例如约10μm至500μm。屏蔽壁140可以通过封装基板110的突出单元115接地。屏蔽壁140的第一厚度t1可以大于突出单元115的宽度W，即，突出单元115在平行于封装基板110的上表面的方向上的上述尺寸。此外，屏蔽壁140的第一厚度t1可以大于突出单元115的高度h，即，在垂直于封装基板110的上表面的方向上从阻焊层112到突出单元115的上表面的上述距离。
在一些示例中，屏蔽壁140通过屏蔽壁粘合层160附接到封装基板110。屏蔽壁粘合层160可以插设在封装基板110的阻焊层112的上表面与屏蔽壁140之间。封装基板110的突出单元115可以延伸穿过屏蔽壁粘合层160。屏蔽壁粘合层160可以是例如环氧树脂。
屏蔽盖150可以覆盖模制单元130的上表面并与屏蔽壁140接触。屏蔽盖150可以由导电材料诸如铜(Cu)、镍(Ni)、银(Ag)、金(Au)、铁(Fe)或其组合形成。在一些示例中，屏蔽盖150是电磁辐射吸收带。在一些示例中，屏蔽盖150是与屏蔽壁140不同的材料。例如，屏蔽壁140可以包括铜(Cu)，屏蔽盖150可以是电磁辐射吸收带。屏蔽盖150可以在垂直于封装基板110的上表面的方向上具有厚度t2。在一些示例中，屏蔽壁140的厚度t1不同于屏蔽盖150的厚度t2。具体地，屏蔽壁140的厚度t1可以大于屏蔽盖150的厚度t2。屏蔽盖150可以通过屏蔽壁140和封装基板110的突出单元115接地。
图3A是封装基板110的突出单元115的一种形式的平面图。
参照图3A，封装基板110的突出单元115可以沿着闭合曲线延伸。此外，封装基板110的突出单元115可以邻近封装基板110的周边延伸，即，紧邻(alongside)封装基板110的周边延伸。在一些示例中，封装基板110具有近似矩形的形状。然而，突出单元115的形状不限于矩形。
图3B是封装基板110的突出单元115b的另一种形式的平面图。
参照图3B，封装基板110的突出单元115b可以包括彼此间隔开的多个部分。突出单元115b的所述多个部分之间的距离d和从阻焊层112的上表面到突出单元115b的上表面的距离h(见图2)足够小以允许突出单元115b实现电磁屏蔽。突出单元115b的所述多个部分可以沿着闭合曲线布置。例如，封装基板110可以具有近似矩形的形状，并且突出单元115b的所述多个部分可以沿着与封装基板110的周边的形状对应的近似矩形的路径布置。然而，突出单元115b的所述部分沿着其布置的闭合路径的形状不限于矩形。
图3C是封装基板110的突出单元115c的另一种形式的平面图。
参照图3C，封装基板110的突出单元115c可以包括分别与封装基板110的边缘相邻的多个部分。在一些示例中，封装基板110具有有四个边缘的近似矩形形状，并且突出单元115c可以具有分别与封装基板110的四个边缘相邻的四个部分。
图4是根据发明构思的半导体封装100a的另一示例的剖视图。在下文，将主要地仅描述图1所示的半导体封装100与图4所示的半导体封装100a之间的差异。
参照图4，屏蔽壁140a可以具有径向地延伸穿过其的至少一个开口140OP。开口140OP可以是孔或狭缝。开口140OP足够小以允许屏蔽壁140a仍然实现所述至少一个半导体芯片120的电磁屏蔽。开口140OP可以具有任何形状(截面)。当由屏蔽壁140a围绕的空间填充有模制化合物(稍后描述)时，开口140OP可以允许多余的模制材料穿过屏蔽壁140a。
图5是根据发明构思的半导体封装200的另一示例的剖视图。
参照图5，半导体封装200可以包括第一子封装SP1、第二子封装SP2和多个封装间连接单元270。也就是，半导体封装200可以是层叠封装(POP)半导体器件。
第一子封装SP1可以包括第一封装基板210、第一半导体芯片220、第一模制单元230、第一屏蔽壁240和第一屏蔽盖250。
第一封装基板210可以是例如PCB。第一封装基板210可以包括基底层211、阻焊层212、上焊盘213、下焊盘214和突出单元215。阻焊层212可以覆盖基底层211的上表面和下表面。上焊盘213可以位于基底层211的上表面之上，并可以不被阻焊层212覆盖。下焊盘214可以位于基底层211的下表面上，并可以不被阻焊层212覆盖。上焊盘213和下焊盘214可以通过基底层211中的互连(未示出)彼此连接。突出单元215可以从基底层211延伸到第一屏蔽壁240的下表面。也就是，突出单元215的一端可以与基底层211接触，其另一端可以与第一屏蔽壁240的下表面接触。突出单元215可以邻近第一封装基板210的边缘定位。
第一半导体芯片220可以是逻辑芯片或存储器芯片。第一半导体芯片220可以通过芯片粘合层223附接到第一封装基板210的上表面。第一半导体芯片220可以通过接合线221连接到第一封装基板210。在另一示例中，第一半导体芯片220通过凸块连接到第一封装基板210。此外，第一半导体芯片220与第一屏蔽壁240和第一屏蔽盖250间隔开。
第一模制单元230可以覆盖第一封装基板210的上表面并围绕第一半导体芯片220。
第一屏蔽壁240可以围绕第一模制单元230的侧面延伸。第一屏蔽壁240的一端可以与第一封装基板210的突出单元215接触，第一屏蔽壁240的另一端可以与第一屏蔽盖250接触。
在一些示例中，第一屏蔽壁240通过第一屏蔽壁粘合层260附接到第一封装基板210。第一屏蔽壁粘合层260可以位于第一封装基板210的阻焊层212与第一屏蔽壁240的下表面之间。第一封装基板210的突出单元215可以延伸穿过第一屏蔽壁粘合层260。
第一屏蔽盖250可以覆盖第一模制单元230的上表面并与第一屏蔽壁240接触。
第二子封装SP2可以包括第二封装基板310、第二半导体芯片320、第二模制单元330和外部连接单元370。
第二封装基板310可以是例如PCB。第二封装基板310可以包括基底层311、阻焊层312、上焊盘313和下焊盘314。阻焊层312可以覆盖基底层311的上表面和下表面。上焊盘313可以位于基底层311的上表面之上，并可以不被阻焊层312覆盖。下焊盘314可以位于基底层311的下表面上，并可以不被阻焊层312覆盖。上焊盘313和下焊盘314可以通过基底层211中的互连(未示出)彼此连接。
第二半导体芯片320可以是逻辑芯片或存储器芯片。第二半导体芯片320可以通过芯片粘合层323附接到第二封装基板310的上表面。第二半导体芯片320可以通过接合线321连接到第二封装基板310。在另一些示例中，第二半导体芯片320通过凸块连接到第二封装基板310。
第二模制单元330可以覆盖第二封装基板310的上表面的至少一部分并围绕第二半导体芯片320。
外部连接单元370可以布置在第二封装基板310的下表面上。
封装间连接单元270可以布置在第一子封装SP1和第二子封装SP2之间。具体地，封装间连接单元270可以布置在第一子封装SP1的第一封装基板210和第二子封装SP2的第二封装基板310之间。封装间连接单元270可以连接第一子封装SP1和第二子封装SP2。封装间连接单元270可以包括例如金(Au)、铜(Cu)、镍(Ni)、锡(Sn)和铅(Pb)或其组合。封装间连接单元270可以包括例如焊球。
图6是根据发明构思的半导体封装200a的另一示例的剖视图。在下文，将主要仅描述图5所示的半导体封装200与图6所示的半导体封装200a之间的差异。
参照图6，第二子封装SP2还可以包括第二屏蔽壁340和第二屏蔽盖350。
第二屏蔽壁340可以环绕第二模制单元330延伸(围绕第二模制单元330的侧面)。多个封装间连接单元270可以布置在第二屏蔽壁340周围。第二屏蔽壁340的一端可以与第二封装基板310的突出单元315接触，第二屏蔽壁340的另一端可以与第二屏蔽盖350接触。
在一些示例中，第二屏蔽壁340通过第二屏蔽壁粘合层360附接到第二封装基板310。第二屏蔽壁粘合层360可以位于第二封装基板310的阻焊层312和第二屏蔽壁340之间。第二封装基板310的突出单元315可以延伸穿过第二屏蔽壁粘合层360。
第二屏蔽盖350可以覆盖第二模制单元330的上表面并与第二屏蔽壁340接触。
图7是根据发明构思的半导体封装200b的另一示例的剖视图。在下文，将主要仅描述图5的半导体封装200与图7的半导体封装200b之间的差异。
参照图7，第一屏蔽壁240a可以具有径向地延伸穿过其的至少一个开口240OP。开口240OP可以是孔或狭缝。开口240OP的尺寸如此小，使得第一屏蔽壁240a仍然能够实现所述至少一个芯片220的电磁屏蔽。当由屏蔽壁240a围绕的空间填充有模制材料以形成模制单元230时，开口240OP允许多余的模制材料穿过屏蔽壁240a。
图8A至图8D示出根据发明构思的制造半导体封装的方法的示例。在这些附图中，之前参照图1-3描述的封装的元件将由相同的附图标记表示。
参照图8A，提供封装基板110。封装基板110包括至少一个基底层(或简称“基底”)111、覆盖基底层111的上表面和下表面的阻焊层112、在基底层111的上表面之上的上焊盘113、在基底层111的下表面上的下焊盘114以及从封装基板110的上表面突出穿过阻焊层112的突出单元115。
可以通过在封装基板110的下表面上形成导电端子来形成外部连接单元170。例如，可以通过在封装基板110的下表面上附接焊球来形成外部连接单元170。
此外，至少一个半导体芯片120(例如第一半导体芯片120a和所述多个第二半导体芯片120b)通过芯片粘合层123在芯片安装区域内附接到封装基板110的上表面。在所示的示例中，单个和/或堆叠的芯片的横向阵列在封装基板110之上的各芯片安装区域内安装到封装基板110。
参照图8B，在封装基板110上形成屏蔽壁140。屏蔽壁140可以通过屏蔽壁粘合层160附接到封装基板110的上表面。例如，可以在封装基板110上形成屏蔽壁粘合层160，可以将屏蔽壁140放置在屏蔽壁粘合层160之上，并且可以通过施加力到屏蔽壁140而朝向封装基板110按压屏蔽壁140。
在一些示例中，屏蔽壁140被按压为与封装基板110的突出单元115接触。在这种情况下，屏蔽壁粘合层160可以形成为覆盖突出单元115。在将屏蔽壁140放置在屏蔽壁粘合层160之上之后，可以向屏蔽壁140施加力，从而迫使封装基板110的突出单元115穿过屏蔽壁粘合层160并与屏蔽壁140接触。
参照图8C，在由屏蔽壁140和封装基板110界定的空间(芯片安装区域)中形成模制单元130。首先，在由屏蔽壁140界定的空间中在封装基板110的上表面上沉积模制材料(即，模制化合物)。然后，固化该模制材料，例如，将该模制材料暴露到UV光，或使得该模制材料固化。因此，分别在所述空间(芯片安装区域)中形成模制主体，即，由屏蔽壁140、封装基板110等模制的材料体。
参照图8D，可以切割屏蔽壁140和封装基板110以在半导体芯片堆叠之间分离封装基板110和屏蔽壁140，从而产生半导体封装的多个离散单元。
参照图1，可以在模制单元130之上形成屏蔽盖150。屏蔽盖150可以通过例如将电磁吸收带附接到模制单元130的顶表面来形成。或者，屏蔽盖150可以通过将电磁吸收(屏蔽)材料喷射到模制单元130的顶部上来形成。在任一种情况下，屏蔽盖150也可以附接到并覆盖屏蔽壁140的上端。
在根据如上所述的发明构思的制造方法中，屏蔽壁140和屏蔽盖150可以容易地、快速且廉价地形成。
图9示出根据发明构思的制造半导体封装的方法的一示例中的阶段，该半导体封装为图4所示的且参照图4描述的类型。该方法的其它阶段类似于图8A-8D所示且参照图8A-图8D描述的那些阶段。
参照图4和图9，屏蔽壁140a具有至少一个开口140OP。模制材料(即，当模制单元130正被形成时已经填充由屏蔽壁140a界定的空间的模制材料)可以进入屏蔽壁140a中的开口140OP，甚至如果过量的模制材料通过模制工艺被迫进入到所述空间中，则模制材料可以穿过屏蔽壁140a中的开口140OP。因此，模制单元130可以容易地形成，而不损坏该空间内的组件并界定该空间。
图10示出根据发明构思的制造图5所示的且参照图5描述的类型的半导体封装的方法的一示例中的阶段。
参照图10，制备第一子封装SP1。第一子封装SP1可以以与图8A至图8D所示并参照图8A至图8D描述的方法类似的方法制备。
首先，提供第一封装基板210。第一封装基板210包括基底层211、覆盖基底层211的上表面和下表面的阻焊层212、在基底层211的上表面之上的上焊盘213、在基底层211的下表面上的下焊盘214以及穿过阻焊层212突出的突出单元215。
在第一封装基板210的下表面上形成封装间连接单元270。例如，可以通过将焊球附接到第一封装基板210的下表面来形成封装间连接单元270。此外，通过芯片粘合层223将第一半导体芯片220附接到第一封装基板210的上表面。
接下来，将第一屏蔽壁240附接到第一封装基板210。第一屏蔽壁240可以通过第一屏蔽壁粘合层260附接到第一封装基板210。
然后，在由第一屏蔽壁240围绕的空间中形成第一模制单元230。
接下来，可以切割第一屏蔽壁240和第一封装基板210。
然后，可以在第一模制单元230的顶上形成第一屏蔽盖250。第一屏蔽盖250可以通过例如将电磁辐射吸收带附接到第一模制单元230的顶表面(以及第一屏蔽壁240的上端)形成。或者，第一屏蔽盖250可以通过用电磁辐射吸收(屏蔽)材料喷射第一模制单元230的顶表面(和第一屏蔽壁240的上端)形成。
另外，制备第二子封装SP2。首先，提供第二封装基板310。第二封装基板310包括基底层311、覆盖基底层311的上表面和下表面的阻焊层312、在基底层311的上表面上的上焊盘313、在基底层311的下表面上的下焊盘314。
在第二封装基板310的下表面上形成外部连接单元370。例如，外部连接单元370可以通过将焊球附接到第二封装基板310的下表面来形成。此外，通过芯片粘合层323将第二半导体芯片320附接到第二封装基板310的上表面。接下来，形成环绕第二半导体芯片320延伸的第二模制单元330。
然后，第一子封装SP1层叠到第二子封装SP2上。因此，可以制造图5所示的半导体封装200。
此外，第二封装基板310还可以包括延伸穿过阻焊层312的突出单元315，并且第二子封装SP2的制备还可以包括：将第二屏蔽壁340附接到第二封装基板310；在由第二屏蔽壁340和第二封装基板310界定的空间中形成模制单元330；以及将第二屏蔽盖350附接到模制单元330的顶表面和第二屏蔽壁340的上端表面。在这种情况下，可以制造图6所示的半导体封装200a。
最后，上面已经详细描述了发明构思的示例。然而，发明构思可以以许多不同的方式付诸实践，而不应被解释为限于上述示例。而是，这些示例被描述，使得本公开透彻和完整，并将发明构思充分传达给本领域技术人员。因此，发明构思的真实精神和范围不受上述示例的限制，而是通过解释下面的权利要求书来限定。
本申请要求于2018年6月26日在韩国知识产权局提交的韩国专利申请第10-2018-0073589号的权益，其公开内容通过引用被整体地结合于此。

Claims (20)

1.一种制造半导体封装的方法，该方法包括：
将至少一个半导体芯片安装到封装基板的上表面；
在所述封装基板之上形成屏蔽壁，该屏蔽壁围绕所述至少一个半导体芯片的侧面延伸；
在由所述屏蔽壁和所述封装基板界定的空间中形成模制主体；以及
形成覆盖所述模制主体并与所述屏蔽壁接触的屏蔽盖。
2.根据权利要求1所述的方法，其中形成所述屏蔽壁包括利用粘合剂将所述屏蔽壁附接到所述封装基板。
3.根据权利要求2所述的方法，其中形成所述屏蔽壁包括：
在所述封装基板的所述上表面上形成屏蔽壁粘合层；
将所述屏蔽壁放置在所述屏蔽壁粘合层之上；以及
抵着所述屏蔽壁粘合层对所述屏蔽壁用力。
4.根据权利要求1所述的方法，其中形成所述屏蔽盖包括将所述屏蔽盖附接到所述模制主体的顶表面。
5.根据权利要求1所述的方法，其中所述屏蔽壁在与所述封装基板的所述上表面平行的方向上的厚度大于所述屏蔽盖在垂直于所述封装基板的所述上表面的方向上的厚度。
6.根据权利要求1所述的方法，其中所述屏蔽壁形成为与所述至少一个半导体芯片间隔开。
7.根据权利要求1所述的方法，其中所述屏蔽盖形成为与所述至少一个半导体芯片间隔开。
8.根据权利要求1所述的方法，其中所述封装基板包括从所述封装基板的所述上表面突出的突起，并且形成所述屏蔽壁包括迫使所述屏蔽壁与所述突起接触。
9.一种制造半导体封装的方法，该方法包括：
提供封装基板，该封装基板包括具有上表面的基底、在所述基底的所述上表面上的阻焊层、以及接触所述基底并延伸到所述阻焊层中的突起；
在所述基底的所述上表面上将至少一个半导体芯片安装到所述封装基板；
将屏蔽壁附接到所述封装基板，所述屏蔽壁在所述突起之上且环绕所述至少一个半导体芯片延伸；
在由所述屏蔽壁和所述封装基板限定的空间中形成模制主体；以及
形成覆盖所述模制主体并与所述屏蔽壁接触的屏蔽盖。
10.根据权利要求9所述的方法，其中将所述屏蔽壁附接到所述封装基板包括：
形成覆盖所述封装基板的所述突起的屏蔽壁粘合层；
将所述屏蔽壁放置在所述屏蔽壁粘合层之上；以及
朝向所述屏蔽壁粘合层对所述屏蔽壁用力，直到所述封装基板的所述突起穿透所述屏蔽壁粘合层并与所述屏蔽壁接触。
11.根据权利要求9所述的方法，其中如在所述半导体封装的平面图中看到的，所述突起沿着闭合环是连续的。
12.根据权利要求9所述的方法，其中如在所述半导体封装的平面图中看到的，所述突起包括沿着闭合环的路径彼此间隔开的多个部分。
13.根据权利要求9所述的方法，其中所述突起包括彼此间隔开的多个部分，每个部分与所述封装基板的侧面中的相应一个相邻地设置。
14.根据权利要求13所述的方法，其中所述封装基板具有四个侧面，并且所述突起由分别与所述封装基板的所述四个侧面相邻的四个部分组成。
15.根据权利要求9所述的方法，其中所述屏蔽壁通过所述封装基板的所述突起接地。
16.根据权利要求9所述的方法，其中所述屏蔽盖通过所述屏蔽壁和所述封装基板的所述突起接地。
17.根据权利要求9所述的方法，其中所述屏蔽壁在与所述封装基板的所述基底的所述上表面平行的方向上的厚度大于所述突起在与所述封装基板的所述基底的所述上表面平行的方向上的宽度。
18.根据权利要求9所述的方法，其中所述屏蔽壁在与所述封装基板的所述基底的所述上表面平行的方向上的厚度大于在垂直于所述封装基板的所述上表面的方向上从所述阻焊层到所述突起的上表面的距离。
19.一种半导体封装的制造方法，该方法包括：
将半导体芯片安装在封装基板的上表面上成水平阵列，其中所述水平阵列的各个芯片在平行于所述封装基板的所述上表面的方向上彼此横向地间隔开；
在所述封装基板之上形成围绕每个所述半导体芯片延伸的屏蔽壁；
在由所述屏蔽壁和所述封装基板界定的空间中沉积模制材料；
固化所述模制材料，从而形成模制主体，该模制主体将所述半导体芯片分别封装在所述空间内的所述封装基板上；
在所述水平阵列的所述半导体芯片之间的区域中切开所述屏蔽壁和所述封装基板；以及
形成覆盖每个所述模制主体的屏蔽盖。
20.根据权利要求19所述的方法，其中所述屏蔽壁具有从其内周表面延伸穿过到其外周表面的至少一个开口，并且在将所述模制材料沉积到由所述屏蔽壁和所述封装基板界定的所述空间中期间，所述模制材料进入所述至少一个开口中。
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