CN110648997A - SiC chip photoetching mark forming method - Google Patents
SiC chip photoetching mark forming method Download PDFInfo
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- CN110648997A CN110648997A CN201910899025.2A CN201910899025A CN110648997A CN 110648997 A CN110648997 A CN 110648997A CN 201910899025 A CN201910899025 A CN 201910899025A CN 110648997 A CN110648997 A CN 110648997A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000001259 photo etching Methods 0.000 title claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 110
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 97
- 229920005591 polysilicon Polymers 0.000 claims abstract description 80
- 238000005530 etching Methods 0.000 claims abstract description 38
- 239000011248 coating agent Substances 0.000 claims abstract description 13
- 238000000576 coating method Methods 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 238000010586 diagram Methods 0.000 description 12
- 238000001459 lithography Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000011856 silicon-based particle Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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Abstract
The invention relates to a method for forming a photoetching mark of a SiC chip, which comprises the following steps: s1: growing a polycrystalline silicon layer on the SiC epitaxial layer; s2: coating photoresist on the polycrystalline silicon layer, and forming a first layer of graph and a marking graph of the SiC chip by single photoetching; s3: etching the polysilicon layer by using photoresist as a mask, and performing ion implantation on the whole wafer after removing the photoresist; s4: coating photoresist on the polysilicon layer, covering the first layer of pattern region of the SiC chip with the photoresist, and exposing the marked pattern region; s5: etching the SiC epitaxial layer of the marked graphic region by using the polycrystalline silicon layer as a mask; s6: removing all the photoresist on the surface; s7: and the second layer of pattern of the SiC chip is subjected to alignment according to the etched mark pattern on the SiC epitaxial layer. In the technical scheme, in the alignment process, the alignment deviation between the etched mark on the SiC epitaxial layer and the first layer of graph of the SiC chip is avoided, and the alignment precision between the etched mark on the SiC epitaxial layer and the second layer of graph of the SiC chip is not influenced by the polycrystalline silicon layer.
Description
Technical Field
The invention belongs to the field of semiconductor devices, and particularly relates to a method for forming a photoetching mark of a SiC chip.
Background
The SiC material has the advantages of large forbidden band width, high breakdown electric field, high saturation drift velocity and high thermal conductivity, and the excellent properties of the materials make the SiC material an ideal material for manufacturing high-power, high-frequency, high-temperature-resistant and anti-radiation devices. At present, various power semiconductor devices such as SBDs, MOSFETs, IGBTs and the like are manufactured by adopting SiC materials. Among them, in SiC MOSFETs, polysilicon is widely used as an ion implantation mask layer. However, due to the isotropic property of the polycrystalline silicon during growth and deposition, the marking grooves etched on the SiC epitaxial layer can be gradually filled along various directions along with the increase of the thickness of the polycrystalline silicon layer, so that the marking appearance is seriously deformed, and the rough polycrystalline silicon particles cover the marking grooves etched on the SiC epitaxial layer, so that the marks are blurred, the signal identification of the marks is influenced, and the photoetching alignment precision between the polycrystalline silicon process layers on the SiC is reduced. Therefore, in order to improve the accuracy of the photolithographic alignment between the polysilicon layers on SiC, it is necessary to eliminate the influence of polysilicon on the mark.
Disclosure of Invention
In order to solve the problems, the invention provides a method for forming a photoetching mark of a SiC chip, which eliminates the influence of fuzzy marks caused by a polycrystalline silicon layer with a certain thickness and improves the alignment precision of photoetching between polycrystalline silicon layers on SiC.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a method for forming a photoetching mark on a SiC chip comprises the following steps:
s1: growing a polycrystalline silicon layer on the SiC epitaxial layer;
s2: coating photoresist on the polycrystalline silicon layer, and forming a first layer of graph and a marking graph of the SiC chip by single photoetching;
s3: etching the polysilicon layer by using photoresist as a mask, and performing ion implantation on the whole wafer after removing the photoresist;
s4: coating photoresist on the polysilicon layer, covering the first layer of pattern region of the SiC chip with the photoresist, and exposing the marked pattern region;
s5: etching the SiC epitaxial layer of the marked graphic region by using the polycrystalline silicon layer as a mask;
s6: removing all the photoresist on the surface;
s7: and the second layer of pattern of the SiC chip is subjected to alignment according to the etched mark pattern on the SiC epitaxial layer.
In this technical solution, further, in step S1, the thickness of the polysilicon layer is greater than 0.5 um.
Further, in step S2, the photoresist thickness is greater than the polysilicon layer thickness.
Further, in step S2, the first layer pattern of the SiC chip and the mark pattern are in the same reticle, wherein the minimum size of the mark pattern is 4um × 4 um.
Further, in step S4, the photoresist thickness is twice or more than twice the polysilicon layer thickness.
Advantageous effects
In the technical scheme, the polycrystalline silicon is used as the ion injection mask of the SiC wafer, the alignment deviation between the etched mark on the SiC epitaxial layer and the first layer of graph of the SiC chip is avoided in the alignment process, and the alignment precision between the etched mark on the SiC epitaxial layer and the second layer of graph of the SiC chip is not influenced by the polycrystalline silicon layer. The method for forming the photoetching mark of the SiC chip not only ensures that the first layer of graph of the SiC chip has no alignment deviation with the mark, but also ensures that no polycrystalline silicon layer is left on the mark left on the etched SiC epitaxial layer, thereby eliminating the influence of the polycrystalline silicon layer with certain thickness on blurring the mark and improving the alignment precision of the photoetching between the polycrystalline silicon layers on the SiC.
Drawings
The invention is further illustrated with reference to the following figures and examples.
FIG. 1 is a schematic diagram of the structure obtained after growing a polysilicon layer of a certain thickness on an epitaxial layer of SiC in an embodiment of the present invention;
FIG. 2 is a schematic diagram of a structure obtained after a first layer pattern and a mark pattern of a SiC chip are formed by single lithography by coating a photoresist on a polysilicon layer in an embodiment of the present invention;
FIG. 3 is a diagram illustrating a structure of an ion implantation mask formed after etching a polysilicon layer and removing a photoresist in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of the structure obtained after the first patterned areas of the SiC chip are protected by photoresist to expose the marked patterned areas in accordance with an embodiment of the present invention;
FIG. 5 is a diagram illustrating a structure obtained after etching the SiC epitaxial layer in the marked pattern region using the polysilicon layer as a mask in accordance with the exemplary embodiment of the present invention;
fig. 6 is a schematic diagram of the structure obtained after removing all the photoresist on the surface in the embodiment of the present invention.
In the drawings:
1. SiC epitaxial layer 2, polysilicon layer 3, first photoresist layer 4, first layer pattern
5. Marking pattern 6, second photoresist layer
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example 1
A method for forming a photoetching mark on a SiC chip comprises the following steps:
s1: growing a polysilicon layer 2 on the SiC epitaxial layer 1, as shown in figure 1;
s2: coating photoresist on the polysilicon layer 2 to form a first photoresist layer 3, and performing single photoetching to form a first layer pattern 4 and a mark pattern 5 of the SiC chip, as shown in FIG. 2;
s3: etching the polysilicon layer 2 by using photoresist as a mask, removing the first photoresist layer 3, and performing ion implantation on the whole wafer as shown in figure 3;
s4: coating photoresist on the polycrystalline silicon layer 2 to form a second photoresist layer 6, covering the first layer diagram and 4 region of the SiC chip with the photoresist, and exposing the region of the mark diagram 5, as shown in the attached figure 4;
s5: etching the SiC epitaxial layer 1 in the region of the mark pattern 5 by using the polysilicon layer 2 as a mask, as shown in figure 5;
s6: removing all the photoresist on the surface, as shown in fig. 6;
s7: and the second layer of graph of the SiC chip is subjected to alignment according to the etched mark graph 5 on the SiC epitaxial layer 1.
In step S1, the polysilicon layer 2 has a thickness greater than 0.5 um. If the thickness of the polysilicon layer 2 is thin, the polysilicon has little effect on the formation of marks on the SiC epitaxial layer using zero layer lithography. The invention is mainly used for improving the photoetching registration precision between process layers of polycrystalline silicon with certain thickness, and the thickness of the polycrystalline silicon layer is generally more than 0.5 um. In this embodiment, the thickness of the polysilicon layer 2 is 0.8 um.
In step S2, the first photoresist layer 3 has a thickness greater than that of the polysilicon layer 2. The thickness of the photoresist is determined primarily by the thickness of the polysilicon and the selectivity of the etched polysilicon to the photoresist. Under proper etching conditions, the etching rate of the polysilicon is 0.31 um/min, the etching rate of the photoresist is 0.21 um/min, and the etching selection ratio of the first photoresist layer 3 to the polysilicon layer 2 is about 1.5. Considering that the photoresist thickness has a margin to keep the photoresist type after etching, the ratio of the photoresist thickness to the polysilicon layer thickness should be larger than 1. In this embodiment, the thickness of the first photoresist layer 3 is 1.2 um.
In step S2, the first layer pattern 4 of the SiC chip and the mark pattern 5 are in the same reticle, where the mark pattern is a mark of a nikon lithography machine, the minimum size is a square hole of an LSA mark, and the size is 4um × 4 um. The width of the scribing groove of the SiC chip is not less than 80um, so that the marking pattern can be placed in the scribing groove of the chip. In this embodiment, the size of the mark pattern is 4um × 4 um.
In step S4, the thickness of the second photoresist layer 6 is twice or more than the thickness of the polysilicon layer 3. The ratio of the thickness of the photoresist to the thickness of the polysilicon layer is not less than 2. Because the polysilicon layer is etched in the previous step, a deeper step is formed. The ratio of the photoresist thickness to the polysilicon layer thickness should be no less than 2, taking into account the photoresist coverage and protection, and the selectivity of etching the polysilicon and photoresist. In this embodiment, the thickness of the second photoresist layer 6 is 1.6 um.
In step S7, the alignment method is the prior art, and will not be described in detail in the embodiments, and the mark formed by etching on the SiC epitaxial layer is not affected by etching or corrosion of polysilicon in the subsequent processes. The pattern of the second layer of the SiC chip and subsequent patterns may be registered in accordance with this label.
Example 2
A method for forming a photoetching mark on a SiC chip comprises the following steps:
s1: growing a polysilicon layer 2 on the SiC epitaxial layer 1, as shown in figure 1;
s2: coating photoresist on the polysilicon layer 2 to form a first photoresist layer 3, and performing single photoetching to form a first layer pattern 4 and a mark pattern 5 of the SiC chip, as shown in FIG. 2;
s3: etching the polysilicon layer 2 by using photoresist as a mask, removing the first photoresist layer 3, and performing ion implantation on the whole wafer as shown in figure 3;
s4: coating photoresist on the polycrystalline silicon layer 2 to form a second photoresist layer 6, covering the first layer diagram and 4 region of the SiC chip with the photoresist, and exposing the region of the mark diagram 5, as shown in the attached figure 4;
s5: etching the SiC epitaxial layer 1 in the region of the mark pattern 5 by using the polysilicon layer 2 as a mask, as shown in figure 5;
s6: removing all the photoresist on the surface, as shown in fig. 6;
s7: and the second layer of graph of the SiC chip is subjected to alignment according to the etched mark graph 5 on the SiC epitaxial layer 1.
In step S1, the polysilicon layer 2 has a thickness greater than 0.5 um. If the thickness of the polysilicon layer 2 is thin, the polysilicon has little effect on the formation of marks on the SiC epitaxial layer using zero layer lithography. The invention is mainly used for improving the photoetching registration precision between process layers of polycrystalline silicon with certain thickness, and the thickness of the polycrystalline silicon layer is generally more than 0.5 um. In this embodiment, the thickness of the polysilicon layer 2 is 1 um.
In step S2, the first photoresist layer 3 has a thickness greater than that of the polysilicon layer 2. The thickness of the photoresist is determined primarily by the thickness of the polysilicon and the selectivity of the etched polysilicon to the photoresist. Under proper etching conditions, the etching rate of the polysilicon is 0.31 um/min, the etching rate of the photoresist is 0.21 um/min, and the etching selection ratio of the first photoresist layer 3 to the polysilicon layer 2 is about 1.5. Considering that the photoresist thickness has a margin to keep the photoresist type after etching, the ratio of the photoresist thickness to the polysilicon layer thickness should be larger than 1. In this embodiment, the thickness of the first photoresist layer 3 is 1.5 um.
In step S2, the first layer pattern 4 of the SiC chip and the mark pattern 5 are in the same reticle, where the mark pattern is a mark of a nikon lithography machine, the minimum size is a square hole of an LSA mark, and the size is 4um × 4 um. The width of the scribing groove of the SiC chip is not less than 80um, so that the marking pattern can be placed in the scribing groove of the chip. In this embodiment, the size of the mark pattern is 4.5um × 4.5 um.
In step S4, the thickness of the second photoresist layer 6 is twice or more than the thickness of the polysilicon layer 3. The ratio of the thickness of the photoresist to the thickness of the polysilicon layer is not less than 2. Because the polysilicon layer is etched in the previous step, a deeper step is formed. The ratio of the photoresist thickness to the polysilicon layer thickness should be no less than 2, taking into account the photoresist coverage and protection, and the selectivity of etching the polysilicon and photoresist. In this embodiment, the thickness of the second photoresist layer 6 is 2 um.
In step S7, the alignment method is the prior art, and will not be described in detail in the embodiments, and the mark formed by etching on the SiC epitaxial layer is not affected by etching or corrosion of polysilicon in the subsequent processes. The pattern of the second layer of the SiC chip and subsequent patterns may be registered in accordance with this label.
Example 3
A method for forming a photoetching mark on a SiC chip comprises the following steps:
s1: growing a polysilicon layer 2 on the SiC epitaxial layer 1, as shown in figure 1;
s2: coating photoresist on the polysilicon layer 2 to form a first photoresist layer 3, and performing single photoetching to form a first layer pattern 4 and a mark pattern 5 of the SiC chip, as shown in FIG. 2;
s3: etching the polysilicon layer 2 by using photoresist as a mask, removing the first photoresist layer 3, and performing ion implantation on the whole wafer as shown in figure 3;
s4: coating photoresist on the polycrystalline silicon layer 2 to form a second photoresist layer 6, covering the first layer diagram and 4 region of the SiC chip with the photoresist, and exposing the region of the mark diagram 5, as shown in the attached figure 4;
s5: etching the SiC epitaxial layer 1 in the region of the mark pattern 5 by using the polysilicon layer 2 as a mask, as shown in figure 5;
s6: removing all the photoresist on the surface, as shown in fig. 6;
s7: and the second layer of graph of the SiC chip is subjected to alignment according to the etched mark graph 5 on the SiC epitaxial layer 1.
In step S1, the polysilicon layer 2 has a thickness greater than 0.5 um. If the thickness of the polysilicon layer 2 is thin, the polysilicon has little effect on the formation of marks on the SiC epitaxial layer using zero layer lithography. The invention is mainly used for improving the photoetching registration precision between process layers of polycrystalline silicon with certain thickness, and the thickness of the polycrystalline silicon layer is generally more than 0.5 um. In this embodiment, the thickness of the polysilicon layer 2 is 1.2 um.
In step S2, the first photoresist layer 3 has a thickness greater than that of the polysilicon layer 2. The thickness of the photoresist is determined primarily by the thickness of the polysilicon and the selectivity of the etched polysilicon to the photoresist. Under proper etching conditions, the etching rate of the polysilicon is 0.31 um/min, the etching rate of the photoresist is 0.21 um/min, and the etching selection ratio of the first photoresist layer 3 to the polysilicon layer 2 is about 1.5. Considering that the photoresist thickness has a margin to keep the photoresist type after etching, the ratio of the photoresist thickness to the polysilicon layer thickness should be larger than 1. In this embodiment, the thickness of the first photoresist layer 3 is 1.8 um.
In step S2, the first layer pattern 4 of the SiC chip and the mark pattern 5 are in the same reticle, where the mark pattern is a mark of a nikon lithography machine, the minimum size is a square hole of an LSA mark, and the size is 4um × 4 um. The width of the scribing groove of the SiC chip is not less than 80um, so that the marking pattern can be placed in the scribing groove of the chip. In this embodiment, the size of the mark pattern is 5um × 5 um.
In step S4, the thickness of the second photoresist layer 6 is twice or more than the thickness of the polysilicon layer 3. The ratio of the thickness of the photoresist to the thickness of the polysilicon layer is not less than 2. Because the polysilicon layer is etched in the previous step, a deeper step is formed. The ratio of the photoresist thickness to the polysilicon layer thickness should be no less than 2, taking into account the photoresist coverage and protection, and the selectivity of etching the polysilicon and photoresist. In this embodiment, the thickness of the second photoresist layer 6 is 2.4 um.
In step S7, the alignment method is the prior art, and will not be described in detail in the embodiments, and the mark formed by etching on the SiC epitaxial layer is not affected by etching or corrosion of polysilicon in the subsequent processes. The pattern of the second layer of the SiC chip and subsequent patterns may be registered in accordance with this label.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (6)
1. A method for forming a photoetching mark on a SiC chip is characterized by comprising the following steps: the method comprises the following steps:
s1: growing a polycrystalline silicon layer on the SiC epitaxial layer;
s2: coating photoresist on the polycrystalline silicon layer, and forming a first layer of graph and a marking graph of the SiC chip by single photoetching;
s3: etching the polysilicon layer by using photoresist as a mask, and performing ion implantation on the whole wafer after removing the photoresist;
s4: coating photoresist on the polysilicon layer, covering the first layer of pattern region of the SiC chip with the photoresist, and exposing the marked pattern region;
s5: etching the SiC epitaxial layer of the marked graphic region by using the polycrystalline silicon layer as a mask;
s6: removing all the photoresist on the surface;
s7: and the second layer of pattern of the SiC chip is subjected to alignment according to the etched mark pattern on the SiC epitaxial layer.
2. The SiC chip lithographic mark forming method according to claim 1, characterized in that: in step S1, the polysilicon layer has a thickness greater than 0.5 um.
3. The SiC chip lithographic mark forming method according to claim 1, characterized in that: in step S2, the photoresist thickness is greater than the polysilicon layer thickness.
4. The SiC chip lithographic mark forming method according to claim 1, characterized in that: in step S2, the first layer pattern of the SiC chip and the mark pattern are in the same reticle.
5. The SiC chip lithographic mark forming method according to claim 1, characterized in that: in step S2, the minimum size of the mark pattern is 4um × 4 um.
6. The SiC chip lithographic mark forming method according to claim 1, characterized in that: in step S4, the photoresist thickness is twice or more than twice the polysilicon layer thickness.
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| WO2021249171A1 (en) * | 2020-06-12 | 2021-12-16 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
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