CN104576400A - Technology integration method of fin field-effect transistor - Google Patents
Technology integration method of fin field-effect transistor Download PDFInfo
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- CN104576400A CN104576400A CN201510030594.5A CN201510030594A CN104576400A CN 104576400 A CN104576400 A CN 104576400A CN 201510030594 A CN201510030594 A CN 201510030594A CN 104576400 A CN104576400 A CN 104576400A
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- effect transistor
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- 238000000034 method Methods 0.000 title claims abstract description 90
- 230000005669 field effect Effects 0.000 title claims abstract description 22
- 230000010354 integration Effects 0.000 title claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 156
- 230000008569 process Effects 0.000 claims abstract description 62
- 238000001259 photo etching Methods 0.000 claims abstract description 54
- 239000012792 core layer Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000003292 glue Substances 0.000 claims description 20
- 238000005259 measurement Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000003667 anti-reflective effect Effects 0.000 claims description 3
- 238000009499 grossing Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 238000000059 patterning Methods 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 238000013461 design Methods 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000012544 monitoring process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a technology integration method of a fin field-effect transistor. After side wall etching and core layer removing in a fin layer patterning technology process, a barrier photoetching model is additionally adopted for performing a photoetching technology, and a virtual pattern for improving the planarization of a fin layer insulating layer, fin layer patterns different from a non-photoresist pattern region in width, a protecting pattern for measuring marks and other patterns contained in the barrier photoetching model are utilized to increase the density of final fin layer patterns, improve the flexibility of fin layer layout design and obtain the fin layer patterns different in width. Thus, on the premise of limited cost increase, multiple devices can be manufactured on a silicon wafer substrate, the uniformity of a follow-up fin layer insulating layer planarization technology and the uniformity of fin layer etching can be improved, and the film thickness measuring marks can be protected.
Description
Technical field
The present invention relates to ic manufacturing technology field, more specifically, relate to a kind of process integration method of fin field-effect transistor.
Background technology
Fin field-effect transistor (FinFET) technology is the cutting edge technology of future generation of integrated circuit industry.FinFET is a kind of multi-door three-dimensional transistor completely newly, and its active layer is also referred to as fin layer.In the patterning process of FinFET fin layer, due to the feature of design rule and the restriction by mask aligner resolution etc., generally use two pieces of reticle and Twi-lithography technique, and adopt side wall hard mask autoregistration pattern technology and line end excision pattern technology respectively, form final fin layer patterning process.
But adopt the autoregistration of side wall hard mask graphically to carry out the patterned technique of fin layer and there are following shortcomings: the first, the fin layer dimension of picture of formation is single.Because side wall growth is generally formed by the technique such as chemical vapour deposition (CVD) or ald, side wall at the bottom of silicon wafer-based on the thickness that deposits be basically identical, so the size of the fin layer final graphics that etching is formed also is consistent using side wall as etch hardmask.Thus different device channel width cannot be defined by changing fin layer width, maybe different components can only be defined by the number change of fin.This proposes very high requirement to design rule, also limit the flexibility of device simultaneously.The second, due to the very thin thickness of the hard mask of side wall, the width of the fin layer figure of formation is just very little, and the size of no matter core layer graphics area, final graphics can only be left in the region of peripheral side wall.So the pattern density formed by the hard mask of side wall is very low, be unfavorable for the flatening process after the etching of follow-up fin layer destination layer and fin layer insulating layer deposition.3rd, side wall hard mask autoregistration pattern technology can destroy the mark of on-line monitoring and measurement.Such as, thickness measure mark etc. need the large block graphics of certain area, but, only have the figure of side wall region to stay after fin layer patterning process, there is not the large block graphics of certain area, therefore cannot on-line monitoring thickness.
How by the method for process integration, the advantage that side wall hard mask autoregistration pattern technology can be kept to bring, can overcome again more above-mentioned shortcomings, is the target of industrial process research staff.
Summary of the invention
The object of the invention is to the above-mentioned defect overcoming prior art existence; a kind of process integration method of fin field-effect transistor is provided; in fin layer patterning process flow process; stopping reticle and photoetching process thereof by increasing by one piece, fin layer final graphics density can be increased, improve follow-up fin layer insulating barrier flatening process and fin layer etch layer uniformity and protect thickness measurement markers.
For achieving the above object, technical scheme of the present invention is as follows:
A process integration method for fin field-effect transistor, for its fin layer manufacturing process, comprises the following steps:
S01: provide semiconductor substrate, forms the etching barrier layer of fin layer destination layer, core layer and core layer on the substrate successively;
S02: the barrier layer of etching core layer and core layer, form core layer figure;
S03: form side wall hard mask layer on the surface of core layer figure, etching side wall hard mask layer also removes core layer, retains the hard mask graph of side wall;
S04: adopt and stop that reticle carries out photoetching process, forms photoetching offset plate figure above the hard mask graph of part;
S05: respectively with the hard mask graph of side wall in photoetching offset plate figure and non-lithographic glue pattern region for barrier layer, fin layer destination layer is etched, to form first, second fin layer figure respectively at photoetching offset plate figure and non-lithographic glue pattern region;
S06: remove photoresist and the hard mask of side wall, carry out photoetching and the etching technics of follow-up line end excision, form first, second final fin layer figure.
Preferably, described fin layer destination layer comprises its etch hard mask layer.
Preferably, in step S04, adopt and stop that reticle is when carrying out photoetching process, by spin-on anti-reflective layer material and photoresist successively, and adopt photoetching process, to form photoetching offset plate figure above the hard mask graph of part.
Preferably, in step S04, adopt and stop that reticle is when carrying out photoetching process, by spin coating photoetching smoothing material, anti-reflecting layer material and photoresist successively, and adopt photoetching process, to form photoetching offset plate figure above the hard mask graph of part.
Preferably, described stop reticle comprises the fin layer figure with non-lithographic glue pattern region different width dimensions.
Preferably, described stop reticle comprise improve the planarization of fin layer insulating barrier virtual pattern, with the fin layer figure of non-lithographic glue pattern region different width dimensions and the protection figure of measurement markers.
Preferably, the density of first, second fin layer figure described is different.
Preferably, the width of first, second fin layer figure described is different.
Preferably, the density of described first fin layer figure is greater than the density of the second fin layer figure.
Preferably, the width of described first fin layer figure is greater than the width of the second fin layer figure.
As can be seen from technique scheme, the present invention in fin layer patterning process flow process side wall etching and core layer removal after, reticle and photoetching process is stopped by increasing by one piece, and by stopping the virtual pattern of the improvement fin layer insulating barrier planarization that reticle comprises, with multiple figures such as the fin layer figure of non-lithographic glue pattern region different width dimensions and the protection figures of measurement markers, to increase final fin layer pattern density, improve the flexibility of fin layer layout design, realize different fin layer width figure, thus under cost increases limited prerequisite, can at the bottom of silicon wafer-based on realize multiple device, improve uniformity and the fin layer etching homogeneity of follow-up fin layer insulating barrier flatening process, protection thickness measurement markers.
Accompanying drawing explanation
Fig. 1 is the flow chart of the process integration method of a kind of fin field-effect transistor of the present invention;
Fig. 2 ~ Fig. 5 is the structural representation making fin field-effect transistor according to the process integration method of Fig. 1.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
It should be noted that, in following embodiment, when describing embodiments of the present invention in detail, in order to clearly represent structure of the present invention so that explanation, special to the structure in accompanying drawing not according to general scale, and carried out partial enlargement, distortion and simplify processes, therefore, should avoid being understood in this, as limitation of the invention.
In following the specific embodiment of the present invention, refer to Fig. 1, and Fig. 2 ~ Fig. 5 is consulted in combination.Wherein, Fig. 1 is the flow chart of the process integration method of a kind of fin field-effect transistor of the present invention, and Fig. 2 ~ Fig. 5 is the structural representation making fin field-effect transistor according to the process integration method of Fig. 1.As shown in Figure 1, the process integration method of a kind of fin field-effect transistor of the present invention, for its fin layer manufacturing process, comprises the following steps:
As shown in frame 01, S01: provide semiconductor substrate, forms the etching barrier layer of fin layer destination layer, core layer and core layer on the substrate successively.
Refer to Fig. 2.Described substrate 24 can be semi-conductor silicon chip, then in described substrate 24, deposits fin layer destination layer 23.Described fin layer destination layer 23 can include its etch hard mask layer (not shown).
As shown in frame 02, S02: the barrier layer of etching core layer and core layer, form core layer figure.
Please continue to refer to Fig. 2.Described fin layer destination layer 23 continues deposition core layer 22 and the etching barrier layer (not shown) of core layer, then, adopts photoetching process, photoetching, etching are carried out to the barrier layer of core layer and core layer 22, and forms core layer figure 22.
As shown in frame 03, S03: form side wall hard mask layer on the surface of core layer figure, etching side wall hard mask layer also removes core layer, retains the hard mask graph of side wall.
Please continue to refer to Fig. 2.Adopt chemical vapour deposition (CVD) or atom layer deposition process, form side wall hard mask layer 21 on the surface of core layer figure 22.
Please then consult Fig. 3.Then, etch side wall hard mask layer 21 and remove core layer 22.Now, the hard mask graph 25 of side wall is retained.
As shown in frame 04, S04: adopt and stop that reticle carries out photoetching process, forms photoetching offset plate figure above the hard mask graph of part.
Refer to Fig. 4.On silicon chip after the hard mask graph 25 of side wall is formed, stop that reticle (figure slightly) carries out photoetching process with increase one piece, object is after completing photoetching process, above the hard mask graph 25-1 of part of diagram a-quadrant, form photoetching offset plate figure 32.Described stop reticle includes the fin layer figure with illustrated non-lithographic glue pattern region B different width dimensions (i.e. the hard mask graph 25-2 of illustrated side wall characterize the width dimensions of fin layer figure).Preferably, described stop reticle can comprise improve the planarization of fin layer insulating barrier virtual pattern, with the fin layer figure of non-lithographic glue pattern region B different width dimensions and the protection figure of measurement markers.
As an alternate embodiment of the present invention, when utilizing above-mentioned stop reticle to carry out photoetching process, can on the silicon chip after the hard mask graph of side wall 25 (i.e. hard mask graph 25-1 and 25-2 of part) is formed, by spin-on anti-reflective layer material 31 and photoresist 32 successively, and adopt photoetching process, to form required photoetching offset plate figure 32 above the part hard mask graph 25-1 of diagram a-quadrant (i.e. photoetching offset plate figure region A), and at non-lithographic glue pattern region B, form the hard mask graph 25-2 of part side wall of exposed state (without photoresist mask).
As a preferred embodiment of the present invention, when utilizing above-mentioned stop reticle to carry out photoetching process, also can on the silicon chip after the hard mask graph of side wall 25 (i.e. hard mask graph 25-1 and 25-2 of part) is formed, by spin coating photoetching smoothing material successively, anti-reflecting layer material 31 and photoresist 32, and adopt photoetching process, to form required photoetching offset plate figure 32 above the part hard mask graph 25-1 of diagram a-quadrant (i.e. photoetching offset plate figure region A), and at non-lithographic glue pattern region B, form the hard mask graph 25-2 of part side wall of exposed state (without photoresist mask).
As shown in frame 05, S05: respectively with the hard mask graph of side wall in photoetching offset plate figure and non-lithographic glue pattern region for barrier layer, fin layer destination layer is etched, to form first, second fin layer figure respectively at photoetching offset plate figure and non-lithographic glue pattern region.
As shown in frame 06, S06: remove photoresist and the hard mask of side wall, carry out photoetching and the etching technics of follow-up line end excision, form first, second final fin layer figure.
Refer to Fig. 5.With the hard mask graph 25-2 of side wall of the photoetching offset plate figure 32 shown in Fig. 4 and non-lithographic glue pattern region B for barrier layer, the fin layer destination layer 23 of below is etched, thus forms the first fin layer figure 33 and the second fin layer figure 34 respectively at photoetching offset plate figure region A and non-lithographic glue pattern region B.Afterwards, remaining photoresist and the hard mask of side wall are removed, and carries out photoetching and the etching technics of follow-up line end excision, first, second final fin layer figure 33,34 can be formed.
When utilizing above-mentioned stop reticle to carry out photoetching process, according to technique needs, that comprise by described stop reticle with fin layer figure that is non-lithographic glue pattern region B different width dimensions (i.e. the hard mask graph of side wall characterize the width dimensions of fin layer figure), obtain the different in width of first, second fin layer figure 33,34 described.Further, as can be seen from Figure 5, the fin layer figure of the larger width dimensions comprised by described stop reticle, obtains the first fin layer figure 33 that relative second fin layer figure 34 has larger width dimensions.Further, that also comprise by described stop reticle with fin layer figure that is non-lithographic glue pattern region B different width dimensions, obtain the different densities of first, second fin layer figure 33,34 described, and the density of described first fin layer figure 33 can be made to be greater than the density of the second fin layer figure 34, and then the density of final fin layer figure can be increased.
In addition, the virtual pattern of improvement fin layer insulating barrier planarization also comprised by described stop reticle and the protection figure of measurement markers, improve uniformity and fin layer etching homogeneity, the protection thickness measurement markers of follow-up fin layer insulating barrier flatening process.
In the prior art, because side wall is formed by the technique such as chemical vapour deposition (CVD) or ald, side wall at the bottom of silicon wafer-based on the thickness that deposits be basically identical.So the size of the fin layer final graphics that etching is formed also is consistent using side wall as etch hardmask, thus cannot defines different device channel width by changing fin layer width, maybe can only define different components by the number change of fin.Meanwhile, due to the very thin thickness of the hard mask of side wall, the width of the fin layer figure of formation is just very little, and the size of no matter core layer graphics area, final graphics can only be left in the region of peripheral side wall.So the pattern density formed by the hard mask of side wall is very low, be unfavorable for the flatening process after the etching of follow-up fin layer destination layer and fin layer insulating layer deposition.In addition, side wall hard mask autoregistration pattern technology also can destroy the mark of on-line monitoring and measurement.Such as, thickness measure mark etc. need the large block graphics of certain area, but, only have the figure of side wall region to stay after fin layer patterning process, there is not the large block graphics of certain area, therefore cannot on-line monitoring thickness.
The present invention in fin layer patterning process flow process side wall etching and core layer removal after, reticle and photoetching process is stopped by increasing by one piece, and by stopping the virtual pattern of the improvement fin layer insulating barrier planarization that reticle comprises, with multiple figures such as the fin layer figure of non-lithographic glue pattern region different width dimensions and the protection figures of measurement markers, to increase final fin layer pattern density, improve the flexibility of fin layer layout design, realize different fin layer width figure, thus under cost increases limited prerequisite, can at the bottom of silicon wafer-based on realize multiple device, improve uniformity and the fin layer etching homogeneity of follow-up fin layer insulating barrier flatening process, protection thickness measurement markers.Therefore, the present invention stops reticle and photoetching process by introducing, and greatly improves the defect that the hard mask autoregistration of current employing side wall is graphically carried out existing for fin layer patterning process.
Above-describedly be only the preferred embodiments of the present invention; described embodiment is also not used to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. a process integration method for fin field-effect transistor, for its fin layer manufacturing process, is characterized in that, comprise the following steps:
S01: provide semiconductor substrate, forms the etching barrier layer of fin layer destination layer, core layer and core layer on the substrate successively;
S02: the barrier layer of etching core layer and core layer, form core layer figure;
S03: form side wall hard mask layer on the surface of core layer figure, etching side wall hard mask layer also removes core layer, retains the hard mask graph of side wall;
S04: adopt and stop that reticle carries out photoetching process, forms photoetching offset plate figure above the hard mask graph of part;
S05: respectively with the hard mask graph of side wall in photoetching offset plate figure and non-lithographic glue pattern region for barrier layer, fin layer destination layer is etched, to form first, second fin layer figure respectively at photoetching offset plate figure and non-lithographic glue pattern region;
S06: remove photoresist and the hard mask of side wall, carry out photoetching and the etching technics of follow-up line end excision, form first, second final fin layer figure.
2. the process integration method of fin field-effect transistor according to claim 1, is characterized in that, described fin layer destination layer comprises its etch hard mask layer.
3. the process integration method of fin field-effect transistor according to claim 1, it is characterized in that, in step S04, when adopting stop reticle to carry out photoetching process, by spin-on anti-reflective layer material and photoresist successively, and adopt photoetching process, to form photoetching offset plate figure above the hard mask graph of part.
4. the process integration method of fin field-effect transistor according to claim 1, it is characterized in that, in step S04, when adopting stop reticle to carry out photoetching process, by spin coating photoetching smoothing material, anti-reflecting layer material and photoresist successively, and adopt photoetching process, to form photoetching offset plate figure above the hard mask graph of part.
5. the process integration method of fin field-effect transistor according to claim 1, is characterized in that, described stop reticle comprises the fin layer figure with non-lithographic glue pattern region different width dimensions.
6. the process integration method of fin field-effect transistor according to claim 1 or 5; it is characterized in that, described stop reticle comprise improve the planarization of fin layer insulating barrier virtual pattern, with the fin layer figure of non-lithographic glue pattern region different width dimensions and the protection figure of measurement markers.
7. the process integration method of fin field-effect transistor according to claim 1, is characterized in that, the density of first, second fin layer figure described is different.
8. the process integration method of fin field-effect transistor according to claim 1, is characterized in that, the width of first, second fin layer figure described is different.
9. the process integration method of the fin field-effect transistor according to claim 1 or 7, is characterized in that, the density of described first fin layer figure is greater than the density of the second fin layer figure.
10. the process integration method of the fin field-effect transistor according to claim 1 or 8, is characterized in that, the width of described first fin layer figure is greater than the width of the second fin layer figure.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107039436A (en) * | 2016-01-11 | 2017-08-11 | 三星电子株式会社 | Semiconductor devices and its manufacture method |
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| US20100207248A1 (en) * | 2009-02-13 | 2010-08-19 | Hynix Semiconductor Inc. | Patterns of Semiconductor Device and Method of Forming the Same |
| US20120220132A1 (en) * | 2011-02-25 | 2012-08-30 | Tokyo Electron Limited | Semiconductor device manufacturing method |
| CN103855019A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| KR20090072787A (en) * | 2007-12-28 | 2009-07-02 | 주식회사 하이닉스반도체 | Method for forming alignment pattern in semiconductor device |
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Application publication date: 20150429 |