CN116564807A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN116564807A
CN116564807A CN202210113709.7A CN202210113709A CN116564807A CN 116564807 A CN116564807 A CN 116564807A CN 202210113709 A CN202210113709 A CN 202210113709A CN 116564807 A CN116564807 A CN 116564807A
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China
Prior art keywords
mask
layer
forming
dimension
width
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CN202210113709.7A
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Chinese (zh)
Inventor
李凤美
赵振阳
柯星
纪世良
张海洋
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210113709.7A priority Critical patent/CN116564807A/en
Publication of CN116564807A publication Critical patent/CN116564807A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a base and a layer to be etched, and the substrate comprises a first area and a second area; forming a plurality of first initial mask structures on the first region, and forming a plurality of second mask structures on the second region, wherein the first initial mask structures have a first width deviation dimension, and the second mask structures have a second width deviation dimension; forming a first sacrificial layer on the layer to be etched and the second mask structure; and etching the first initial mask structure based on the first advanced process control technology to form a first mask structure, wherein the first mask structure has a second width dimension and a third width deviation dimension, and the third width deviation dimension is equal to the second width deviation dimension. The first advanced process control technology is utilized to carry out algorithm optimization, so that the third width deviation size is equal to the second width deviation size, and the process steps of additionally forming a sacrificial layer and then covering the first mask structure are omitted.

Description

Method for forming semiconductor structure
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method for forming a semiconductor structure.
Background
Advanced process control (APC, advanced Process Control) research in semiconductor processing aims to effectively monitor process and equipment to improve yield and overall device performance.
With the continuous decrease of semiconductor process nodes, the process window is smaller and smaller during the processing of semiconductor devices, which puts forward stricter process control requirements on integrated circuit devices and inspection devices, and the conventional statistical process control (SPC, statistical Process Control) and the control method for a certain parameter alone cannot adapt to the current process technical requirements, so that the advanced process control technology becomes one of the key technologies of the semiconductor process. Advanced process control technology is gradually accepted as a main solution, including semiconductor equipment suppliers, measurement equipment suppliers, manufacturers, and the like, and has been gradually popularized and applied in chemical mechanical polishing, chemical vapor deposition, photolithography, etching, and the like.
The advanced process control technology aims at solving the problem of drift of the average value of results caused by fluctuation of various parameters and performance indexes in the process between different wafers, can effectively shorten the time required by measurement, timely adjust process variables, and is beneficial to improving productivity, reducing energy consumption, improving product quality and continuity, improving process safety and the like, so that process equipment can realize a stricter process window and meet the continuous reduction requirement of semiconductor process nodes.
Although advanced process control techniques are used to control the etching process in the prior art, the prior art still has the problems of low wafer production yield and low reliability.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure so as to improve the production yield and the reliability of a wafer.
In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a base and a layer to be etched positioned on the base, and the substrate comprises a first area and a second area; forming a plurality of first initial mask structures which are arranged in parallel along a first direction on the first region, and forming a plurality of second mask structures which are arranged in parallel along the first direction on the second region, wherein the initial first mask structures have a first width dimension and a first width deviation dimension in the first direction, and the second mask structures have a second width deviation dimension difference in the first direction; forming a first sacrificial layer on the layer to be etched and the second mask structure, wherein the first sacrificial layer exposes the first region and the first initial mask structure; based on a first advanced process control technology, etching the first initial mask structure by taking the first sacrificial layer as a mask to form a first mask structure, wherein the first mask structure has a second width dimension and a third width deviation dimension in the first direction, the second width dimension is smaller than the first width dimension, and the third width deviation dimension is equal to the second width deviation dimension; removing the first sacrificial layer; forming a protective layer covering the first mask structure and the second mask structure based on a second advanced process control technology, so that the first mask structure and the protective layer form a first patterned structure, the second mask structure and the protective layer form a second patterned structure, the first patterned structure has a fourth deviation width dimension in the first direction, the second patterned structure has a fifth width deviation dimension in the first direction, and the fourth width deviation dimension and the fifth width deviation dimension are equal; and etching the layer to be etched by taking the first patterned structure and the second patterned structure as masks, forming a plurality of first device structures in the first region, and forming a plurality of second device structures in the second region.
Optionally, the fourth width deviation dimension is 0; the fifth width deviation dimension is 0.
Optionally, the layer to be etched further includes a third region, and the third region is provided with a plurality of third mask structures arranged in parallel along the first direction, and the third mask structures have a sixth deviation size in the first direction.
Optionally, after removing the first sacrificial layer and before forming the protective layer, the method further includes: forming a second sacrificial layer on the layer to be etched and the third mask structure, wherein the second sacrificial layer exposes the first mask structure and the second mask structure; after the protective layer is formed, the fourth width deviation dimension is equal to the sixth width deviation dimension, and the fifth width deviation dimension is equal to the sixth width deviation dimension.
Optionally, forming the first device structure and the second device structure based on a third advanced process control technology, and during forming the first device structure and the second device structure, further comprising: and etching the layer to be etched by using the third mask structure, and forming a plurality of third device structures in the third region, wherein the first device structures have seventh width deviation sizes in the first direction, the second device structures have eighth width deviation sizes in the first direction, and the third device structures have ninth width deviation sizes in the first direction.
Optionally, the seventh width deviation dimension is 0; the eighth width deviation dimension is 0; the ninth width deviation dimension is 0.
Optionally, the forming method of the first initial mask structure and the second mask structure includes: forming a mask material layer on the layer to be etched; forming a patterned layer on the mask material layer, wherein the patterned layer exposes a part of the top surface of the mask material layer; and etching the mask material layer by taking the patterned layer as a mask until the top surface of the layer to be etched is exposed, so as to form the first initial mask structure and the second mask structure.
Optionally, the process of etching the mask material layer by using the patterned layer as a mask includes: and (5) a dry etching process.
Optionally, the material of the mask material layer includes: silicon oxide or silicon nitride.
Optionally, the protective layer is further located on the top surface of the layer to be etched.
Optionally, the forming process of the protective layer includes: atomic layer deposition process.
Optionally, the material of the protective layer includes: and (3) silicon oxide.
Optionally, the process of etching the first initial mask structure includes: and (5) a dry etching process.
Optionally, the process of etching the layer to be etched by using the first mask structure, the second mask structure and the protection layer as masks includes: a dry etching process of plasma.
Optionally, the material of the layer to be etched includes: a semiconductor material; the semiconductor material includes: silicon or silicon germanium.
Optionally, the first device structure and the second device structure respectively include: a fin.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor structure, the first advanced process control technology is utilized to perform algorithm optimization, so that the third width deviation size of the first mask structure is equal to the second width deviation size of the second mask structure; and forming a global covered protective layer by using the second advanced process control technology, wherein the fourth width deviation size of the first patterned structure is equal to the fifth width deviation size of the second patterned structure through thickness compensation of the protective layer, so that the process step of additionally forming a sacrificial layer and then covering the first mask structure is omitted.
Further, the fourth width deviation dimension is 0; the fifth width deviation size is 0, so that the width deviation sizes of various patterns can be eliminated accurately, the accuracy of subsequent pattern transmission is further ensured, and the production yield and reliability of the wafer are improved.
Further, after removing the first sacrificial layer and before forming the protective layer, further comprising: forming a second sacrificial layer on the layer to be etched and the third mask structure, wherein the second sacrificial layer exposes the first mask structure and the second mask structure; after the protective layer is formed, the fourth width deviation dimension is equal to the sixth width deviation dimension, and the fifth width deviation dimension is equal to the sixth width deviation dimension. The step of forming the second sacrificial layer, in which the second sacrificial layer exposes the first mask structure and the second mask structure, is utilized to ensure that the fourth width deviation dimension of the first patterned structure, the fifth width deviation dimension of the second patterned structure and the sixth width deviation dimension of the third mask structure are equal, thereby omitting the process step of additionally forming the sacrificial layer and then covering the first mask structure and the second mask structure.
Further, forming the first device structure and the second device structure based on a third advanced process control technique, and during forming the first device structure and the second device structure, further comprising: etching the layer to be etched by using the third mask structure, and forming a plurality of third device structures in the third region, wherein the first device structures have seventh width deviation sizes in the first direction, the second device structures have eighth width deviation sizes in the first direction, and the third device structures have ninth width deviation sizes in the first direction; the seventh width deviation dimension is 0; the eighth width deviation dimension is 0; the ninth width deviation dimension is 0. The width deviation of various patterns can be simultaneously and accurately eliminated, and further the accuracy of the width dimensions of the first device structure, the second device structure and the third device structure is improved, and the production yield and the reliability of the wafer are improved.
Drawings
FIGS. 1-3 are schematic views of steps of a method for forming a semiconductor structure;
fig. 4 to 10 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 11 to 18 are schematic views illustrating steps of a method for forming a semiconductor structure according to another embodiment of the present invention.
Detailed Description
As described in the background art, although the advanced process control technology is adopted in the prior art to control the etching process, the problem of low wafer production yield and low reliability still exists in the prior art. The following will make a detailed description with reference to the accompanying drawings.
Fig. 1 to 3 are schematic structural views illustrating steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, the substrate includes a base 100 and a layer 101 to be etched on the base 100, the substrate includes a first region I and a second region II, the first region I has a plurality of first initial mask structures 102 arranged in parallel along a first direction, the first initial mask structures 102 have a first width dimension d1, the first initial mask structures 102 have a first width deviation dimension Δ1, the second region II has a plurality of second mask structures 103 arranged in parallel along the first direction, and the second mask structures 103 have a second width deviation dimension Δ2.
Referring to fig. 2, a first sacrificial layer 104 is formed on the layer to be etched 101 and on the second mask structure 103, and the first sacrificial layer 104 exposes the first region I and the first initial mask structure 102; based on a first advanced process control technique, the first initial mask structure 102 is etched to form a first mask structure 105, the first mask structure 105 has a second width dimension d2, the second width dimension d2 is smaller than the first width dimension d1, and the first mask structure 105 does not have a width deviation dimension.
Referring to fig. 3, after forming the first mask structure 105, the first sacrificial layer 104 is removed; forming a protective layer 106 on the sidewall and top surface of the first mask structure 105 and on the sidewall and top surface of the second mask structure 103, such that the first mask structure 105 and the protective layer 106 form a first patterned structure (not labeled), and the second mask structure 103 and the protective layer 106 form a second patterned structure; and etching the layer 101 to be etched by taking the first patterned structure and the second patterned structure as masks, forming a plurality of first device structures 107 in the first area I, and forming a plurality of second device structures 108 in the second area II.
In this embodiment, in the process of forming the first initial mask structure 102 and the second mask structure 103, due to process fluctuation, there is a difference between the first width d1 of the first initial mask structure 102 and a preset first target width, so that the first initial mask structure 102 has the first width deviation Δ1, and similarly, the second mask structure 103 has the second width deviation Δ2.
Since the width of the first mask structure 105 is different from the width of the second mask structure 103 in process design, the etching adjustment needs to be performed on the first initial mask structure 102. A first advanced process control technique is employed during the etch adjustment such that the first mask structure 105 is formed without a width deviation dimension.
However, when performing etching adjustment on the first initial mask structure 102, the second mask structure 103 needs to be covered by the first sacrificial layer 104. Therefore, the first advanced process control technique cannot compensate the second width deviation Δ2 of the second mask structure 103, so that the second width deviation Δ2 of the second mask structure 103 is always present. The second patterned structure is used as a mask to etch the layer 101 to be etched, which also causes deviation in the feature size of the finally formed second device structure 108, thereby resulting in lower wafer yield and reliability.
In addition, since the advanced process control technology is a global process, the bias adjustment of each structure is kept consistent, and if the second width bias dimension Δ2 is to be compensated by the advanced process control technology, a sacrificial layer is further required to be formed to cover the first mask structure 105, so that the number of process steps is increased.
On the basis, the invention provides a method for forming a semiconductor structure, which utilizes the first advanced process control technology to carry out algorithm optimization so that the third width deviation size of the first mask structure is equal to the second width deviation size of the second mask structure; and forming a global covered protective layer by using the second advanced process control technology, wherein the fourth width deviation size of the first patterned structure is equal to the fifth width deviation size of the second patterned structure through thickness compensation of the protective layer, so that the process step of additionally forming a sacrificial layer and then covering the first mask structure is omitted.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 10 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate is provided, the substrate includes a base 200 and a layer 201 to be etched on the base 200, and the substrate includes a first region I and a second region II.
In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium.
In this embodiment, the material of the layer 201 to be etched is a semiconductor material; the semiconductor material is silicon. In other embodiments, the semiconductor material may also be silicon germanium.
In other embodiments, the material of the layer to be etched may also be metal.
In this embodiment, the layer 201 to be etched in the first region I is used for forming a plurality of first fin portions subsequently, the layer 201 to be etched in the second region II is used for forming a plurality of second fin portions subsequently, the width dimension of the first fin portions in terms of design requirements is smaller, the space dimension between adjacent first fin portions is larger, the width dimension of the second fin portions in terms of design requirements is larger, and the space dimension between adjacent second fin portions is smaller.
Referring to fig. 5, a plurality of first initial mask structures 202 are formed on the first region I and arranged in parallel along a first direction X, a plurality of second mask structures 203 are formed on the second region II and arranged in parallel along the first direction X, the initial first mask structures 202 have a first width dimension d1 and a first width deviation dimension Δ1 along the first direction X, and the second mask structures 203 have a second width deviation dimension Δ2 along the first direction X.
In this embodiment, the first deviation dimension Δ1 is a deviation between the actual width and the target width of the first initial mask structure 202, and the second deviation dimension Δ2 is a deviation between the actual width and the target width of the second mask structure 203.
In this embodiment, the forming method of the first initial mask structure 202 and the second mask structure 203 includes: forming a mask material layer (not shown) on the layer 201 to be etched; forming a patterned layer (not shown) on the mask material layer, the patterned layer exposing a portion of a top surface of the mask material layer; and etching the mask material layer by taking the patterned layer as a mask until the top surface of the layer 201 to be etched is exposed, thereby forming the first initial mask structure 202 and the second mask structure 203.
In this embodiment, the process of etching the mask material layer with the patterned layer as a mask uses a dry etching process.
In this embodiment, the mask material layer is made of silicon oxide; in other embodiments, the material of the mask material layer may also be silicon nitride.
Referring to fig. 6, a first sacrificial layer 204 is formed on the layer 201 to be etched and on the second mask structure 203, and the first sacrificial layer 204 exposes the first region I and the first initial mask structure 202.
It should be noted that, in order to reduce the process cost, the first initial mask structure 202 and the second mask structure 203 are formed by using the same Zhang Guangzhao. However, since the first fin portion and the second fin portion have different feature sizes, the feature sizes of the second mask structure 203 and the subsequently formed first mask structure are required to be correspondingly different. However, due to the limitation of photolithography, the first initial mask structure 202 and the second mask structure 203 formed by one photomask cannot meet the corresponding feature size requirement at the same time, and therefore, further adjustment processing needs to be performed on the first initial mask structure 202 to further reduce the critical dimension, so that the first mask structure and the second mask structure 203 meet the corresponding feature size requirement.
In this embodiment, in order to avoid affecting the second mask structure 203 when performing the adjustment process on the first initial mask structure 202, the second mask structure 203 needs to be covered by the sacrificial layer 204.
In this embodiment, the material of the sacrificial layer 204 is photoresist.
Referring to fig. 7, based on a first advanced process control technology, the first sacrificial layer 204 is used as a mask to perform etching treatment on the first initial mask structure 202, so as to form a first mask structure 205, wherein the first mask structure 205 has a second width dimension d2 and a third width deviation dimension Δ3 in the first direction X, the second width dimension d2 is smaller than the first width dimension d1, and the third width deviation dimension Δ3 is equal to the second width deviation dimension Δ2.
In this embodiment, the third width deviation dimension Δ3 is a deviation between the actual width of the first mask structure 205 and the target width.
In this embodiment, the algorithm optimization is performed by using the first advanced process control technology, so that the third width deviation dimension Δ3 of the first mask structure 202 is equal to the second width deviation dimension Δ2 of the second mask structure 203, so that the second width deviation dimension Δ2 and the third width deviation dimension Δ3 can be eliminated synchronously by using additional advanced process control technology.
In this embodiment, a dry etching process is used for the etching process of the first initial mask structure 202.
Referring to fig. 8, after the first mask structure 205 is formed, the first sacrificial layer 204 is removed.
In this embodiment, the process of removing the first sacrificial layer 204 uses an ashing process.
Referring to fig. 9, after the first sacrificial layer 204 is removed, a protection layer 206 is formed on the sidewall and the top surface of the first mask structure 205 and on the sidewall and the top surface of the second mask structure 203 based on a second advanced process control technology, so that the first mask structure 205 and the protection layer 206 form a first patterned structure, the second mask structure 203 and the protection layer 206 form a second patterned structure, the first patterned structure has a fourth offset width dimension Δ4 in the first direction X, the second patterned structure has a fifth width offset dimension Δ5 in the first direction X, and the fourth width offset dimension Δ4 and the fifth width offset dimension Δ5 are equal.
In this embodiment, the fourth deviation width dimension Δ4 is a deviation between the actual width of the first patterned structure and the target width, and the fifth deviation width dimension Δ5 is a deviation between the actual width of the second patterned structure and the target width.
In this embodiment, the algorithm optimization is performed by using the first advanced process control technology, so that the third width deviation dimension Δ3 of the first mask structure 205 is equal to the second width deviation dimension Δ2 of the second mask structure 203; the global covered protection layer 206 is formed by the additional second advanced process control technology, and the thickness compensation of the protection layer 206 can ensure that the fourth width deviation dimension Δ4 of the first patterned structure is equal to the fifth width deviation dimension Δ5 of the second patterned structure, thereby omitting the process steps of additionally forming a sacrificial layer and then covering the first mask structure 205.
In this embodiment, the fourth width deviation dimension Δ4 is 0; the fifth width deviation dimension delta 5 is 0, so that the width deviation dimensions of various patterns can be eliminated accurately, the accuracy of subsequent pattern transmission is further ensured, and the production yield and reliability of the wafer are improved.
In this embodiment, the protection layer 206 is used to reduce the influence of lateral etching on the width dimensions of the first mask structure 205 and the second mask structure 203 in the subsequent patterning process, so as to ensure that the first fin portion and the second fin portion formed after the patterning process are consistent with the target feature dimensions.
In this embodiment, the protection layer 206 is further located on the top surface of the layer 201 to be etched.
In this embodiment, the formation process of the protection layer 206 uses an atomic layer deposition process.
In this embodiment, the material of the protection layer 206 is silicon oxide.
It should be noted that, although the protection layer 206 is still located on the top surface of the layer 201 to be etched, the thickness is very thin, and the protection layer 206 located on the top surface of the layer 201 to be etched may be directly bombarded and etched by a plasma etching process in the subsequent process of pattern transfer. Therefore, after the protective layer 206 is formed by an atomic layer deposition process, no further processing is required even though the protective layer 206 is still located on the top surface of the layer 201 to be etched.
Referring to fig. 10, the layer 201 to be etched is etched by using the first patterned structure and the second patterned structure as masks, a plurality of first device structures 207 are formed in the first region I, and a plurality of second device structures 208 are formed in the second region II.
In this embodiment, the process of etching the layer 201 to be etched using the first mask structure 205, the second mask structure 203, and the protection layer 206 as masks uses a dry etching process of plasma.
In this embodiment, the first device structure 207 and the second device structure 208 are fin portions respectively. I.e. the first device structure 207 is a first fin portion, and the second device structure 208 is a second fin portion.
In other embodiments, when the material of the layer to be etched is metal, the first device structure and the second device structure may also be conductive layers.
Fig. 11 to 18 are schematic views illustrating steps of a method for forming a semiconductor structure according to another embodiment of the present invention.
The present embodiment is a description of a method for forming a semiconductor structure based on the above embodiment, and is different from the above embodiment in that: the layer 201 to be etched further includes a third region III, where a plurality of third mask structures are disposed on the third region III and are arranged in parallel along the first direction X, and the third mask structures have a sixth deviation dimension in the first direction X. The following will make a detailed description with reference to the accompanying drawings.
Referring to fig. 11, the layer 201 to be etched further includes a third region III, on which a plurality of third mask structures 209 are arranged in parallel along the first direction X, where the third mask structures 209 have a sixth deviation dimension Δ6 in the first direction X.
In this embodiment, the sixth deviation dimension Δ6 is a deviation between the actual width of the third mask structure 209 and the target width.
In this embodiment, the third mask structure 209 is used to form a third device structure through patterning.
In this embodiment, the forming method of the first initial mask structure 202, the second mask structure 203, and the third mask structure 209 includes: forming a mask material layer (not shown) on the layer 201 to be etched; forming a patterned layer (not shown) on the mask material layer, the patterned layer exposing a portion of a top surface of the mask material layer; and etching the mask material layer by taking the patterned layer as a mask until the top surface of the layer 201 to be etched is exposed, so as to form the first initial mask structure 202, the second mask structure 203 and the third mask structure 209.
Referring to fig. 12, a first sacrificial layer 204 is formed on the layer 201 to be etched, the second mask structure 203 and the third mask structure 209, and the first sacrificial layer 204 exposes the first region I and the first initial mask structure 202.
In this embodiment, the function of the first sacrificial layer 204 is the same as that of the material and the above embodiment, and will not be described in detail herein.
Referring to fig. 13, based on a first advanced process control technology, the first sacrificial layer 204 is used as a mask to perform etching treatment on the first initial mask structure 202, so as to form a first mask structure 205, wherein the first mask structure 205 has a second width dimension d2 and a third width deviation dimension Δ3 in the first direction X, the second width dimension d2 is smaller than the first width dimension d1, and the third width deviation dimension Δ3 is equal to the second width deviation dimension Δ2.
In this embodiment, the third width deviation dimension Δ3 is a deviation between the actual width of the first mask structure 205 and the target width.
In this embodiment, the etching process of the first initial mask structure 202 is the same as that in the above embodiment, and will not be described in detail herein.
Referring to fig. 14, after the first mask structure 205 is formed, the first sacrificial layer 204 is removed.
In this embodiment, the process of removing the first sacrificial layer 204 is the same as that in the above embodiment, and will not be described in detail herein.
Referring to fig. 15, after the first sacrificial layer 204 is removed, a second sacrificial layer 210 is formed on the layer to be etched 201 and on the third mask structure 209, and the second sacrificial layer 210 exposes the first mask structure 205 and the second mask structure 203.
In this embodiment, the material of the second sacrificial layer 210 is photoresist.
Referring to fig. 16, after the second sacrificial layer 210 is formed, a protection layer 206 is formed on the sidewall and the top surface of the first mask structure 205 and on the sidewall and the top surface of the second mask structure 203 based on a second advanced process control technology, so that the first mask structure 203 and the protection layer 206 form a first patterned structure, the second mask structure 203 and the protection layer 206 form a second patterned structure, the first patterned structure has a fourth offset width dimension Δ4 in the first direction X, the second patterned structure has a fifth width offset dimension Δ5 in the first direction X, and the fourth width offset dimension Δ4 and the fifth width offset dimension Δ5 are equal.
In this embodiment, the fourth deviation width dimension Δ4 is a deviation between the actual width of the first patterned structure and the target width, and the fifth deviation width dimension Δ5 is a deviation between the actual width of the second patterned structure and the target width.
In this embodiment, the fourth width deviation dimension Δ4 is not 0, and the fifth width deviation dimension Δ5 is not 0.
In the present embodiment, the fourth width deviation dimension Δ4 is equal to the sixth width deviation dimension Δ6, and the fifth width deviation dimension Δ5 is equal to the sixth width deviation dimension Δ6. By using the existing step of forming the second sacrificial layer 210 in the process, the second sacrificial layer 210 exposes the first mask structure 205 and the second mask structure 203, so that the fourth width deviation dimension Δ4 of the first patterned structure, the fifth width deviation dimension Δ5 of the second patterned structure, and the sixth width deviation dimension Δ6 of the third mask structure 209 are equal, and the additional step of forming the sacrificial layer and then covering the first mask structure 205 and the second mask structure 203 is omitted.
In this embodiment, the material and the forming process of the protection layer 206 are the same as those in the above embodiment, and will not be described herein.
Referring to fig. 17, after the protective layer 206 is formed, the second sacrificial layer 210 is removed.
In this embodiment, the process of removing the second sacrificial layer 210 uses an ashing process.
Referring to fig. 18, the first device structure 207 and the second device structure 208 are formed based on a third advanced process control technology, and in the process of forming the first device structure 207 and the second device structure 208, the layer 201 to be etched is etched with the third mask structure 209, and a plurality of third device structures 211 are formed in the third region III, wherein the first device structure 207 has a seventh width deviation dimension Δ7 in the first direction X, the second device structure 208 has an eighth width deviation dimension Δ8 in the first direction X, and the third device structure 211 has a ninth width deviation dimension Δ9 in the first direction X.
In this embodiment, the seventh width deviation dimension Δ7 is a deviation between the actual width of the first device structure 207 and the target width, the eighth width deviation dimension Δ8 is a deviation between the actual width of the second device structure 208 and the target width, and the ninth width deviation dimension Δ9 is a deviation between the actual width of the third device structure 211 and the target width.
In this embodiment, the seventh width deviation dimension Δ7 is 0; the eighth width deviation dimension Δ8 is 0; the ninth width deviation dimension Δ9 is 0. Through the advanced process control technology, the width deviation of various patterns can be simultaneously and accurately eliminated, so that the accuracy of the width dimensions of the first device structure 207, the second device structure 208 and the third device structure 211 is improved, and the wafer production yield and reliability are improved.
In this embodiment, the first device structure 207 and the second device structure 208 are identical to those in the above embodiment, and will not be described in detail herein.
In this embodiment, the third device structure 211 is a third fin portion.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a base and a layer to be etched positioned on the base, and the substrate comprises a first area and a second area;
forming a plurality of first initial mask structures which are arranged in parallel along a first direction on the first region, and forming a plurality of second mask structures which are arranged in parallel along the first direction on the second region, wherein the initial first mask structures have a first width dimension and a first width deviation dimension in the first direction, and the second mask structures have a second width deviation dimension difference in the first direction;
forming a first sacrificial layer on the layer to be etched and the second mask structure, wherein the first sacrificial layer exposes the first region and the first initial mask structure;
based on a first advanced process control technology, etching the first initial mask structure by taking the first sacrificial layer as a mask to form a first mask structure, wherein the first mask structure has a second width dimension and a third width deviation dimension in the first direction, the second width dimension is smaller than the first width dimension, and the third width deviation dimension is equal to the second width deviation dimension;
removing the first sacrificial layer;
forming a protective layer covering the first mask structure and the second mask structure based on a second advanced process control technology, so that the first mask structure and the protective layer form a first patterned structure, the second mask structure and the protective layer form a second patterned structure, the first patterned structure has a fourth deviation width dimension in the first direction, the second patterned structure has a fifth width deviation dimension in the first direction, and the fourth width deviation dimension and the fifth width deviation dimension are equal;
and etching the layer to be etched by taking the first patterned structure and the second patterned structure as masks, forming a plurality of first device structures in the first region, and forming a plurality of second device structures in the second region.
2. The method of forming a semiconductor structure of claim 1, wherein the fourth width bias dimension is 0; the fifth width deviation dimension is 0.
3. The method of forming a semiconductor structure as claimed in claim 1, wherein the layer to be etched further comprises a third region, the third region having a plurality of third mask structures arranged in parallel along the first direction, the third mask structures having a sixth offset dimension in the first direction.
4. The method of forming a semiconductor structure of claim 3, further comprising, after removing the first sacrificial layer and before forming the protective layer: forming a second sacrificial layer on the layer to be etched and the third mask structure, wherein the second sacrificial layer exposes the first mask structure and the second mask structure; after the protective layer is formed, the fourth width deviation dimension is equal to the sixth width deviation dimension, and the fifth width deviation dimension is equal to the sixth width deviation dimension.
5. The method of forming a semiconductor structure of claim 4, wherein the first device structure and the second device structure are formed based on a third advanced process control technique, and further comprising, during forming the first device structure and the second device structure: and etching the layer to be etched by using the third mask structure, and forming a plurality of third device structures in the third region, wherein the first device structures have seventh width deviation sizes in the first direction, the second device structures have eighth width deviation sizes in the first direction, and the third device structures have ninth width deviation sizes in the first direction.
6. The method of forming a semiconductor structure of claim 5, wherein the seventh width deviation dimension is 0; the eighth width deviation dimension is 0; the ninth width deviation dimension is 0.
7. The method of forming a semiconductor structure of claim 1, wherein the method of forming the first initial mask structure and the second mask structure comprises: forming a mask material layer on the layer to be etched; forming a patterned layer on the mask material layer, wherein the patterned layer exposes a part of the top surface of the mask material layer; and etching the mask material layer by taking the patterned layer as a mask until the top surface of the layer to be etched is exposed, so as to form the first initial mask structure and the second mask structure.
8. The method of claim 7, wherein etching the mask material layer using the patterned layer as a mask comprises: and (5) a dry etching process.
9. The method of forming a semiconductor structure of claim 7, wherein the material of the masking material layer comprises: silicon oxide or silicon nitride.
10. The method of forming a semiconductor structure of claim 1, wherein the protective layer is further located on a top surface of the layer to be etched.
11. The method of forming a semiconductor structure of claim 10, wherein the process of forming the protective layer comprises: atomic layer deposition process.
12. The method of forming a semiconductor structure of claim 1, wherein the material of the protective layer comprises: and (3) silicon oxide.
13. The method of forming a semiconductor structure of claim 1, wherein the process of etching the first initial mask structure comprises: and (5) a dry etching process.
14. The method of forming a semiconductor structure as claimed in claim 1, wherein the etching the layer to be etched using the first mask structure, the second mask structure and the protection layer as masks comprises: a dry etching process of plasma.
15. The method of forming a semiconductor structure of claim 1, wherein the material of the layer to be etched comprises: a semiconductor material; the semiconductor material includes: silicon or silicon germanium.
16. The method of forming a semiconductor structure of claim 15, wherein the first device structure and the second device structure each comprise: a fin.
CN202210113709.7A 2022-01-30 2022-01-30 Method for forming semiconductor structure Pending CN116564807A (en)

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