CN115376895A - Patterned structure and manufacturing method thereof - Google Patents
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- CN115376895A CN115376895A CN202110766182.3A CN202110766182A CN115376895A CN 115376895 A CN115376895 A CN 115376895A CN 202110766182 A CN202110766182 A CN 202110766182A CN 115376895 A CN115376895 A CN 115376895A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 138
- 238000000034 method Methods 0.000 claims abstract description 66
- 238000005530 etching Methods 0.000 claims abstract description 33
- 239000000463 material Substances 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 19
- -1 radical compound Chemical class 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 235
- 238000000059 patterning Methods 0.000 description 18
- 238000009966 trimming Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Inorganic Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
A method of fabricating a patterned structure includes the following flow. A hard mask layer and a photoresist layer are sequentially formed on the substrate in a first direction. A photoresist layer is formed on the hard mask layer. An isotropic etching process is performed on the hard mask layer and the photoresist layer in a second direction perpendicular to the first direction, such that the width of the hard mask layer in the second direction is smaller than the width of the photoresist layer in the second direction. Therefore, the thickness and shape of the damaged photoresist layer are reduced, the size of the hard mask layer is shortened, and the accurate reduction of the key size of a subsequently formed structure or an element is facilitated.
Description
Technical Field
The invention relates to a patterned structure and a method for manufacturing the same.
Background
Patterning by mask (mask) is an important and important step for the fabrication of semiconductor structures or semiconductor devices. In particular, for the semiconductor structure or semiconductor device to be formed, the size of the mask is related to the Critical Dimension (CD) of the semiconductor structure or semiconductor device.
One of the problems to be solved by those skilled in the art is to ensure that the pattern formed by photoresist (photoresist) on the mask is not damaged while ensuring the reduction of the mask size.
Disclosure of Invention
One aspect of the present invention relates to a method of fabricating a patterned structure.
According to an embodiment of the present invention, a method of fabricating a patterned structure includes the following flow. A hard mask layer and a photoresist layer are sequentially formed on the substrate in a first direction. A photoresist layer is formed on the hard mask layer. And performing an isotropic etching process on the hard mask layer and the photoresist layer in a second direction perpendicular to the first direction, so that the width of the hard mask layer in the second direction is smaller than that of the photoresist layer in the second direction.
According to an embodiment of the present invention, in the step of sequentially stacking the hard mask layer and the photoresist layer upward, the hard mask layer and the photoresist layer are sequentially stacked and formed on the underlying layer. The material of the photoresist layer is the same as the material of the bottom layer.
According to an embodiment of the present invention, the method further comprises patterning a hard mask through the photoresist layer.
In some embodiments, in the step of sequentially stacking the hard mask layer and the photoresist layer in the first direction, the hard mask layer and the photoresist layer are sequentially stacked on a bottom layer, which is a semiconductor material layer, and the semiconductor material layer is patterned by a pattern of the patterned hard mask layer after performing the isotropic etching process.
According to an embodiment of the present invention, the photoresist layer and the hard mask layer are directly etched in the first direction before the isotropic etching process is performed, so as to simultaneously reduce the width of the photoresist layer in the second direction and the width of the hard mask layer in the second direction.
According to one embodiment of the present invention, the isotropic etching process uses a radical compound.
According to an embodiment of the present invention, after performing the isotropic etching process, the photoresist layer completely covers the hard mask layer in the first direction.
According to an embodiment of the present invention, after the isotropic etching process is performed, the photoresist layer has a uniform thickness in the first direction.
One aspect of the present invention relates to a patterned structure. The photoresist layer has a uniform thickness in the first direction.
According to one embodiment of the present invention, a patterned structure includes a hard mask layer and a photoresist layer. A photoresist layer is stacked on the hard mask layer in a first direction. The hard mask layer has a width in a second direction that is smaller than a width of the photoresist layer in the second direction, and the second direction is perpendicular to the first direction. The photoresist layer completely covers the hard mask layer in the first direction.
In one or more embodiments of the present invention, the photoresist layer has a uniform thickness in the first direction.
In summary, by performing isotropic etching with high etching selectivity on the side surfaces of the stacked hard mask layer and the photoresist layer, the size of the hard mask layer can be reduced without damaging the thickness and shape of the photoresist layer, thereby facilitating the reduction of the critical dimension of the subsequently formed structure or device.
The foregoing is merely illustrative of the problems, solutions to problems, and other aspects of the present invention, and the specific details thereof are set forth in the following description and the related drawings.
Drawings
Advantages of the invention will be better understood from the following description of embodiments, taken together with the accompanying drawings. The illustrations in the figures are merely exemplary embodiments and should not be construed to limit individual embodiments or to limit the scope of the claims.
FIGS. 1-3 illustrate schematic cross-sectional views of different flow paths in a method of fabricating a structure for patterning according to one embodiment of the present invention;
FIG. 4 is a flow chart illustrating a method of fabricating a patterned structure according to one embodiment of the invention; and
fig. 5 to 7 are schematic cross-sectional views illustrating different processes in a method for manufacturing a patterned structure according to an embodiment of the present invention.
[ description of symbols ]
100 patterned Structure
120 bottom layer
140 hard mask layer
160 photoresist layer
165 effective photoresist region
200 method
210-230, flow chart
300 patterned structure
320 bottom layer
340 hard mask layer
360 photoresist layer
400 isotropic etch
D1: direction
D2: direction
T1 is thickness
T2 is thickness
T3 thickness
T4 is thickness
W1: width
W2 is width
W3 is the width
W4 is width
Detailed Description
The following detailed description of the embodiments, taken in conjunction with the accompanying drawings, is not intended to limit the scope of the invention, but rather the description of the structure is not intended to limit the order of execution, and any arrangement of components which results in a structure which achieves equivalent functionality is within the scope of the invention. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same or similar elements will be described with the same reference numerals in the following description.
Also, the terms (terms) used throughout the specification and claims have the ordinary meaning as is accorded to each term commonly employed in the art, in the context of the present invention, and in the context of specific contexts, unless otherwise indicated. Certain terms used to describe the invention are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the invention.
In this document, the terms "first", "second", etc. are used only for distinguishing elements or operation methods having the same technical terms, and are not intended to indicate a sequence or limit the present invention.
Furthermore, the terms "comprising," "including," "providing," and the like, as used herein, are intended to be open-ended and mean including but not limited to.
Further, in this document, the terms "a" and "an" may be used broadly to refer to a single or to a plurality of such terms, unless the context specifically states otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," and similar language, when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Please refer to fig. 1 to 3. Fig. 1 to 3 are schematic cross-sectional views illustrating different processes in a method of manufacturing a structure for patterning according to an embodiment of the present invention.
As shown in fig. 1, in one embodiment of the present invention, the patterned structure includes a hard mask (HD) layer 140 and a Photoresist (PR) layer 160 stacked. In the vertical first direction D1, the hard mask layer 140 and the photoresist layer 160 are sequentially stacked on the Under Layer (UL) 120.
In some embodiments, the bottom layer 120 is, for example, a layer of a semiconductor material, such as a layer comprising a silicon substrate. A hard mask layer 140 is formed over the bottom layer 120, and a photoresist layer 160 is then formed over the hard mask layer 140. Thus, the bottom layer 120 of semiconductor material may be patterned by patterning the hard mask layer 140 through the photoresist layer 160, and then patterning the hard mask layer 140.
In some embodiments, the material of the bottom layer 120 is the same as the photoresist layer 160, or other photoresist material. A hard mask layer 140 is formed over the bottom layer 120, and a photoresist layer 160 is then formed over the hard mask layer 140. Thus, the hard mask layer 140 may be patterned by the photoresist layer 160, and the bottom layer 120 of photoresist material may serve as an extension of the photoresist layer 160 to form a further photoresist pattern through the hard mask layer 140.
For purposes of simplicity of description, the same or similar dimensions, lengths, widths or thicknesses are indicated using the same or similar reference numerals. In fig. 1 to 3, the hard mask layer 140 has a thickness T1 in a first direction D1 and a width W1 in a second direction D2, wherein the second direction D2 is perpendicular to the first direction D1. Similarly, the photoresist layer 160 has a thickness T2 in the first direction D1 and a width W2 in the second direction D2. In the present invention, the first direction D1 refers to a vertical direction of stacking, the second direction D2 refers to a direction extending horizontally, and the second direction D2 is perpendicular to the first direction D1.
Fig. 2 is continued with fig. 1. In order to reduce the size of the hard mask layer 140, a portion of the photoresist layer 160 is removed, such that a portion of the hard mask layer 140 is exposed and not covered by the photoresist layer 160. The hard mask layer 140 not covered by the photoresist layer 160 can be removed.
As shown in fig. 2, a portion of the photoresist layer 160 is removed such that the width W2 of the photoresist layer 160 is reduced. Such fabrication may be referred to as a trim (trim) process of the photoresist layer 160. In some embodiments, the trimming process to reduce the width W2 of the photoresist layer 160 may be performed by plasma (plasma). Since the trimming process is performed by plasma, the thickness T2 of the photoresist layer 160 is reduced along with the reduction of the width W2. This may cause the thickness T2 of the photoresist layer 160 to deviate from the designed value.
Fig. 3 is continued with fig. 2. Based on the photoresist layer 160 with the reduced width W2 after trimming, the exposed portions of the hard mask layer 140 can be removed by an etching (etch) process. In this embodiment, the portion of the hard mask layer 140 not covered by the photoresist layer 160 is removed, and the width W1 of the hard mask layer 140 is reduced, thereby forming the patterned structure 100. Patterned structure 100 can be used to pattern underlayer 120.
In some embodiments, the etching of hard mask layer 140 may also act on photoresist layer 160. Therefore, the photoresist layer 160 is also eroded (erosion) along with the etching of the hard mask layer 140. Since the hard mask layer 140 is etched from the outside to the inside, the photoresist layer 160 is etched from the outside to the inside. Thus, the photoresist layer 160 is not uniform, but forms a convex hillock shape, which is shown by the dotted line in FIG. 3. This corresponds to the thickness of the effective photoresist region 165 of the photoresist layer 160 being different for different positions in the second direction D2. This may cause the pattern on hard mask layer 140 to deviate from the design during subsequent further processing of hard mask layer 140 through photoresist layer 160, which may result in unstable Critical Dimension (CD)/IMB for the pattern on hard mask layer 140. When patterning is to be performed on the basis of the hard mask layer 140 to form semiconductor structures/devices, it may also deviate from the pre-designed patterns and critical dimensions.
Referring to fig. 4, fig. 5 to 7 are respectively shown according to different processes shown in fig. 4. Fig. 4 shows a flow chart of a method 200 of manufacturing a patterned structure 300 according to an embodiment of the present invention. In this embodiment, the method 200 includes a flow 210 to a flow 230. Fig. 5-7 illustrate schematic cross-sectional views of different flow paths in a method 200 of fabricating a patterned structure 300 according to an embodiment of the invention.
Please refer to fig. 4 and fig. 5. In the process 210, a hard mask layer 340 and a photoresist layer 360 are sequentially stacked in a vertical first direction D1. In the present embodiment, a hard mask layer 340 and a photoresist layer 360 are sequentially formed on the bottom layer 320.
In some embodiments, the bottom layer 320 is, for example, a layer of a semiconductor material, such as a layer comprising a silicon substrate. A hard mask layer 340 is formed over the underlayer 320, and a photoresist layer 360 is then formed over the hard mask layer 340. Thus, the bottom layer 320 of semiconductor material may be patterned by patterning the hard mask layer 340 through the photoresist layer 360 and then patterning the hard mask layer 340. In some embodiments, the material of the bottom layer 320 is a photoresist material, e.g., the same as the photoresist layer 360, such that after patterning by the hard mask layer 340, the bottom layer 320 of photoresist material serves as an extension of the photoresist layer 360 to form a further photoresist pattern by the hard mask layer 340.
In fig. 5 to 7, the hard mask layer 340 has a thickness T3 in a vertical first direction D1 and a width W3 in a lateral second direction D2. The second direction D2 is perpendicular to the first direction D1. Similarly, the photoresist layer 360 has a thickness T4 in the first direction D1 and a width W4 in the second direction D2.
Please return to fig. 5. In fig. 5, the hard mask layer 340 and the photoresist layer 360 may be formed by, for example, a deposition process. By the subsequent process of the method 200, the width W3 of the hard mask layer 340 may be reduced to a predetermined thickness, which is half or less than half of the original thickness, so that the size of the hard mask layer 340 is reduced. For example, the width W3 of the hard mask layer 340 may be, for example, 40 nm when formed, and the width W3 of the hard mask layer 340 may be reduced to 20 nm by the subsequent processes of the method 200, but the invention is not limited thereto. Meanwhile, the central portion of the photoresist layer 360 covering the reduced hard mask layer 340 may not have the problem of non-uniform thickness.
Please refer to fig. 4 and fig. 6. In the optional process 220, the widths W3 and W4 of the hard mask layer 340 and the photoresist layer 360 in the second direction D2 perpendicular to the first direction D1 are reduced. It should be noted that the width W3 of the hard mask layer 340 has not been reduced to the designed final thickness. It is understood that, before reducing the hard mask layer 340 to the designed size, the outer portion of the hard mask layer 340 may be removed preliminarily to increase the speed of the overall process.
As shown in FIG. 6, it is contemplated that after the portion of the photoresist layer 360 is removed, the remaining thickness T4 may be sufficient for performing a subsequent process for patterning the hard mask layer 340.
In some embodiments, etching can be provided in the first direction D1 to directly etch the photoresist layer 360 and the hard mask layer 340, thereby reducing the width W4 of the photoresist layer 360 and the width W3 of the hard mask layer 340 in the second direction D2.
In some embodiments, the optional process 220 can be implemented by, for example, fig. 2 and 3. In detail, the photoresist layer 360 may be trimmed by plasma, and the hard mask layer 340 exposed outside may be removed by etching. Thus, although the outer portion of the photoresist layer 360 may be eroded to have a non-uniform thickness (not shown), the central portion of the photoresist layer 360 is less affected, and the thickness of the portion of the photoresist layer 360 covering the hard mask layer 340 is substantially uniform.
In some embodiments, the reduced width of the hard mask layer 340 may be set to be less than a predetermined value, so as to ensure that the etching margin of the photoresist layer 360 is small, so that the non-uniformity of the outer edge of the photoresist layer 360 with respect to the center thickness is not significant, and the thickness T4 of the photoresist layer 360 as a whole is ensured to maintain a certain degree of uniformity.
Please refer to fig. 4 and fig. 7 simultaneously. In the process 230, an isotropic etching (anisotropic etching) 400 is performed on the hard mask layer 340 and the photoresist layer 360 in the second direction D2 such that the width W3 of the hard mask layer 340 is smaller than the width W4 of the photoresist layer 360. That is, the isotropic etch 400 is performed in a lateral direction of the stacked hard mask layer 340 and photoresist layer 360.
The isotropic etch 400 is performed to ensure that the thickness T3 of the hard mask layer 340 and the thickness T4 of the photoresist layer 360 are reduced uniformly in the second direction D2. To make the width W3 of the hard mask layer 340 smaller than the width W4 of the photoresist layer 360, the etching selectivity of the isotropic etching 400 is required to be set, so that the etching rates of the isotropic etching 400 on the hard mask layer 340 and the photoresist layer 360 are different.
Compared to fig. 6, after the process 230, the width W4 of the photoresist layer 360 in fig. 7 is almost the same or only slightly reduced.
As shown in FIG. 7, after etching, the width W3 of the hard mask layer 340 is smaller than the width W4 of the photoresist layer 360. In some embodiments, the width W3 of the hard mask layer 340 is reduced by one-half compared to fig. 5, i.e., the dimension of the hard mask layer 340 in the second direction D2 is reduced by half.
Continuing with the uniform thickness photoresist layer 360 of FIG. 6, in FIG. 7, the photoresist layer 360 has a uniform thickness T4 in the first direction D1 after the lateral isotropic etching 400. Since the thickness of at least the portion of the photoresist layer 360 covering the hard mask layer 340 is uniform, as described above, the thickness of the photoresist layer 360 covering the hard mask layer 340 is also uniform in fig. 7.
Thus, when the hard mask layer 340 is subsequently patterned by the photoresist layer 360, the effective photoresist area of the photoresist layer 360 can be kept intact to ensure that the patterning of the hard mask layer 340 can achieve the designed target, since the central portion of the hard mask layer 340 covered by the photoresist layer 360 is ensured to have a uniform thickness. In other words, the edge of the hard mask layer 340 will not generate defects due to the non-uniform thickness of the photoresist layer 360 during the patterning process, and the edge effect (side effect) of the hard mask layer 340 can be improved. This enables an effective and accurate reduction of the critical dimensions of the hard mask layer 340.
For the isotropic etch 400 with a high etch selectivity, the etch selectivity of the hard mask layer 340 to the photoresist layer 360 is greater than one, so that more of the hard mask layer 340 is removed in the isotropic etch 400.
In some embodiments, the isotropic etch 400 with high etch selectivity of the process 230 can be achieved by a neutral, non-ionic (within) process. For example, in some embodiments, the high etch selectivity isotropic etch 400 of the process 230 may be tuned to provide a high etch selectivity, such as by radical chemistry. Such an etching method can form a single layer of atoms on the surface of the exfoliated material with atomic scale precision. It should be understood, however, that the present invention is not so limited to the isotropic etch 400 process used in the process 230. In some embodiments, other isotropic etching techniques that can achieve high etch selectivity are also included in the present invention. In some embodiments, the high etch selectivity isotropic etch 400 includes a neutral, non-ionic wet etch (wet) method.
In some embodiments, the process 220 and the process 230 are etching in different directions, so that different tools are used for scoring, thereby increasing the overall speed of the method 200 and saving the required time. For example, in some embodiments, in the process 220, a direct etch may be provided in the first machine in the first direction D1 to simultaneously remove the photoresist layer 360 and the hard mask layer 340 on the bottom layer 320; subsequently, the bottom layer 320, the hard mask layer 340 and the photoresist layer 360 are removed from the first machine, and the stacked bottom layer 320, hard mask layer 340 and photoresist layer 360 are placed into another second machine with their sides facing upward to perform the process 230 to perform the isotropic etching process.
Following the process 210 through the process 230 of the method 200, as shown in fig. 7, the patterned structure 300 is formed on the bottom layer 320. In the present embodiment, the patterned structure 300 includes a hard mask layer 340 and a photoresist layer 360. A photoresist layer 360 is stacked on the hard mask layer 340 in the first direction D1. The width W3 of the hard mask layer 340 in the second direction D2 is smaller than the width W4 of the photoresist layer 360 in the second direction D2, such that the photoresist layer 360 completely covers the hard mask layer 340 in the first direction D1.
In the case where the hard mask layer 340 is completely covered in the first direction D1 by the photoresist layer 360, in some embodiments, it may also be planned to use the hard mask layer 340 with a high thickness.
As shown in fig. 7, the photoresist layer 360 of the patterned structure 300 has a uniform thickness T4 in the first direction D1. In some embodiments, photoresist layer 360 has a uniform thickness at least in a central portion that covers hardmask layer 340.
In some embodiments, the bottom layer 320 is, for example, a layer of semiconductor material, and the semiconductor structure or device can be formed by performing patterning through the reduced-size hard mask layer 340, and the formed semiconductor structure or device can have critical dimensions that conform to the design. In some embodiments, patterning of the semiconductor structure, such as a wire or interconnect structure, is performed by a hard mask layer 340. In some embodiments, the patterning structure 300 can be applied to a patterning process of a conducting line or an interconnection structure of a multi-layer Mask (MLR), so that the line width of the formed conducting line or the interconnection structure can be properly and accurately reduced according to a design, and the overall critical dimension can be reduced.
In some embodiments, the bottom layer 320 may be a photoresist material, which serves as an extension of the photoresist layer 360, and is patterned by the hard mask layer 340 to serve as further photoresist.
In summary, the present invention provides a patterned structure for patterning and a method for fabricating the patterned structure. By performing isotropic etching with high etching selectivity ratio on the side surfaces of the stacked hard mask layer and the photoresist layer, the size of the hard mask layer can be shortened without damaging the thickness and shape of the photoresist layer, thereby facilitating the reduction of the critical dimension of a subsequently formed structure or element, or facilitating the subsequent formation of an extension layer of photoresist material.
Although the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of fabricating a patterned structure, comprising:
sequentially stacking a hard mask layer and a photoresist layer in a first direction, wherein the photoresist layer is formed on the hard mask layer; and
performing an isotropic etching process on the hard mask layer and the photoresist layer in a second direction perpendicular to the first direction, so that the width of the hard mask layer in the second direction is smaller than the width of the photoresist layer in the second direction.
2. The method of claim 1, wherein in the step of sequentially stacking the hard mask layer and the photoresist layer in the first direction, the hard mask layer and the photoresist layer are sequentially stacked on an underlying layer, and a material of the photoresist layer is the same as a material of the underlying layer.
3. The method of claim 1, further comprising:
the hard mask is patterned through the photoresist layer.
4. The method of claim 3, wherein in the step of sequentially stacking the hard mask layer and the photoresist layer in the first direction, the hard mask layer and the photoresist layer are sequentially stacked and formed on a bottom layer, the bottom layer being a semiconductor material layer, and the semiconductor material layer is patterned by a pattern of the patterned hard mask layer after performing the isotropic etching process.
5. The method of claim 1, wherein the photoresist layer and the hard mask layer are etched in the first direction before the isotropic etching process is performed to simultaneously reduce the width of the photoresist layer in the second direction and the width of the hard mask layer in the second direction.
6. The method of claim 1, wherein the isotropic etching process uses a radical compound.
7. The method of claim 1, wherein the photoresist layer completely covers the hard mask layer in the first direction after performing the isotropic etch process.
8. The method of claim 1, wherein the photoresist layer has a uniform thickness in the first direction after performing the isotropic etch process.
9. A patterned structure, comprising:
a hard mask layer; and
a photoresist layer stacked on the hard mask layer in a first direction, wherein a width of the hard mask layer in a second direction is smaller than a width of the photoresist layer in the second direction, the second direction is perpendicular to the first direction, and the photoresist layer completely covers the hard mask layer in the first direction.
10. The patterned structure of claim 9, wherein the photoresist layer has a uniform thickness in the first direction.
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| TW110118557A TWI833084B (en) | 2021-05-21 | 2021-05-21 | Patterning structure and method of manufacturing thereof |
| TW110118557 | 2021-05-21 |
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| CN115376895A true CN115376895A (en) | 2022-11-22 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6482726B1 (en) * | 2000-10-17 | 2002-11-19 | Advanced Micro Devices, Inc. | Control trimming of hard mask for sub-100 nanometer transistor gate |
| CN106502041A (en) * | 2015-09-03 | 2017-03-15 | 信越化学工业株式会社 | Photo blanks |
| CN109427656A (en) * | 2017-08-31 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Semiconductor device and its manufacturing method |
| US10229850B1 (en) * | 2018-01-02 | 2019-03-12 | Globalfoundries Inc. | Cut-first approach with self-alignment during line patterning |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4409362B2 (en) * | 2004-05-28 | 2010-02-03 | 富士通マイクロエレクトロニクス株式会社 | Reticle manufacturing method |
| JP2008536699A (en) * | 2005-04-14 | 2008-09-11 | プレジデント・アンド・フエローズ・オブ・ハーバード・カレツジ | Tunable solubility in sacrificial layers for microfabrication |
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- 2021-05-21 TW TW110118557A patent/TWI833084B/en active
- 2021-07-07 CN CN202110766182.3A patent/CN115376895A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6482726B1 (en) * | 2000-10-17 | 2002-11-19 | Advanced Micro Devices, Inc. | Control trimming of hard mask for sub-100 nanometer transistor gate |
| CN106502041A (en) * | 2015-09-03 | 2017-03-15 | 信越化学工业株式会社 | Photo blanks |
| CN109427656A (en) * | 2017-08-31 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Semiconductor device and its manufacturing method |
| US10229850B1 (en) * | 2018-01-02 | 2019-03-12 | Globalfoundries Inc. | Cut-first approach with self-alignment during line patterning |
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| TW202246890A (en) | 2022-12-01 |
| TWI833084B (en) | 2024-02-21 |
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