TWI314349B - Method for forming spacers with different widths - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of forming a spacer, and more particularly to a method of forming a plurality of width spacers. . Prior Art An integral part of the gap-wall semiconductor process, for example, in order to handle short-channel effects in the gate structure, requires the formation of a spacer structure. In addition to the interpole structure, traces of the spacers are also common in different parts of various semiconductors. For example, in the Trench, there is a case where spacers are used in order to satisfy electrical or physical properties. = the width of the gap will affect the nature of its creation, and for the fine half

In the industry, it is very important to be able to make the gaps of the required specifications. A IT With the advancement of electronic technology, the number of circuit components that can be stored in a wafer is increasing. As its applications become more diverse and diverse, the internal structure of the wafer is becoming more complex. For example, in system-integrated wafers (soc) or other common applications, it is often necessary to use circuit components of different nature in different regions, and when these circuit components often require gaps of different widths: A conventional practice is to create gaps in separate regions. However, the problem with this is that the repeated actions require multiple reticle counts, and at the same time, the area tends to have etched contamination of the doped regions. Therefore, in today's and visible future, due to the need for multiple width spacers

1314349 _ Case No. 92101177_ Year of the month 曰 Amendment _ V. Invention description (2) In the case of an increase, if it is possible to find a method that is effective and flexible and can protect the non-working area, it will become increasingly The complex semiconductor industry has made a significant contribution. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an efficient method of forming a plurality of width gap walls. A preferred embodiment in accordance with the present invention includes the following steps. First, a substrate is provided which has a plurality of structures on the sides thereof which need to form spacers which are distributed in a plurality of regions. In other words, structures requiring different width spacers are located in different work areas. Then, the multilayer etching is selected to be deposited on a substrate in a stacked manner with different dielectric layers, wherein the adjacent dielectric layers have different cost-selection ratios, and the material of the dielectric layer is used as a spacer. material. Then, one or more lithography etching operations are selectively used based on different spacer width requirements. The so-called lithography etching operation herein includes the following steps. The first step is to form a patterned photoresist on the dielectric layer to expose a number of working areas. The second step is to selectively etch in the exposed exposed regions, e.g., using different etch selectivity ratios of adjacent dielectric layers to achieve the desired number of dielectric layers. The third step is to remove the photoresist for the next steps. The dielectric layer of the different work areas retains a different number of layers or shapes by at least one lithography etching operation. Finally, the unnecessary dielectric layer material is removed by an anisotropic etch, so that the spacers of different working areas have different widths.

Page 9 1314349 _ Case No. 92101177_Yearly Revision _ V. Invention Description (3) Therefore, the present invention not only provides an easy-to-plan fabrication method, but also can be used for a partial area of an entire wafer or wafer. , with considerable flexibility. In addition, the pre-formed dielectric layer can also serve as a protection to the substrate and its structure to avoid unwanted contamination during the formation of the spacers. Therefore, the present invention does provide an effective method to solve the current problem, and thus contributes significantly to the increasingly complex semiconductor manufacturing. Embodiments The present invention provides a method of forming a plurality of spacer widths, and a specific embodiment will be provided below to illustrate the method. First, please refer to Fig. 1, which is a schematic diagram of an integrated circuit chip 1 。. The chip 10 is composed of a computing module 1 , a control module 1 2 , a first memory 1 3 , a second memory 14 , and a communication module 15 . The present invention is a system single-chip (SoC), which is intended to be illustrative only and not to limit the scope of the invention. The inter-module circuits of the chip 10 tend to have different characteristics. For example, even if it is also a CMOS logic gate, the width of the required spacers will be different because of its use as a communication, memory, or calculation. There are different requirements for achieving circuit components of different characteristics. Therefore, during the manufacture of the wafer 10, the need for spacers of different widths is produced for circuit components in different regions. In this example, since the circuit components need to have spacers having different widths, we divide the wafer 1 into a calculation module 11, a control module 1, a first memory 1, and a second memory.

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V. Description of invention 1 4, and the domain division method only, in the case of different implementations, please apply. The first structure is distributed in the super-implementation package. Emperor No. 92101177 (4) Communication module 1 5 several working areas. For ease of explanation... 丄; industry, district = industry t, even in the communication module may need most to refer to Figure 2, this flow chart illustrates the method of making spacers, providing a substrate (step 202), The side walls of these substrates having these structures need to form spacers, and these households pass through more than two working areas. For example, these $^ types include gates, trenches, and the like. Next, at least two or more dielectric layers (steps 204) are formed on the substrate, and the dielectric layers are stacked one above another on the substrate. These dielectric layers provide materials for forming the spacers, and examples of the method of forming these dielectric layers include conventional deposition methods of semiconductor processes. Adjacent ones of these dielectric layers have different etching selectivity ratios for use as conditions for controlling subsequent selective etching. Next, according to the final spacer structure to be formed, (step 2〇6) lithography is selected. Etching operation (step 208) or selective etching of the dielectric layer directly (step 2 1 0), the selective etching described herein may be selected as dry, engraved, bath, etc. To the touch or non-isotropic etch, and using the etch selectivity ratio of the dielectric layer adjacent to the two layers to form different gap widths. Such etching without etching using a different dielectric layer by etching is also referred to as self a 1 igned etching β. The selection of the lithography etching operation (step 208) includes the following steps. . First, a patterned aperture is formed on the aforementioned dielectric layer (Patterned photo)

Page 11 1314349 No. 1 92101177 Λ.Ά 修正 Amendment 5. Invention Description (5) Two esist) </ br> to expose a part of the work area (steps 2〇82). Then, for the exposed working area portion, the dielectric layer is selectively etched (step 2084), and the selective etching may be performed by dry etching, wet etching, isotropic etching or non-isotropic etching, and utilized. The etching selectivity ratio of the dielectric layer adjacent to the two layers is different to achieve the need of different spacer widths 1 and then: removal of the photoresist is performed (step 2086). The 余 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个 整个For example, one or more selective etchings 21 进行 may be performed after forming at least = dielectric 204, and then the parent may enter at least one lithography etching operation 208 and one or more selective etchings 210'. The methods are all within the scope of the present invention, and the formation of the spacers is completed (step 21 4). Wherein the features of the invention include at least the following points. First, all the required dielectric layers are formed. If it is desired to form N kinds of walls, it is necessary to form at least N layers of dielectric layers. In the process of forming the gap in the gap area, at least one more time is taken in the work. By performing the lithography etching operation in different working areas = selective etching of etching, the gap walls of different working areas have different or a plurality of layers of dielectric layers, thereby achieving different widths in different working areas. . Gap Walls In order to more clearly illustrate the concepts of the present invention, the methods of the present invention are further illustrated below. Fine example First, please refer to Figure 3 (a) to Figure 3 (h), which illustrate how and how

Case No. 92101177 1314349

V. INSTRUCTION OF THE INVENTION (6) _____ An example in which a dielectric layer is formed first and then selectively passed through a micro or shaped spacer. The surface is etched to achieve different widths in the first pattern on the substrate 32 in Fig. 3(a), and in the second working area 312 ==2 has = f^gap, first on the substrate 32. Three dielectric layers are deposited "B, 332." to have different etch selectivity ratios, and dielectric layer 332 and dielectric layer 333 have different etch selectivity ratios. A photoresist 341 is formed over the dielectric layers 331, 332, and 333. Then, as shown in Fig. 3(b), the first working region 311 exposed by the photoresist 341 is subjected to an isotropic or non-isotropic engraving to remove the dielectric layer 333. Since the electrical layer 333 and the dielectric layer 332 have different etching selectivity ratios, the dielectric layer 333 can be removed. As for the first working area 312, since it is protected by the photoresist 341, it is not affected by the etching. Then, the dielectric layer 33 2 of the first work area 311 is continuously subjected to the process of non-isotropic processing, and the structure shown in Fig. 3(c) can be obtained. At this time, the photoresist 341 of the second working area 31 2 is removed, and the photoresist 342 is added to the first working area 311 by a patterning process, so that the structure of the third figure (d) can be obtained. Then, the second non-isotropic etching of the second working region 3丨2 exposed by the photoresist 342 can sequentially obtain the structures of FIGS. 3(e) and 3(f). Next, the photoresist 342 is removed to obtain the structure of Fig. 3(g). Finally, an anisotropic etch is performed on all the working regions at the end to remove all of the dielectric layers which are not the spacer walls, and the structure of Fig. 3(h) is obtained. After the above procedure, we obtain that the gate structure 321 of the first work area 311 has a different spacer width than the gate structure 322 of the second work area 31 2 . This ^

1314349 _ Case No. 92101177 _ dd/mm/yyday Revision _ V. INSTRUCTIONS (7) The difference in the width of the gap is determined by the number of layers and the thickness of the material constituting the dielectric layer. It must be pointed out that in the process of forming the entire spacer, since the non-isotropic etching is uniformly performed to remove the unnecessary dielectric layer material, the substrate 32 is directly subjected to the dielectric layer 3 3 1 Protected by 3 3 2, 3 3 3, so that the doped regions under the gate structures 3 2 1 , 3 2 2 are not contaminated by multiple etchings. The above is an example of forming two width-shaped spacers in two working areas by using three dielectric layers. Of course, those skilled in the art can use this description to expand into any number of dielectric layers of two or more layers to form. Two or more spacers of any width shape of any number of two or more working areas. Another example of how to form spacers of three widths will be described below. For this example, please refer to the structural diagrams of each stage in Figures 4(a) to 4(i). In Fig. 4(a), the substrate 42 has a first working area 411, a second working area 412, and a third working area 413, in which the gate structures 421, 422 and 423 are respectively provided. First, four dielectric layers 431, 432, 433, 434 are formed on the substrate 42, wherein the adjacent two layers of the four dielectric layers 431, 432, 433, 43 4 have different etching selectivity ratios. Then, light $441 is formed over the four dielectric layers 431, 432, 433, 434 to expose the first working area 411 as shown in Fig. 4(a). Next, the non-isotropic etching is performed twice on the exposed first working region 411, and the structures shown in Figs. 4(b) and 4(c) are sequentially obtained. Next, an isotropic etching is performed to remove the substance of the dielectric layer 434 of the exposed first working region 411 to obtain the structure shown in Fig. 4(d). Then, the photoresist 441 of the second working area 412 and the third working area 41 3 is removed, and then a photoresist 442 is formed on the first working area 411 to expose

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曰 V. Invention Description (8) The second work area 彳 and the third work area 413 of the second work area 4丨2. Next, the material is removed by exposure to remove the exposed area 2 and the second working area 41 3 and then we obtain the material of the electrical layer 434. The second work area 41 2 and the third work area which have been repaired by these steps are used to obtain the structure shown in Fig. 4 (f). Then, after the anisotropic etching of the structure 413 shown in (e) is further performed, the photoresist 442 in the second working region 4? of FIG. 4 is removed and formed on the first working region 411, Q^^. The photoresist 443 is exposed to the third working area 413' and performs a 笪&amp;, tf or non-isotropic reciprocation to obtain the symmetry shown in Fig. 4(g). The structure of Fig. 4 (h) is obtained by connecting ‘ walking* resistance 443’. In the 'structure' gate structure of FIG. 4(h), 422 and 423 respectively cover different shapes of the dielectric layer H' for an anisotropic etching to remove the unnecessary dielectric layer material 'to this' Figure 4 (i) is obtained. In Fig. 4(i), we can find that the gate structures 421, 422, and 423 have spacers of different shapes and widths, thereby satisfying the different width spacer characteristics required for the gate structures 421, 422, and 423. Next, please refer to Figure 5, which illustrates the different shapes of the gap. Although the above two examples are similar to the shape of the spacer 51 in Fig. 5, if there is a need for design, the above-mentioned technique can be utilized to form the shape of the spacer 52. In addition, please refer to Fig. 6, which illustrates an example in which the present invention is applicable to a trench. Unlike the aforementioned gates, sometimes the structure of the trench shape also requires spacers. At this point, we can use the technique of the present invention to form spacers of different widths or shapes in different work areas.

Page 15 1314349 - - Case No. "77___ 主^^~ - V. Description of the invention (9) In addition to 'the above two applications in the gate and the ditch', other structures requiring a spacer may also be applied to the present invention. Techniques, for example, 'the need to create a structure requiring a spacer after a flattening process, such as wires or trenches' can also be applied to the technique of the present invention to form spacers of different widths or shapes in different work areas. The present invention knows that the application of the present invention has at least the following advantages. First, since the substrate is protected by the dielectric layer during the fabrication of the spacer, it is possible to avoid the contamination β caused by the process, such as etching. In this way, the method can avoid contamination of the replacement region under the gate of different working areas. Secondly, the present invention deposits the dielectric layer as the spacer material all at once, and then transmits selective lithography. In the case of a combination of different dielectric layer shapes to obtain different spacer shapes, this is easy for the designer of the circuit to plan, and therefore The present invention also has important utility for increasingly complex circuits. Accordingly, the present invention does provide an effective method for forming spacers of different widths or shapes in different work areas, and thus the present invention is required for future semiconductor processes. It is difficult to say that there is no significant contribution to the more complicated circuit accumulation. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit the invention to anyone skilled in the art without departing from the invention. The spirit and scope of the invention may be varied and modified, and the scope of the invention is defined by the scope of the appended claims.

Page 16 1314349 Case No. 92101177 曰Revision Diagram Simple Description of the Drawings FIG. 1 illustrates a schematic diagram of an integrated circuit wafer; FIG. 2 illustrates a flow chart of the embodiment method; FIG. 3 (a) to (h) Examples of forming two types of width spacers are shown in Figs. 4(a) to (i) for exemplifying the example of forming three kinds of width spacers. Fig. 5 illustrates an example of different gap wall shapes; and Fig. 6 illustrates another structure spacer application. example. Description of the drawings: 10 chip 1 2 control module 1 4 second memory 202 to 214 flow chart step 3 11 first working area 3 2 substrate 3 2 1 gate structure 3 3 1 dielectric layer 3 3 3 Dielectric layer 342 photoresist 4 1 2 second working area 4 2 1 gate structure 423 gate structure 11 computing module 1 3 first memory 1 5 communication module 2082~2086 flow chart step 312 second working area 42 Substrate 3 2 2 gate structure 3 3 2 dielectric layer 341 photoresist 411 first working region 413 third working region 422 gate structure 43 1 dielectric layer

1314349 Case No. 92101177 Issued Correction Schematic description 432 dielectric layer 434 dielectric layer 442 photoresist 5 1 spacer 4 3 3 dielectric layer 441 photoresist 443 photoresist 5 2 spacer

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Claims (1)

1314349 _ Case No. 92101177_年月日日 Revision _ VI. Patent Application Range 1. A method for forming a plurality of width spacers, the method comprising: forming a first dielectric layer on a plurality of structures, wherein the structures are distributed And forming at least a first working area and a second working area on a substrate; forming a second dielectric layer on the plurality of structures, the material of the second dielectric layer is different from the material of the first dielectric layer Forming a first photoresist on the second working region; selectively etching the second dielectric layer on the first working region to completely remove the exposed second dielectric layer; Forming the first dielectric layer on the sidewall of the plurality of structures in the first working region to form a first spacer; removing the first photoresist; forming a second photoresist on the first And etching the second dielectric layer and the first dielectric layer in the second working area to form a second spacer on the sidewall of the plurality of structures in the second working area, thereby The width of the second spacers is large The width of the plurality of first spacers. 2. The method of claim 1, wherein at least one semiconductor process is included between the step of forming the first photoresist and the second photoresist. 3. The method of claim 1, wherein the structures comprise a gate structure. Page 19 1314349 _ Case No. 92101177 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 5. The method of claim 1, wherein the first spacers and the second spacers are different in number of dielectric layers, such that the first spacers and the second gaps The width of the wall is different. 6. A method of forming a plurality of width spacers, the method comprising: forming a first dielectric layer on a plurality of structures, wherein the structures are distributed on at least a first work area and at least a second on a substrate a working region; forming a second dielectric layer on the plurality of structures, the material of the second dielectric layer is different from the material of the first dielectric layer; forming a third dielectric layer on the plurality of structures, the first The material of the three dielectric layers is different from the material of the second dielectric layer; forming a first photoresist on a second working region; selectively etching the third dielectric layer in the first working region to completely Removing the exposed third dielectric layer; the second dielectric layer exposed by the non-isotropic etching is formed on the sidewalls of the first dielectric layer on the structures in the first working region a first spacer; removing the first photoresist; forming a second photoresist on the first working area; Page 20 1314349 _ Case No. 92101177_年月日日__ Sixth, the patent application scope sequentially etches the third dielectric layer and the second dielectric layer of the second working area, in the second working area Forming a second spacer on the sidewall of the plurality of structures; removing the second photoresist; and etching the exposed first dielectric layer to simultaneously serve the first dielectric on the structures of the first operating region Forming a third spacer on the sidewall of the electrical layer together with the first spacers, and forming a fourth spacer along with the second spacers on sidewalls of the structures of the second working region, thereby The width of the fourth spacers is greater than the width of the third spacers. 7. The method of claim 6, wherein at least one semiconductor process is included between the step of forming the first photoresist and the second photoresist. 8. The method of claim 6, wherein the structures comprise a gate structure. 9. The method of claim 6, wherein the structures comprise a trench structure. A semiconductor structure comprising: a substrate comprising a first work area and a second work area; a plurality of circuit structures located in the first work area and the second work area Page 21 1314349 _ case number 92101177_Yearly revision _ six, the patent application scope field; a first dielectric layer, located in the first working area and the second working area of the circuit structure side wall; The second dielectric layer is located on the sidewall of the circuit structure of the second working area, wherein the material of the second dielectric layer is different from the material of the first dielectric layer, and the first gap of the first working area is The wall includes the first dielectric layer, and the second spacer of the second working area includes the first dielectric layer and the second dielectric layer, wherein the second spacer has a width greater than the first spacer width. 11. The semiconductor structure of claim 10, further comprising a third dielectric layer located on sidewalls of the circuit structures of the first work area and the second work area, wherein the first operation The first spacer of the region includes the first dielectric layer and the third dielectric layer, and the second spacer of the second working region includes the first dielectric layer, the second dielectric layer, and the The third dielectric layer is such that the width of the second spacer is greater than the width of the first spacer. 1 2. The semiconductor structure of claim 10, further comprising a third dielectric layer on a sidewall of the circuit structures in the second operating region, wherein the first operating region a spacer includes the first dielectric layer, and the second spacer of the second working region includes the first dielectric layer, the second dielectric layer, and the third dielectric layer, thereby enabling the second gap Page 22 1314349 _ Case No. 92101177_年月曰 修正 Amendment _ VI. Patent Application Scope The width of the wall is greater than the width of the first spacer. The semiconductor structure of claim 1 or claim 2, wherein the material of the third dielectric layer is different from the material of the second dielectric layer. 1 4. The semiconductor structure of claim 10, wherein the circuit structures comprise a gate structure. The semiconductor structure of claim 10, wherein the circuit structure comprises a trench structure. Page 23