CN111799150A

CN111799150A - Semiconductor structure and preparation method thereof

Info

Publication number: CN111799150A
Application number: CN201910276119.4A
Authority: CN
Inventors: 张德鑫
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-04-08
Filing date: 2019-04-08
Publication date: 2020-10-20
Anticipated expiration: 2039-04-08
Also published as: CN111799150B

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a first trench on a substrate; cleaning and filling the first trenches to form active regions isolated from each other by the first trenches; and forming a mask layer on the surface of the active area, forming an opening on the mask layer, etching the active area along the opening to form a second groove, cleaning and filling the second groove to form the semiconductor structure. The preparation method can form a semiconductor structure with smaller critical dimension of an active region and good structural stability, simplifies the substrate structure and the process, and is suitable for the preparation of semiconductor structures in multiple fields.

Description

Semiconductor structure and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.

Background

The active region structure is one of the most basic structures in a semiconductor device and is prepared by forming trenches in a semiconductor substrate through a one-step photolithography process and defining active regions between the trenches. However, as the requirements of semiconductor devices are higher and higher, the distance between trenches is narrower and narrower, and the problem of structure collapse is easily caused when wet cleaning is performed on the trenches during the trench formation process, which affects not only the subsequent preparation process but also the performance of the whole active region.

It is to be noted that the information invented in the above background section is only for enhancing the understanding of the background of the present invention, and therefore, may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a semiconductor structure and a preparation method thereof, and solves the problem that the structure is easy to collapse in the preparation process of an active region.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor structure, comprising:

providing a substrate;

forming a first groove on the substrate, cleaning the first groove, filling the first groove, and forming active regions which are isolated by the first groove;

forming a mask layer on the surface of the active area;

forming an opening in the mask layer, etching the active region along the opening, forming a second groove in the active region, cleaning the second groove, filling the second groove, and forming the semiconductor structure; and the distance between the first groove and the second groove is the critical dimension of the active region of the semiconductor structure.

In an exemplary embodiment of the present invention, each of the first grooves and the second grooves includes a plurality of grooves, and the plurality of second grooves and the plurality of first grooves are alternately arranged at intervals.

In one exemplary embodiment of the present invention, forming a first trench on the substrate includes:

forming a mask layer on the surface of the substrate;

and forming an opening on the mask layer, etching the substrate along the opening, and forming the first groove in the substrate.

In an exemplary embodiment of the present invention, the mask layer includes a photoresist.

In one exemplary embodiment of the present invention, the mask layer further includes a hard mask layer including one or both of a carbide layer and a nitride layer.

In an exemplary embodiment of the present invention, a process of forming an opening in the mask layer is as follows:

exposing and developing the mask layer in sequence to form a pattern;

and adopting resolution enhancement photoetching to assist chemical shrinkage to perform shrinkage treatment on the pattern to form the opening.

In one exemplary embodiment of the present invention, the substrate includes a silicon wafer and a protective layer covering the silicon wafer.

In one exemplary embodiment of the present invention, the protective layer includes an oxide layer and a nitride layer covering the oxide layer.

In one exemplary embodiment of the present invention, filling the first trench or the second trench includes:

and filling oxide into the first trench or the second trench.

In an exemplary embodiment of the present invention, the cleaning of the first trench and the second trench employs a wet cleaning process.

According to another aspect of the present invention, there is provided a semiconductor structure prepared by any one of the methods described above.

When the semiconductor structure is prepared, first grooves are formed on a substrate, the first grooves are filled after being cleaned, second grooves which are alternately arranged among the first grooves at intervals are formed, and the semiconductor structure is formed after cleaning and filling of spacers. On one hand, the distance between the grooves formed in each step of the preparation method is larger, the active region structure is stable and is not easy to collapse during cleaning, and the active region structure with narrower line width and good structure stability can be formed. It also allows the cleaning step to accommodate narrower and narrower line widths without line width limitations. On the other hand, the preparation method enables the photoetching process to process the semiconductor structure with higher precision, and avoids the limitation of the process on the precision.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

FIG. 1 is a schematic diagram of a semiconductor structure;

FIG. 2 is a schematic diagram of a semiconductor structure collapse;

FIG. 3 is a schematic diagram of a wet clean collapse of a semiconductor structure;

FIG. 4 is a flow chart of a method for fabricating a semiconductor structure according to the present invention;

FIG. 5 is a schematic diagram of a structure for forming a hard mask layer on a substrate;

FIG. 6 is a schematic diagram of a structure for patterning a photoresist on a hard mask layer;

FIG. 7 is a schematic structural diagram of etching a first trench in a substrate;

FIG. 8 is a schematic structural view of filling oxide in the first trench;

FIG. 9 is a schematic view of a planarization process for the first trench;

FIG. 10 is a schematic diagram of a structure for forming a hard mask layer on an active region;

FIG. 11 is a schematic diagram of a structure for patterning a photoresist on a hard mask layer;

FIG. 12 is a schematic structural view of etching a second trench on the active region;

FIG. 13 is a schematic structural view of filling oxide in the second trench;

FIG. 14 is a schematic view of an opening structure for an original photoresist;

FIG. 15 is a schematic view of the structure of the opening after chemical shrinkage.

In the figure: 1. a silicon wafer; 2. an oxide layer; 3. a first nitride layer; 4. a carbonization zone; 5. a second nitride layer; 6. photoresist; 7. a first trench; 8. a second trench; 9. a separator; 10. a chemical shrinking agent.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

The semiconductor structure is generally fabricated by etching a desired trench in a substrate by photolithography, and filling the trench with a spacer to form a trench isolation region and an active region, as shown in fig. 1-2. In the above manufacturing process, contaminants such as residues and particles are left on the wafer surface, and therefore, a cleaning step is required to remove the contaminants on the wafer surface. For example, wet cleaning is often used to clean photoresist residues and polymers on the wafer surface. However, when the wafer after wet cleaning is dried, the pattern is affected by surface tension, and a defect of pattern damage often occurs, as shown in fig. 3. As the line width is reduced, the probability of pattern damage increases. As semiconductor processes are developed in the precision direction, the critical dimension of the active region becomes smaller and smaller, and the active region needs to be correspondingly reduced to realize the continuous reduction of the device size. This also puts higher demands on the wet cleaning process, the line width of the wet cleaning becomes narrower, and the problem of pattern collapse becomes more prominent.

The embodiment provides a method for manufacturing a semiconductor structure, which is particularly suitable for manufacturing a semiconductor structure with a small groove gap. The method has wide application field, can be used for preparing structures required by various purposes of semiconductors, such as an active region and an isolation region structure for manufacturing a semiconductor device, or a capacitor hole with high depth-to-width ratio, and the like, and is not listed here, and the active region and the isolation region structure for preparing the semiconductor device are taken as an example for explanation.

As shown in fig. 4, the method for manufacturing a semiconductor structure of this embodiment includes:

step S100, a substrate is provided.

Step S200, forming a first groove on the substrate, cleaning the first groove, filling the first groove, and forming active regions which are isolated by the first groove;

step S300, forming a mask layer on the surface of the active area;

step S400, forming an opening in the mask layer, etching an active region along the opening, and forming a second groove in the active region; cleaning the second groove, and filling the second groove to form a semiconductor structure; the distance between the first trench and the second trench is the critical dimension of the active region of the semiconductor structure.

When the adjacent isolation grooves are closer to each other, all the grooves are formed in batches by the method. The grooves formed in the first step are large in space and stable in structure, so that the structure between the adjacent first grooves is not easy to collapse in the first cleaning process. The groove formed in the first step is filled with the spacer, so that the whole substrate is of an integral structure without the groove, the structure is stable, and the stability of the base can be ensured when the groove formed in the second step is formed. Meanwhile, the second grooves are located between the two first grooves, the distance between every two adjacent second grooves is large, and the structure is stable and not prone to collapse in the second cleaning process. Therefore, the structure of each step can be ensured to be stable in the process of forming the complete semiconductor structure, and the active region with stable structure and good performance is finally formed. Therefore, the most important effect of the method of this embodiment is that when the wet cleaning is adopted in the cleaning method, the wet cleaning can adapt to the smaller and smaller line width of the active region, the limitation of the line width is avoided, and the application range is greatly expanded. In addition, the method for forming the active regions in batches can prepare the semiconductor active region with narrower line width so as to adapt to continuously-miniaturized device sizes and avoid the limitation of the photoetching technology. Meanwhile, the mode can ensure that the structure of the active region is stable in the cleaning process, so that excessive dielectric layers do not need to be prepared on the substrate, the preparation process is simplified, and raw materials are saved.

The preparation method of the embodiment can well give consideration to the cleaning process when preparing the active region and the isolation region structure, prepare the active region structure with narrow line width, form the active region structure with good structural stability, and improve the problem of structural stability of the active region in the cleaning process.

The following describes the method for fabricating the semiconductor structure of this embodiment in detail:

in this embodiment, the first trenches and the second trenches both include a plurality of second trenches, and the plurality of second trenches and the plurality of first trenches are alternately arranged at intervals, so that a semiconductor structure having a layout of a plurality of active regions and isolation regions can be manufactured. In addition, the mode of etching the groove in batches enables the key size of the active region to achieve higher precision, and a more ideal device is prepared. Moreover, when the number of the isolation trenches is large, the substrate is easily damaged in a traditional one-step etching mode, and the damage condition of the substrate is greatly reduced by a batch etching method, so that the performance loss is avoided.

In the present embodiment, referring to fig. 5, the substrate material of step S100 includes a silicon wafer 1 and a protective layer covering the silicon wafer. The protective layer comprises an oxide layer 2 and a first nitride layer 3 in sequence. An oxide layer 2 grows on the silicon wafer 1, so that doping can be shielded, scratches can be prevented, and stress between an upper layer structure and silicon can be reduced. The material of the oxide layer 2 may be silicon dioxide or the like. The first nitride layer 3 deposited on the oxide layer 2 serves both as a robust masking material to help protect the active region during subsequent growth of the spacers 9 into the isolation trenches and as a barrier material for polishing during polish planarization. The material of the first nitride layer 3 may be silicon nitride.

In other embodiments, the substrate material may also be sapphire, silicon carbide, etc., and the protective layer may also comprise silicon dioxide, silicon nitride, etc.

In this embodiment, the method for forming the first trench on the substrate may also adopt a photolithography process, which specifically includes:

step S210, forming a mask layer on the surface of the substrate;

step S220 is to pattern the mask layer, form an opening on the mask layer, etch the substrate along the opening, and form a first trench in the substrate.

Specifically, the mask layer may be a photoresist, which is first coated on a protective layer of the substrate. And exposing and developing the photoresist in sequence to form a first groove pattern on the photoresist. The photoresist may be a positive or negative photoresist. The substrate is then etched using the first trench pattern on the photoresist, transferring the pattern of the photoresist to the substrate. The etching may be dry etching or wet etching, such as plasma thin film etching or solution etching. And after the etching is finished, removing the photoresist to obtain a first groove. The removing method can be wet removing or dry removing, such as dissolving the photoresist with organic solvent or directly stripping the photoresist.

In this embodiment, in order to make the pattern structure of the mask layer more stable and ensure higher substrate etching precision, referring to fig. 5-6, the two-step photolithography process may first form a hard mask layer, then coat the photoresist 6 on the hard mask layer, and perform an exposure, development and etching process. The hard mask layer is firmer, so that the pattern structure formed on the hard mask is more stable, the substrate is firm when the first groove and the second groove are etched, and an ideal groove structure can be obtained.

The hard mask layer may include one or both of the carbide layer 4 and the nitride layer 5. For example, referring to fig. 5, forming a hard mask layer on a substrate may include: a carbonized layer 4 is formed on the substrate, and a second nitride layer 5 is formed on the carbonized layer 4. The carbonized layer 4 may be silicon carbide, etc., the second nitride layer 5 may be silicon nitride, etc., the formation process may be growth, deposition, sputtering, etc., the two layers have stable structures and are easy to develop, the pattern on the photoresist 6 can be accurately transferred onto the structure layer, and then transferred onto the substrate, and the removal is convenient at the same time, and the pattern can be conveniently removed by a dry method (such as stripping) or a wet method (such as solution etching), so as to obtain a first trench, referring to fig. 7.

In the present embodiment, referring to fig. 8, step S200 fills the first trench formed with a spacer 9 for the purpose of forming an isolation structure. The spacers 9 may be an oxide or the like, for example an oxide may be formed in the first trenches 7 by means of growth, such thermally grown oxide passivates the silicon surface and the deposited oxide of the shallow trench fill may be isolated from the silicon. The oxide can also be used as an effective barrier layer to avoid the generation of side wall leakage current in the device. Other methods of forming other fillers are of course possible. After growing oxide in the first trench 7, referring to fig. 9, planarization may be performed by chemical mechanical polishing, followed by a second photolithography process.

In an embodiment, the second trench 8 may also be manufactured by the above-mentioned photolithography process, which specifically includes: referring to fig. 10, a hard mask layer is first formed on the active region, and then, referring to fig. 11, a photoresist 6 is coated again on the hard mask. The photoresist 6 is then sequentially exposed and developed to form an opening in the photoresist 6. And etching the active region along the opening, and after the etching is finished, removing the photoresist 6 and the hard mask layer to obtain second grooves, wherein the positions of the second grooves and the first grooves are alternately arranged at intervals, referring to fig. 12. The structure of the hard mask layer, the material of the hard mask layer, the type of the photoresist, the etching method, the removal method, and the like may be the same as or different from the photolithography process of the first trench, and the present invention does not specially limit the structure.

Referring to fig. 13, step S400 fills the spacers 9 for isolation in each second trench 8 to form a semiconductor structure, thereby completing the fabrication of the shallow trench isolation structure. The type and filling method of the second trench spacer 9 may be the same as or different from the first trench filler, and the present invention is not limited thereto.

In the present embodiment, on the basis of ensuring the structural stability, in order to meet the requirement of semiconductor scaling, the opening width of the mask layer may be reduced by resolution enhancement lithography assisted chemical shrink technology (RELACS assisted technology). The resolution enhancement photoetching auxiliary chemical shrinkage reagent comprises water-soluble macromolecules and a cross-linking agent, and can generate cross-linking reaction with the surface of the photoresist to form a water-insoluble cross-linking layer, so that the photoresist forms a new side wall, and the opening width is reduced, namely the width of an active region is reduced. Accordingly, referring to fig. 14-15, step S220 may include:

step S221, forming a mask layer on the first trench, and exposing and developing the mask layer in sequence to form a pattern;

step S222, adopting resolution enhancement photoetching to assist chemical shrinkage to perform shrinkage processing on the pattern, and forming an opening.

Wherein, the specific process of the shrinkage treatment is as follows: coating a resolution enhancement photoetching auxiliary chemical shrinking agent 10 on the side wall of the developed photoresist 6, and carrying out mixed baking on the photoresist 6 to ensure that the chemical shrinking agent 10 forms a water-insoluble cross-linked layer on the surface of the photoresist 6 to form a new side wall. And (4) punching and removing the chemical shrinking agent which is not linked, so as to obtain the groove pattern with the width reduced from a to b.

Step S223, etching the substrate along the reduced width opening, and removing the photoresist 6 and the hard mask layer to obtain a first trench 7 with a narrower width. And then subsequent cleaning and filling of the spacers are performed.

Accordingly, in step S400, when patterning the second trench mask layer, the opening width may also be reduced by using a resolution enhanced lithography assisted chemical shrink technique (RELACS assisted technique) to form the second trench 8 with a narrower width.

In this embodiment, if all trenches are required to be arranged at equal intervals in the active region structure to be finally prepared, as shown in fig. 7-13, the first trenches 7 and the second trenches 8 are required to be alternately arranged at equal intervals, and an interval Y between two adjacent first trenches 7 (i.e., a sum of a width of one active region and a width of one first trench) is 2 times an interval X between all trenches to be finally formed (i.e., a sum of a width of one active region and a width of one second trench). When forming the second trench 8, the first trench 7 is filled with the spacer, and the substrate structure is stable. Meanwhile, the distance between two adjacent second grooves 8 is also Y, so that the structure is stable when the second grooves 8 are cleaned, and collapse is not easy to occur. In addition, if Y is understood as the limit of the traditional method for processing the active area, the method of the invention for processing the active area by times can improve the limit of the processing of the active area by times to X, so that the processing method of the invention can prepare the active area structure with smaller critical dimension. According to the sub-processing method of the embodiment, the size of Y can reach 60-100nm, the size of X can reach 30-50nm, and the line width of the isolation trench can be selected according to the actual preset size of the active region, so that the micro-shrinkage of the key size of the active region is realized, and the precision of the structure of the active region is greatly improved. It will be understood by those skilled in the art that all trenches in the semiconductor structure may also be arranged at unequal intervals, and thus the second trench 8 may not be located at the center of two adjacent first trenches 7, but the principle is not changed.

The active region is formed by the two-step photoetching process, so that the stability of the structure in the processing process can be ensured, and the process cost and the time cost can be controlled. Of course, in other embodiments, the same method may be used to form a third trench, a fourth trench, etc. between the first trenches or between the second trenches to prepare a larger number of trenches.

The above embodiments show the manufacturing method for the active region and the isolation region, and the method of the present invention can also be used for manufacturing the capacitor structure, and also can be manufactured by performing a batch forming process on all trench structures, and the differences only exist in the material and the number of layers of the protection layer, the material and the number of layers of the hard mask layer, and the material of the filler. Those skilled in the art will also know how to apply the method to other semiconductor devices requiring the fabrication of similar high aspect ratio structures, and will not be described in detail herein.

The embodiment also provides a semiconductor structure, which is obtained by the above preparation method, and can be an active region and an isolation region structure on a semiconductor substrate, a micro trench structure in a micro capacitor, or other similar high aspect ratio structures. In the process of preparing the semiconductor structure by the method, the groove is not easy to collapse and has a stable structure.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate;

forming a first trench in the substrate, cleaning the first trench, filling the first trench, and forming active regions isolated from each other by the first trench;

forming a mask layer on the surface of the active area;

2. The method of claim 1, wherein the first trench and the second trench each comprise a plurality of trenches, and the plurality of second trenches and the plurality of first trenches are alternately spaced apart.

3. The method of claim 1, wherein forming a first trench in the substrate comprises:

forming a mask layer on the surface of the substrate;

4. The method of claim 1 or 3, wherein the mask layer comprises a photoresist.

5. The method of claim 4, wherein the mask layer further comprises a hard mask layer, the hard mask layer comprising one or both of a carbide layer and a nitride layer.

6. The method of claim 1 or 3, wherein the step of forming the opening in the mask layer comprises:

exposing and developing the mask layer in sequence to form a pattern;

7. The method of claim 1, wherein the substrate comprises a silicon wafer and a protective layer covering the silicon wafer.

8. The method of claim 7, wherein the protective layer comprises an oxide layer and a nitride layer overlying the oxide layer.

9. The method of claim 1, wherein filling the first trench or the second trench comprises:

and filling oxide into the first trench or the second trench.

10. A semiconductor structure prepared by the method of any one of claims 1-9.