JPS5885526A - Doping method of impurities to semiconductor crystal - Google Patents
Doping method of impurities to semiconductor crystalInfo
- Publication number
- JPS5885526A JPS5885526A JP18496181A JP18496181A JPS5885526A JP S5885526 A JPS5885526 A JP S5885526A JP 18496181 A JP18496181 A JP 18496181A JP 18496181 A JP18496181 A JP 18496181A JP S5885526 A JPS5885526 A JP S5885526A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- impurities
- doping
- layer
- semiconductor crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 title claims abstract description 21
- 239000013078 crystal Substances 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims abstract description 12
- 150000001875 compounds Chemical class 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- -1 metal A. In addition Chemical class 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体素子製造における不純物ドーピング技術
の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in impurity doping techniques in semiconductor device manufacturing.
ダイオード、トランジスタおよび集積回路の製造におい
て、半導体結晶の所定の領域に選択的に所定の不純物を
拡散またはイオン注入によってドーピングする技術は最
も基礎的で重要なものである。所定の領域にのみ不純物
をドープするには、イオン注入法と拡散法とがある。例
えばイオン注入においては、フォトレジストをウェーハ
ーに塗布後フォトレジストの窓を所定領域に設け、この
窓を通ってイオン注入を行うのが最も普通である。In the manufacture of diodes, transistors, and integrated circuits, the most basic and important technique is to selectively dope a predetermined region of a semiconductor crystal with a predetermined impurity by diffusion or ion implantation. There are ion implantation methods and diffusion methods for doping only a predetermined region with impurities. For example, in ion implantation, it is most common to apply a photoresist to a wafer, then provide a photoresist window in a predetermined area, and perform ion implantation through this window.
拡散においてはマスク材に5i02、Si3N、等が通
常用いられていてこのマスク材の窓からの拡散を利用し
ている。For diffusion, 5i02, Si3N, or the like is usually used as a mask material, and the diffusion through the windows of this mask material is utilized.
いずれにせよドーピングのマスクは正確に所定の位置に
窓が開けられていなければならないが、従来の方法にお
いてはどれだけ正確に所定領域の位置に窓開けが可能か
は、フォトマスクのバクーンをフ第1・レジストに露光
転写する際の位置合わせ精度によって決まり、従来の露
光装置では118mが限界でありこれ以上の精度を得る
のは困難であった。そして近年半導体素子の高周波特性
の向上、集積度の向上への要求はますます強くなってい
るが、この要求を満すには素子の大きさを小さくする必
要があり、そのため不純物のドーピングにおいてもより
微小な領域に高精度の位置合わせで行うことがますます
強く求められている。In any case, the doping mask must have windows formed in precisely the predetermined positions, but in conventional methods, how accurately it is possible to open the windows in the predetermined areas depends on the photomask window. It is determined by the positioning accuracy during exposure transfer to the first resist, and with conventional exposure equipment, the limit is 118 m, and it was difficult to obtain higher accuracy. In recent years, there has been an increasingly strong demand for improved high-frequency characteristics and increased integration of semiconductor devices, but in order to meet these demands, it is necessary to reduce the size of the devices, and therefore, it is necessary to reduce the size of the devices by doping impurities. There is an increasing demand for highly accurate positioning in smaller areas.
本発明はこのような状況を鑑みなされたものであり、±
1μm以下の高精度の位置合わせて不純物のY−ピング
を行うことを目的とするものである。The present invention was made in view of this situation, and ±
The purpose is to perform Y-ping of impurities with highly accurate positioning of 1 μm or less.
以下に図を用いて詳細に本発明の説明を行う。The present invention will be explained in detail below using figures.
第1図において、■は半導体結晶、例えば半絶縁性Ga
As結晶基板、2は結晶基板1の一主面上にあらかじめ
形成された一導電型領域、例えばn型GaAsエピタキ
シャル層である。かかる結晶表面上にまず8のA1層を
蒸着により形成する。In Fig. 1, ■ is a semiconductor crystal, such as semi-insulating Ga.
The As crystal substrate 2 is a region of one conductivity type formed in advance on one principal surface of the crystal substrate 1, for example, an n-type GaAs epitaxial layer. First, eight A1 layers are formed on the crystal surface by vapor deposition.
その上部に通常のフォトリソグラフィでレジストパター
ン4・を形成しエツチング等の方法でA1層を加工し、
レジストを除去することにより第2図のAJマスク3′
を形成する。かかる後に所望の第1回めの不純物ドーピ
ングを選択的に行なう。例えばSeのイオン注入により
半導体結晶中に一導電型領域2よりも深いn型領域8を
形成する(第2図)。次いでAノマスク3′を陽極酸化
法等により膨張させてAiマスクパター゛ン3″を形成
する(第3図)。陽極酸化法のように表面を酸化ないし
い窒化等で絶縁化する場合、一般に形成された絶縁膜の
厚さの半分だけ外側へ膨張する。ここではAiマスク3
′を0.25μm陽極酸化しマスク3′を両側へそれぞ
れ0.25μmずつ膨張させた。この後AIマスク3″
をマスクとして所望の第2回目の不純物ドーピングを例
えばSeのイオン注入によりn土層領域7を選択的に形
成する(第3図)。別の実施例では第2図に示すように
レジストパターン4・を残したまま第1回めの不純物ド
ーピングを行ない続いてAノマスク3′の陽極酸化を先
の実施例と同等に行ない第4図に示す如く側面方向にの
み膨張したAiマスク8″を得る。本発明はマスクが側
面方向に膨張すればその目的を満たすものであり再実施
例とも得られる効果は同じものとなる。さらに第1回目
の不純物ドーピング後に半導体結晶及びAノマスク8′
の表面に絶縁性薄膜を形成し陽極酸化に対して半導体結
晶表面を保護することも可能である。A resist pattern 4 is formed on top of it by normal photolithography, and the A1 layer is processed by etching or other methods.
By removing the resist, the AJ mask 3' in FIG.
form. After this, a desired first impurity doping is selectively performed. For example, an n-type region 8 deeper than one conductivity type region 2 is formed in the semiconductor crystal by ion implantation of Se (FIG. 2). Next, the A mask 3' is expanded by an anodic oxidation method or the like to form an Ai mask pattern 3'' (Fig. 3).When the surface is insulated by oxidation or nitridation as in the anodic oxidation method, generally It expands outward by half the thickness of the formed insulating film.Here, the Ai mask 3
' was anodized to a thickness of 0.25 μm, and the mask 3' was expanded by 0.25 μm on each side. After this, AI mask 3″
Using this as a mask, a desired second impurity doping is performed, for example, by ion implantation of Se to selectively form the n-soil layer region 7 (FIG. 3). In another embodiment, as shown in FIG. 2, the first impurity doping is performed while leaving the resist pattern 4, and then the A nomask 3' is anodized in the same manner as in the previous embodiment, as shown in FIG. As shown in FIG. 1, an Ai mask 8'' is obtained which expands only in the lateral direction.The purpose of the present invention is achieved if the mask expands in the lateral direction, and the effect obtained in the second embodiment is the same. After the second impurity doping, the semiconductor crystal and the A no mask 8'
It is also possible to protect the semiconductor crystal surface from anodic oxidation by forming an insulating thin film on the surface of the semiconductor crystal.
本実施例では2回目のイオン注入が1回目のイオン注入
よりも深く、すなわち高エネルギで、1回目よりも低い
ドーズ量で行われた場合のものであり、2のn型領域と
7のn十領域との間に8の深いn型領域を介在させた構
造を得る例である。ここで7と8との間隔はAノマスク
3′と膨張したMマスク3″とのパターンサイズ差すな
わち表面酸化によるパターン膨張量によって決定される
が、Tiは例えば陽極酸化、プラズマ陽極酸化等により
高精度の膨張が可能であるため、その量を±1μm以下
で制御することができ、従って7と8との間隔は高精度
で制御できる。In this example, the second ion implantation was performed deeper than the first ion implantation, that is, with high energy and at a lower dose than the first, and the n-type region 2 and the n-type region 7 were implanted. This is an example of obtaining a structure in which eight deep n-type regions are interposed between ten regions. Here, the interval between 7 and 8 is determined by the pattern size difference between the A mask 3' and the expanded M mask 3'', that is, the amount of pattern expansion due to surface oxidation. Since precision expansion is possible, the amount can be controlled within ±1 μm, and therefore the interval between 7 and 8 can be controlled with high precision.
明らかに本発明は上記例以外にも各種の変形、応用が可
能である。例えば8のAノはTi、Mo、Ta等の高精
度陽極酸化が可能な他の金属、あるいはSi等の半導体
材料を用いることもできる。広くは酸化物のみならず窒
化物や炭化物等の他の化合物となる材料であればよい。Obviously, the present invention can be modified and applied in various ways other than the above examples. For example, for A in No. 8, other metals that can be anodized with high precision such as Ti, Mo, and Ta, or semiconductor materials such as Si may be used. Broadly speaking, any material may be used as long as it is not only an oxide but also other compounds such as nitrides and carbides.
またドープする不純物はSeに限定されず、n型、p型
任意のものを採用できる。また結晶はG aAsに限定
されずに5i1Ge、InP等任意のものを用いること
ができる。Further, the impurity to be doped is not limited to Se, and any n-type or p-type impurity can be used. Further, the crystal is not limited to GaAs, and any crystal such as 5i1Ge and InP can be used.
以上述べた如く、本発明によれば、Aノ金属の如く化合
物となる前の段階のマスク材において所定5−
の条件で化合物とすることにより体積が所定の割合で膨
張することを利用するために、膨張前後のマスクをもと
にドーピングを行うと極めて高精度な間隔差を持ったド
ーピングが可能となる。As described above, according to the present invention, the volume expands at a predetermined rate by forming a compound under predetermined conditions in a mask material at a stage before it becomes a compound, such as metal A. In addition, if doping is performed based on the masks before and after expansion, it becomes possible to perform doping with extremely high precision spacing differences.
第1図乃至第4.は本発明の製造方法の工程を示すため
の断面図である。
1・・・半導体結晶基板
2 ・・ −導電型領域
3.3′・・・マスク材料 例えばA、i!!4 ・・
・・マスク材料 例えばフォト・レジストのレジストパ
ターン
7・・・・第1不純物ドープ領域
8 ・第2不純物ドープ領域
3′邑−・・膨張したマスク材料
−〇−Figures 1 to 4. FIG. 2 is a cross-sectional view showing steps of the manufacturing method of the present invention. 1...Semiconductor crystal substrate 2...-Conductivity type region 3.3'...Mask material For example, A, i! ! 4...
...Mask material, for example, photoresist resist pattern 7...First impurity doped region 8 -Second impurity doped region 3'...Expanded mask material -〇-
Claims (1)
方法において、半導体結晶の表面に金属等からなるマス
ク材を形成し、これをマスクとして第1回目の不純物ド
ーピングを行ないかかる後に前記マスク材を化合物に変
化せしめることにより所定量膨張させた後に第2回目の
不純物ドーピングを行なうことを特徴とする半導体結晶
への不純物ドーピング方法。(1) In a method of selectively doping impurities into a semiconductor crystal, a mask material made of metal or the like is formed on the surface of the semiconductor crystal, and this is used as a mask to perform the first impurity doping. 1. A method of doping impurities into a semiconductor crystal, which comprises expanding the semiconductor crystal by a predetermined amount by changing it into a compound, and then performing a second impurity doping.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18496181A JPS5885526A (en) | 1981-11-17 | 1981-11-17 | Doping method of impurities to semiconductor crystal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18496181A JPS5885526A (en) | 1981-11-17 | 1981-11-17 | Doping method of impurities to semiconductor crystal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5885526A true JPS5885526A (en) | 1983-05-21 |
Family
ID=16162371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18496181A Pending JPS5885526A (en) | 1981-11-17 | 1981-11-17 | Doping method of impurities to semiconductor crystal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5885526A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5378181A (en) * | 1976-12-22 | 1978-07-11 | Hitachi Ltd | Semiconductor device and its manufacture |
-
1981
- 1981-11-17 JP JP18496181A patent/JPS5885526A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5378181A (en) * | 1976-12-22 | 1978-07-11 | Hitachi Ltd | Semiconductor device and its manufacture |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR940001891B1 (en) | Method of making semiconductor device | |
EP0036573A2 (en) | Method for making a polysilicon conductor structure | |
JPS6150394B2 (en) | ||
JPS615580A (en) | Manufacture of semiconductor device | |
KR20090098832A (en) | Semiconductor device manufacturing method | |
US5001077A (en) | Method of producing an asymmetrically doped LDD MESFET | |
GB2230899A (en) | Method of producing a gate | |
US5319231A (en) | Insulated gate semiconductor device having an elevated plateau like portion | |
JPH03152954A (en) | Formation of electric field separation construction and gate construction in integrated misfet device | |
JPS5885526A (en) | Doping method of impurities to semiconductor crystal | |
US3951694A (en) | Method of manufacturing a semiconductor device and device manufactured according to the method | |
JPS6040702B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
JPS60193371A (en) | Manufacture of semiconductor device | |
US4380481A (en) | Method for fabricating semiconductor devices | |
JPS58123723A (en) | Impurity doping method onto semiconductor crystal | |
JPS5879719A (en) | Method for doping impurity into semiconductor crystal | |
JPS5885527A (en) | Doping method of impurities to semiconductor crystal | |
KR100469760B1 (en) | Method for forming gate oxide of merged semiconductor device | |
KR0166824B1 (en) | Semiconductor device manufacturing method | |
KR940001813B1 (en) | Isolation method and device of semiconductor | |
KR100540332B1 (en) | Method for fabricating pattern of semiconductor device | |
JPS6316672A (en) | Manufacture of semiconductor element | |
JPS62108576A (en) | Manufacture of semiconductor device | |
JPS6050069B2 (en) | Transistor making method | |
JPS58123721A (en) | Impurity doping method onto semiconductor crystal |