JPS5885527A - Doping method of impurities to semiconductor crystal - Google Patents

Abstract

PURPOSE:To make doping of impurities possible with accurate positioning of less than + or -1mum accuracy, by a method wherein the first doping is performed on the basis of the first pattern, and then the second doping is performed on the basis of the pattern which is made smaller than the first pattern by the fixed quantiy. CONSTITUTION:A Ti layer 3 is formed on the crystal surface by vapor deposition, and a resist pattern 4 is further formed thereon. The Ti layer is then processed by the method such as etching, and the resist 4 is removed to form a Ti mask 3'. After that, the first desired doping of impurities is performed to form an n<+> region 7 within the semiconductor crystal by implanting ion utilizing Se etc. Then the Ti mask 3' is etched isotropically to make smaller by the fixed quantity e.g. 0.3mum. For the above etching, the plasma etching with high accuracy is suitable. The desired second doping is performed utilizing the Ti mask 3'' as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in impurity doping techniques in semiconductor devices.

In the manufacture of diodes, transistors, and integrated circuits, the most basic and important technique is to selectively dope a predetermined region of a semiconductor crystal with a predetermined impurity by diffusion or ion implantation. There are ion implantation methods and diffusion methods for doping only a predetermined region with impurities. For example, ion implantation 1 - In humans, it is most common to apply photoresist to a wafer, then provide a photoresist window in a predetermined area, and perform ion implantation through this window.

In diffusion, mask material has 810. , SI3N, etc. are commonly used, and the diffusion through the window of this mask material is utilized.

In any case, the doping mask must have windows formed at precisely predetermined positions, but with conventional methods, it is difficult to determine how accurately the windows can be opened at the positions of predetermined areas. It is determined by the alignment accuracy when exposing and transferring the mask pattern to the photoresist, but with conventional fog light equipment, ±1 μm is one virtual limit, and from this point onwards.
It was difficult to obtain an accuracy of 2. In recent years, demands for improved high-frequency characteristics and increased integration of semiconductor devices have become stronger and stronger, but in order to meet these demands, it is necessary to reduce the size of the devices, which requires doping with impurities. There is an increasing demand for highly accurate positioning in even smaller areas.

2- The present invention was developed in view of the above situation, and its object is to perform impurity doping with highly accurate positioning of less than 1/-Lm.

The present invention will be explained in detail below using figures.

In FIG. 1, 1 is a semiconductor crystal, for example, a semi-insulating Q a
The As crystal substrate 2 is a region of one conductivity type formed in advance on one principal surface of the crystal substrate 1, for example, an n-type GaAs epitaxial layer. First, 3 Ti is deposited on the surface of such a crystal.
The layer is formed by vapor deposition.

A resist pattern 4 is formed on top of the resist pattern 4 by ordinary photolithography, and the T1 layer is processed by a method such as etching and the resist is removed to form the TI mask 8 shown in FIG.
′ is formed. After this, a desired first impurity doping is performed. For example, Se is doped into the semiconductor crystal by ion implantation to form an n region 7 as shown in FIG. The TI mask 3' is then isotropically etched to reduce it by a predetermined amount, for example 0.3 μm. High-precision plasma etching is suitable as the etching method. Daiichi 3
= 3 As shown in Figure 3, the desired second impurity doping is performed using the reduced Ti mask 3// as a mask.

The example shown is a case where the second Se ion implantation was performed deeper than the first ion implantation, that is, with a higher energy and a lower dose than the first. This is an example of obtaining a structure in which 8 deep n-type regions are interposed between the n-type region and the n-type region.

Here, the interval between 7 and 8 is determined by the pattern size difference between the Ti mask 3' and the reduced Ti mask 8'', that is, the amount of pattern reduction by etching. Since processing is possible, the side etching amount can be controlled to ±1 μm or less, and therefore 7 and 8
The spacing can be controlled with high precision.

Obviously, the present invention can be modified and applied in various ways other than the above examples. ``For example, 3 (3', 3'') Ti may be other metals that can be etched with high precision, such as Mo or Ta.
It is also possible to use an insulator such as aluminum or 5i02. Furthermore, the resist pattern 4 itself is also applicable. In addition, the impurities in the tope are not limited to Se,
Any N-type or P-type can be used, and in combination with a mask material, impurity doping methods such as thermal diffusion are also possible. Moreover, the crystal is not limited to GaAs, but also Si, Ge
, InP, etc. can be used.

As described above, according to the present invention, after the first doping is performed on the first pattern, the pattern is made smaller by a predetermined amount and the second doping is performed. The relative positions of the second doping can be set extremely precisely.

[Brief explanation of the drawing]

1 to 3 are cross-sectional views showing one embodiment of the present invention. 1...Semiconductor crystal substrate 2...Conductivity type region 3...Mask material 37, 3''...After etching etc. Mask material 5
- 4...Photoresist Bakun 7...
......First impurity doped region 8...
・Second impurity doped region -〇-

Claims (1)

[Claims] According to the method of selectively doping impurities into a semiconductor crystal, a mask cut is formed on the surface of the semiconductor crystal, and after the first impurity doping is performed using this as a mask, the mask material is reduced by a predetermined amount. 1. A method for doping impurities into a semiconductor crystal, which comprises performing a second impurity doping after doping.