JPH03190140A - Mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a low-concentration impurity regions of an LDD structure exact in dimensional accuracy by a method wherein the surface of a silicon substrate is formed in a projected from, a channel part is formed on the upper end of this projected region and the low-concentration impurity regions are respectively formed in the side surface parts of the projected region using an ion implantation method. CONSTITUTION:A silicon substrate 10 is thermally oxidized to form a gate oxide film 11 and moreover, a polysilicon film 12 is deposited using a CVD method. Then, the films 12 and 11 are etched using a photoresist film 33 formed by a photolithography technique as a mask to form a gate electrode 22 and moreover, the substrate 10 is etched to a prescribed depth. Subsequently, an oblique ion implantation is performed in the side surfaces of a projected part at an angle of 45 deg. and low-concentration impurity regions 14 are formed. As the dimension of the regions 14 is decided by the amount of etching in the depth direction of the substrate 10, the dimension can be set precisely by a reactive ion etching device or the like.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a MOS transistor and a method for manufacturing the same, and particularly relates to a MOS transistor and a method for manufacturing the same.
The present invention relates to a MOS transistor having an in) structure and a method for manufacturing the same.

[Conventional technology]

As LSIs become more highly integrated and faster, MOS transistors are becoming increasingly finer. Therefore, a single MOS transistor has a reduced planar dimension and a shortened channel length.

As the channel becomes shorter in this way, electric field concentration occurs at the part of the drain junction of the MOS transistor that is in contact with the silicon surface, and the hot carriers generated here enter the upper gate oxide film, causing deterioration of the gate oxide film. Therefore, as miniaturization progresses, it is necessary to lower the electric field at the train junction. To this end, conventionally, an LDD structure has been used in which a low concentration region is provided near the silicon surface of the drain junction where the electric field is most concentrated to moderate the impurity distribution. FIGS. 2(a) to 2(d) show cross-sectional views of an example of the manufacturing process of a conventional LDD structure MOS transistor in order of process.

First, as shown in FIG. 2(a), a silicon substrate 10 is thermally oxidized to form a gate oxide film 11, and then a polysilicon film 12 is grown.

Next, as shown in FIG. 2(b), a gate electrode 22 made of a polysilicon film is formed using photolithography and etching techniques, and then impurities are introduced by ion implantation to form a low concentration impurity region 14. .

Subsequently, as shown in FIG. 2(c), the silicon substrate 10
An oxide film 13 is deposited thereon by CVD.

Thereafter, as shown in FIG. 2(d), the oxide film 13 is etched back to form a sidewall 23, and then impurities are introduced by ion implantation to form a source region 24 and a drain region 25. .

[Problems to be Solved by the Invention] However, in the above-mentioned LDD structure MoS transistor, the manufacturing process is complicated, and the low concentration impurity region 14 is formed by etching back the oxide film deposited by the CVD method to form the gate electrode. 22 and is formed by ion implantation using this as a mask, there is a problem that the dimensional accuracy of that region becomes unstable.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to provide a MOS transistor and a method for manufacturing the same in which the dimensional accuracy of a lightly doped region is improved without using any special equipment or process.

[Means to solve the problem]

The MoS transistor of the present invention includes a silicon substrate formed in a convex shape, a gate electrode formed on the convex region with a gate oxide film interposed therebetween, and a gate electrode formed downward from the side surface of the convex region. It is configured to include a high concentration impurity region and source/drain regions in contact with the low concentration impurity region.

Further, the method for manufacturing a MOS transistor of the present invention includes a step of forming a convex island-like region on a silicon substrate surface, forming a gate electrode on the island-like region via a gate oxide film, and then forming a gate electrode on the island-like region through a gate oxide film. a step of forming a low concentration impurity region by an ion implantation method with a side surface having an angle; a step of forming an oxide film on the side surface of the island-like region in which the low concentration impurity region is formed; forming a source region and a drain region in contact with the region.

[Effect]

By forming the surface of a silicon substrate into a convex shape, forming a channel portion at the upper end of the convex region, and forming a low concentration impurity region at the side surface of the convex region using an ion implantation method, an LDD can be manufactured.
The dimensional precision of the low concentration impurity region of the tllI structure can be created accurately.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings. FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1(a), a gate oxide film 11 is formed by thermally oxidizing a silicon substrate 10, and then a polysilicon film 12 is deposited using the CVD method.

Next, as shown in FIG. 1B, using the photoresist film 33 formed by photolithography as a mask, the polysilicon film 1 is etched using, for example, sputter etching technology.
2 and gate oxide film 11 are etched to form gate electrode 22, and silicon substrate 10 is further etched to a predetermined depth.

Subsequently, as shown in FIG. 1(c), oblique ion implantation is performed at an angle of 45° to the side surface of the convex portion to form a low concentration impurity region 14.

Thereafter, as shown in FIG. 1(d), an oxide film 21 is formed on the gate electrode 22 by thermal oxidation, and a side oxide film 31 is formed on the side surface of the convex portion.
After forming the silicon substrate 10, highly concentrated impurities are introduced at an angle substantially perpendicular to the surface of the silicon substrate 10 by ion implantation.
A source region 24 and a drain region 25 are formed.

According to the MOS transistor manufactured in this way, the process does not become complicated, and the dimensions of the low concentration impurity region 14 are determined by the amount of etching in the depth direction of the silicon substrate 10. It can be produced with high precision using a reactive ion etching device used in

〔Effect of the invention〕

As described in detail above, according to the present invention, as LDD structure MOS transistors are miniaturized, the dimensions of the low concentration impurity region necessary for alleviating electric field concentration at the drain end can be created with high precision. . Further, in contrast to a conventional LDD structure MOS transistor in which a low concentration impurity region is formed in a planar shape between the source region, the train region, and the gate region, according to the present invention, the low concentration impurity region is formed in a convex shape. Since the source region and the drain region are in contact with the gate electrode in plan view, the area required to form the MOS transistor is effectively reduced. It can be made small and highly integrated.

Furthermore, since it can be manufactured by simply combining general CMOS processes without using special processes or equipment, manufacturing costs will not increase.

[Brief explanation of drawings]

FIGS. 1(a) to (d) are cross-sectional views of a semiconductor chip for explaining one embodiment of the present invention, and FIGS. 2(a) to (d) are each manufacturing process of a conventional MOS transistor with an LDD structure. FIG. 2 is a cross-sectional view of a semiconductor chip for explaining. 10... Silicon substrate, 11... Gate oxide film, 1
2... Polysilicon film, 13... Oxide film, 14...
- Low concentration impurity region, 21... Oxide film, 22... Gate electrode, 23... Side wall, 24... Source region, 25... Train region, 31... Side oxide film, 33 ...$l concave 2nd m

Claims (1)

[Claims] 1. A silicon substrate formed in a convex shape, a gate electrode formed on the convex region via a gate oxide film, and a gate electrode formed downward from the side surface of the convex region. A MOS transistor comprising a low concentration impurity region and source/drain regions in contact with the low concentration impurity region. 2. Step of forming a convex island-like region on the silicon substrate surface, forming a gate electrode on this island-like region via a gate oxide film, and then implanting ions at an angle into the side surface of the island-like region. a step of forming a low concentration impurity region by a method, a step of forming an oxide film on the side surface of the island-like region where the low concentration impurity region is formed, and a step of forming a source region and a drain region in contact with the low concentration impurity region. 1. A method for manufacturing a MOS transistor, the method comprising: forming a MOS transistor.