JP3378561B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, it is suitable for forming different semiconductor elements on a plurality of different semiconductor layers formed on the same semiconductor substrate. The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art A conventional manufacturing method (1) for forming two or more types of semiconductor devices in a plurality of semiconductor layers will be described with reference to FIG. In this method, all manufacturing steps are performed using one alignment mark. First,
As shown in FIG. 3A, the second substrate is formed on the semiconductor substrate 101.
The semiconductor layer 103 and the first semiconductor layer 102 are stacked to be formed. Next, as shown in FIG. 3B, a metal is deposited on the surface of the uppermost first semiconductor layer 102, and alignment for photolithography is performed by using a well-known photolithography and lift-off technique. The mark 104 is formed. This alignment mark 104
Is formed of a material mainly containing Au in consideration of acid resistance and the like.

Photolithography and etching are performed using the alignment mark 104, and the first
The first semiconductor element 105 composed of the semiconductor layer 102 is formed. At this time, the alignment mark 104 is formed.
However, it is deformed under the influence of processing such as etching,
The alignment accuracy in the subsequent second semiconductor element 106 forming process may be reduced. In order to prevent this, as shown in FIG. 3C, the resist pattern 107 is formed not only over the region where the first semiconductor element 105 is formed but also over the alignment mark 104, and the first pattern is formed. The alignment mark 104 is protected in each step of forming the semiconductor element 105.

Therefore, when etching or the like is performed in this state to form the first semiconductor element 105 composed of the first semiconductor layer 102, as shown in FIG. 3D, the first semiconductor element 105 is formed.
Has a step equal to the thickness of the semiconductor layer 102, and the alignment mark 104 remains on the upper surface of the mesa 108.
Are formed together with the first semiconductor element 105.

Also in the subsequent step of forming the second semiconductor element 106 composed of the second semiconductor layer 103, as shown in FIG. 3E, the alignment mark 104 is used to form the second semiconductor element 106. The semiconductor element 106 is formed.

Instead of forming the alignment mark 104 by depositing metal in the conventional method (1), a method (2) has been proposed in which a hole is formed in a semiconductor layer by etching and the hole is used as an alignment mark. There is. In this method (2), as shown in FIG. 4A, first, a plurality of stacked semiconductor layers 102 and 103 are formed.
This is a method in which a hole penetrating through is formed by etching and this hole is used as an alignment mark 201 for photolithography.

Next, as shown in FIG. 4B, a photoresist pattern 107 having a predetermined shape is formed by using the alignment mark 201, and then, as shown in FIG.
As shown in (c), the photoresist pattern 1
A necessary process such as etching an unnecessary portion of the semiconductor layer 102 is performed using 07 as a mask to form the first semiconductor element 105 including the first semiconductor layer 102.

Further, the second semiconductor layer 103 formed of the second semiconductor layer 103 is formed by photolithography and etching.
4D, as is clear from FIG. 4D, even in the step of forming the second semiconductor element 106 made of the second semiconductor layer 103, the alignment mark 201 made of the hole is formed. The second semiconductor element 106 was formed using this.

[0009]

However, according to the study by the present inventor, the conventional methods (1) and (2) described above are
An element formed of a thick semiconductor layer such as a D (Photodiode) and a HEMT (High Electron)
It has been clarified that there are the following problems when an element formed of a relatively thin semiconductor layer, such as a Mobility Transistor (IC), is formed on the same substrate.

That is, in the above-mentioned conventional method (1), in order to prevent the deformation and change of the alignment mark 104 when the first semiconductor element 105 is formed, FIG.
As shown in FIG. 5, it is necessary to cover and protect the alignment mark 104 with the photoresist 107 or the like. As a result, as the process of forming the first semiconductor element 105 progresses, as shown in FIG. 3D, the mesa 108 in which the alignment mark 104 remains on the top is formed, and a large step is formed. The step due to the mesa 108 becomes equal to the thickness of the first semiconductor layer 102 after the formation process of the first semiconductor element 105 is completed.

When the first semiconductor element 105 is an optical element such as PD, the thickness of the first semiconductor layer 102 is 1000.
The thickness is about nm or more, which is much thicker than the thickness 200 nm of the second semiconductor layer 103 for forming the HEMT IC. In addition, in general, the alignment mark of the reduction type exposure apparatus has a side length of about several 100 μm to several mm.

In order to form the second semiconductor element 106 on the second semiconductor layer 103, fine processing such as gate formation is required. In that case, a thin resist film having a thickness of several 100 nm is used. There is a need. However, according to the study by the present inventor, if there is a mesa having a side length of several tens of μm and a step difference larger than the thickness of the resist film, a comet-shaped resist is formed from the center of the wafer toward the periphery. It was found that coating unevenness occurred. Since this coating unevenness reaches a length of several hundreds of μm or more, the fine resist pattern existing around the mesa has a defective shape and the precision of fine processing is remarkably lowered.

In the above conventional method (2),
First semiconductor element 105 including first semiconductor layer 102
In the step of forming the, as shown in FIG.
A photoresist film for protecting the alignment mark 201 cannot be used in order to prevent the occurrence of a step due to a mesa around the alignment mark 201. Therefore, although a large step due to the mesa does not occur, the shape change 202 of the alignment mark 201 occurs as shown in FIG. 5B because a process such as etching is performed without protecting the alignment mark 201. . When the shape change 202 occurs in the alignment mark 201, the alignment accuracy in the photolithography process when fine processing such as gate processing is required is reduced, and various fine patterns are formed at predetermined positions with high accuracy. Becomes difficult.

Therefore, according to the above conventional methods (1) and (2), it is difficult to form a HEMT gate or the like, which requires particularly fine processing, in the second semiconductor layer 103 with high accuracy. As a result, there has been a problem that the in-plane uniformity of the transfer conductance and the threshold value deteriorates. The second semiconductor layer 103 is the substrate 1
01 is not directly formed on the first semiconductor layer, but an underlayer (intermediate layer) for insulating the two from each other or performing good epitaxial growth is formed between the two, and the second semiconductor layer is It is epitaxially grown on the underlayer (intermediate layer). However, in order to simplify the drawing and facilitate understanding, in FIGS. 3 to 5, the underlayer (intermediate layer) is used.
Are omitted, and the second semiconductor layer 103 is directly shown on the substrate 101.

An object of the present invention is to solve the above problems of the prior art, and to form different semiconductor elements in a plurality of semiconductor layers laminated on the same substrate easily and with high accuracy. A method of manufacturing a semiconductor device is provided.

[0016]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a second semiconductor layer and a first semiconductor layer formed on the second semiconductor layer. When processing a plurality of semiconductor layers including at least a layer to form a semiconductor device, after forming a first alignment mark on the surface of the first semiconductor layer, a photo using the first alignment mark A step of forming a first semiconductor element on the first semiconductor layer by a lithographic step, and a step of forming a second alignment mark on the surface of the second semiconductor layer using the first alignment mark. And using the second alignment mark after removing the first alignment mark and the mesa-type structure having the first alignment mark formed on the upper surface. Performing O bets lithography process, characterized in that it comprises a step of forming a second semiconductor device to the second semiconductor layer.

That is, according to the present invention, the first alignment mark and the first alignment mark used in the step of forming the first semiconductor element formed of the first semiconductor layer included in the plurality of semiconductor layers formed by stacking are formed. The large mesa structure generated by the first alignment mark is removed prior to forming the second semiconductor element including the second semiconductor layer formed in contact with the lower surface of the first semiconductor layer, and The second semiconductor element composed of the second semiconductor layer is formed by a photography process using a second alignment mark newly formed by using the first alignment mark.

Therefore, in the step of forming the second semiconductor element, highly accurate alignment is performed by using the newly formed highly accurate second alignment mark without being affected by the previous step. be able to. Further, prior to the step of forming the second semiconductor element formed from the second semiconductor layer, the first alignment mark and the first alignment mark generated in the step of forming the first semiconductor element are formed on the upper part. Since the remaining mesa structure having a large area and a large step is removed, the above-mentioned comet-shaped coating unevenness does not occur during resist coating for fine processing in the second semiconductor element forming step. Effectively prevented. Therefore, the resist is satisfactorily applied without application unevenness, and it becomes possible to carry out a fine lithography technique with high precision, and it is possible to form a HEMT gate that requires particularly fine processing with high precision. As a result, it is possible to obtain a HEMT having extremely good in-plane uniformity of transfer conductance and threshold value.

As the first and second semiconductor layers,
A laminated film of a plurality of semiconductor layers can be used for each. For example, the first semiconductor layer may be InGaA.
InGaAs / In as the s / P layer and the second semiconductor layer
AlAs / InP layers can be used respectively.

It is most practically useful that the film thickness of the first semiconductor layer is larger than the film thickness of the second semiconductor layer. In this case, as the first semiconductor element, an optical element or a transistor-type electronic element in which electrons flow in the vertical direction can be formed, and as the second semiconductor element, a transistor-type electron in which electrons flow in the horizontal direction can be formed. A device or a diode type electronic device can be formed. The optical element is a laser or a photodiode, and the transistor type electronic element in which electrons flow in the vertical direction is an HBT (Heterojunction Bipolar Transistor).
istor: heterojunction bipolar transistor) or RTT (Resonant Tunneling Transistor), and FET (Field Effect Transistor) is used as the transistor-type electronic element in which electrons flow in the lateral direction.
istor; field effect transistor), HEMT or H
FET (Heterostructure Field Effect Transistor;
Heterostructure field effect transistor), and the diode type electronic element is a Schottky diode or R
TDs (Resonant Tunneling Transistors) can be formed respectively.

Further, the first alignment mark is
In order to avoid deformation and the like in wet etching, it is preferable that the solubility in acid is small and that the material be formed from a material that can be easily etched by the reactive ion etching method. As such a material, Ti or Mo is practically suitable.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS. 1 and 2. Figure 1
In (a), symbol 401 is a semi-insulating InP substrate, 4
Reference numeral 03 denotes an HE including a HEMT epitaxially grown on a semi-insulating InP substrate 401 and a Schottky diode.
InGaAs / InAlA for forming MT / IC
A second semiconductor layer made of s / InP having a thickness of about 0.2 μm, and 402 is a UCT-PD (Uni-Carrier-Transpor) epitaxially grown on the second semiconductor layer 403.
InGaAs / InP for forming t photodiode)
The first semiconductor layers each having a thickness of about 1 μm are represented. Note that the InP substrate 401 and the second semiconductor layer 403
InP substrate 4 such as an InAlAs layer
01 between the second semiconductor layer 403 and the semiconductor layer 40
The underlying layer (intermediate layer) for satisfactorily epitaxially growing No. 3 is interposed, and the second semiconductor layer 403 is formed on the underlying layer (intermediate layer). In order to facilitate understanding, the underlayer (intermediate layer) is also used in FIGS. 1 and 2 as in FIGS.
Are not shown.

As shown in FIG. 1B, a thickness of 1000 is formed on the first semiconductor layer 402 by using the well-known photolithography technique, metal deposition technique and lift-off technique.
A first alignment mark 404 made of Å titanium (Ti) was formed. This first alignment mark 40
No. 4 shows a partial pattern such as a vernier pattern during the wet etching in the process of forming the UTC-PD.
Since it comes into contact with the acid used for etching, it is necessary to have sufficient acid resistance. In addition, after the step of forming the UTC-PD is completed, it is necessary to be easily removed by a reactive ion etching (RIE) method. In order to satisfy these conditions, the first alignment mark 40 in the present embodiment.
Although Ti was used as the material of No. 4, the material is not limited to Ti, and the same effect can be obtained by using, for example, Mo having similar properties.

Next, a photoresist is applied to remove unnecessary portions of the photoresist, and the first alignment mark 404 is formed.
Is used as a reference to form a photoresist pattern 405 for forming the UTC-PD, and in order to prevent deformation and alteration of the first alignment mark 404 in the element forming process, a protective photo film is also formed on the first alignment mark 404. A resist pattern 406 was formed to cover the first aligned mark 404.

These photoresist patterns 405,
Using 406 as a mask, the well-known wet etching technique was used to etch the exposed portion of the semiconductor layer 402 to form the UTC-PD 407. During this wet etching, some patterns such as vernier in the first alignment mark 404 came into contact with the acid used for etching.
Since i was used, a large shape change did not occur in the first alignment mark 404. After the step of forming the UTC-PD, as shown in FIG.
UTC-PD407 having a step equal to the thickness of the first alignment mark 404 and the mesa 4 having the first alignment mark 404 on the upper surface.
08 was formed. FIG. 1C shows the UTC-PD407.
After the step of forming the photoresist is completed, the photoresist pattern 40 is formed.
5 shows the state when 5,406 is removed. UTC
-The typical size of PD407 is 20 to 30μ on a side.
On the other hand, the mesa 408 having the first alignment 404 on the upper surface has a side of 100 to 700 μm.
It was about.

Further, the first alignment mark 4 mentioned above.
04, as shown in FIG.
The second alignment mark 409 for forming the HEMT IC from No. 03 was formed on the second semiconductor layer 403 by using the well-known photolithography technique, metal deposition technique, and lift-off technique. In this embodiment, the material of the second alignment mark 409 is gold (Au).
Was used as the main material, and its thickness was set to 2200Å. In the present invention, the second alignment mark 409
The material is not limited to Au. However, according to the study by the present inventor, the second alignment mark 409
It has been revealed that the second alignment mark 409 cannot be covered with the resist film if the thickness of the second alignment mark 409 is equal to or larger than the thickness of the resist film. The thickness of the EB resist needs to be equal to or less than that.

As shown in FIG. 2A, the second alignment mark 409 is used to form a photoresist mask 410 that covers the portion other than the first alignment mark 404 and the mesa 408 under the first alignment mark 404. .

Next, a reactive gas containing SF ₆ gas is used.
After removing the exposed first alignment mark 404 by ion etching, an etchant for InGaAs containing citric acid / hydrogen peroxide as a main component and an etchant for InP containing hydrochloric acid / phosphoric acid / acetic acid as a main component The mesa 408 was removed by etching using. FIG. 2B shows a state in which the photoresist mask 410 is further removed after removing the first alignment mark 404 and the mesa 408. In this case, it is most preferable that the mesa 408 is completely removed and the surface is completely flattened. However, if the step due to the remaining portion of the mesa 408 does not exceed the thickness of the resist film used in the subsequent step, even if the mesa 408 is a large mesa whose one side length exceeds several tens of μm, the peripheral element formation It was clarified that a large flow of coating unevenness that might affect the above does not occur. Therefore, even if the mesa 408 remains in a range not exceeding the thickness of the resist film used in the subsequent step, there is no practical problem.

Next, after a photoresist film is formed on the entire surface, unnecessary portions are removed, and as shown in FIG.
A photoresist pattern 411 is formed and UTC-PD
407 and second alignment mark 409 protection and H
It was used as a mask for forming EMT / IC elements.

Using the photoresist pattern 411 as a mask, steps necessary for forming the HEMT IC such as etching of the exposed portion of the second semiconductor layer 403 were performed. In the present embodiment, since it is necessary to form a gate having a width of 0.1 μm to form the HEMT IC,
In the step of forming the gate, EB (electron beam) drawing was used. The thickness of the EB resist film applied for EB drawing was 3500 Å. After applying the EB resist,
Insufficient coating on UTC-PD407 and a slight change in the film thickness of the EB resist in the vicinity of the periphery were observed, but no coating flow such as a large flow was observed. Therefore, the same gate processing as usual and the subsequent HEMT IC
The entire process could be completed by performing the forming process of No.
After the completion of all the steps, as shown in FIG. 2D, the element 412 in the HEMT / IC made of the semiconductor layer 403 was formed.

After all the manufacturing steps of the UTC-PD 407 and the HEMT / IC were completed, they were formed on the substrate at equal intervals.
The characteristics of 9 HEMTs were investigated. As a result, the average of the threshold values was -570 mV, and the dispersion was 30 mV. The average maximum transconductance is 1200 mS /
mm, the dispersion was 75 mS / mm. These values are equal to the HEMT values and the in-plane uniformity in HEMT / IC when UTC-PD407 is not present on the same substrate, and an element including a thick semiconductor layer such as UTC-PD can be used as a HEMT. It was possible to realize integration on the same substrate together with a semiconductor element composed of a thin semiconductor layer.

[0032]

As described above, according to the present invention, a semiconductor element formed of a thin semiconductor layer and a semiconductor element formed of a thick semiconductor layer can be integrated and formed on the same substrate. In particular, the effect is great for a structure in which a thick semiconductor layer is stacked on a thin semiconductor layer. Such a semiconductor layer structure is particularly useful when integrating an FET electronic circuit composed of a thin semiconductor layer and an optical element composed of a thick semiconductor layer, and has a very great practical effect. By utilizing the present invention, it becomes possible to manufacture a novel OEIC having unprecedented performance in which an FET electronic circuit using the latest miniaturization technology and an optical element having high light efficiency are integrated.

[Brief description of drawings]

FIG. 1 is a process drawing showing an embodiment of the present invention.

FIG. 2 is a process drawing showing an embodiment of the present invention.

FIG. 3 is a process drawing showing an example of a conventional method for forming a semiconductor device.

FIG. 4 is a process chart showing an example of a conventional method for forming a semiconductor device.

FIG. 5 is a diagram showing an example of a conventional method for forming a semiconductor device.

[Explanation of symbols]

101 ... Semiconductor substrate, 102, 103 ... Semiconductor layer, 10
4 ... Alignment marks 104, 105 ... First semiconductor element, 106 ... Second semiconductor element, 107 ... Photoresist pattern, 108 ... Mesa, 201 ... Alignment mark, 202 ... Alignment mark deformation, 401 ... Semiconductor substrate, 402 ... first semiconductor layer, 403 ... second semiconductor layer, 404 ... alignment mark, 405, 406
… Photoresist pattern, 407… UTC-PD, 4
08 ... Mesa, 409 ... Alignment mark, 410, 4
11 ... Photoresist pattern, 412 ... Element.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 27/15 H01L 27/06 F 29/778 31/10 A 29/812 31/10 H01S 5/026 (56) References Kai 63-237520 (JP, A) JP 2000-114277 (JP, A) International Conference on Indium Phosphide and Relatated Materials, 2000. Conference Proceedings, USA, May 2000, P.M. 329-332 IEICE Transactions on Electronics, Nihon, June 2000, Vol. E83-C, No. 6, p. 950-958 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 27/095 H01L 29/812 H01L 29/778 H01L 27/06 H01L 21/027 H01L 21/8232 H01L 27 / 15 H01L 31/10 H01S 5/026

Claims (7)

(57) [Claims] 1. A method for forming a semiconductor device by processing a plurality of semiconductor layers including a second semiconductor layer and a first semiconductor layer formed on the second semiconductor layer, the method comprising: Forming a first alignment mark on the surface of the first semiconductor layer, and then forming a first semiconductor element on the first semiconductor layer by a photolithography process using the first alignment mark. Forming a second alignment mark on the surface of the second semiconductor layer using the first alignment mark,
After removing the first alignment mark and the mesa-type structure having the first alignment mark formed on the upper surface, a photolithography process using the second alignment mark is performed to perform the second semiconductor. A method of manufacturing a semiconductor device, comprising the step of forming a second semiconductor element in a layer. 2. The method for manufacturing a semiconductor device according to claim 1, wherein each of the first and second semiconductor layers is a laminated film of a plurality of semiconductor layers. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the film thickness of the first semiconductor layer is larger than the film thickness of the second semiconductor layer. 4. The first semiconductor element is an optical element or a transistor type electronic element in which electrons flow in a vertical direction,
4. The method of manufacturing a semiconductor device according to claim 3, wherein the second semiconductor element is a transistor-type electronic element or a diode-type electronic element in which electrons flow laterally. 5. The optical element is a laser or a photodiode, the transistor type electronic element in which electrons flow in the vertical direction is HBT or RTT, and the transistor type electronic element in which electrons flow in the horizontal direction is FET,
5. The method of manufacturing a semiconductor device according to claim 4, wherein the method is a HEMT or an HFET, and the diode type electronic element is a Schottky diode or an RTD. 6. The first alignment mark according to claim 1, wherein the first alignment mark is formed of a material which has a low solubility in acid and which can be easily etched by a reactive ion etching method. A method of manufacturing a semiconductor device according to any one of the above. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the material is Ti or Mo.