JP3283581B2 - Method of forming resistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a resistor.
In particular, the present invention relates to a method for forming a resistor using a semiconductor active layer.

[0002] In recent years, the use of microwave bands of 1 GHz or more, such as mobile phones and satellite broadcasting, has become active. It is difficult to make a device used in the microwave band into an IC because the gain of the device is reduced and the structure of the device is not uniform. Therefore, a HIC (Hybrid IC) in which a circuit is formed by hybridizing a single device is formed. ) Is used.

[0003] The HIC requires various know-how in circuit design and assembling, and the cost of a communication device using the HIC is increased due to a large circuit area, difficulty in automation, and an increase in cost. Was leading up.

In order to solve the above problems, MMICs (Microwave Monolithic ICs) in which all microwave circuits are incorporated on a compound semiconductor substrate such as GaAs have been used for mobile phones and the like for the first time. It is difficult to exceed the performance of the conventional HIC.

In order to improve the characteristics of the MMIC, HE
MM using MT (high electron mobility transistor) substrate
There is a need to make ICs. In order to manufacture an MMIC, it is necessary to form a transistor, a resistor, a capacitor, and an inductor on a semiconductor substrate.

As a method of forming a resistor, there is a method of using a metal thin film for a relatively small resistance, and a method of using a semiconductor active layer to obtain a relatively large resistance. An object of the present invention is to form a resistor having an arbitrary sheet resistance value by using a semiconductor active layer formed on a compound semiconductor substrate.

[0007]

2. Description of the Related Art FIG. 6 is a sectional view showing an example of the structure of a HEMT, wherein 1 is a GaAs substrate, 11 is a buffer layer, 12 is an electron transit layer, 13 is an electron supply layer, 14 is a contact layer, and 15 is a gate electrode. , 16 represents a source electrode, and 17 represents a drain electrode.

FIGS. 7A to 7C are cross-sectional views in the order of steps showing a conventional example of resistance formation using a semiconductor active layer. For example, a GaAs substrate is used as the semiconductor substrate 1 and phosphorus (P ⁺ ) is ion-implanted therein (see FIG. 7A).

Thereafter, annealing is performed, for example, at 800 ° C. to activate (see FIG. 7B). Two ohmic electrodes 5a and 5b are formed at a certain interval (see FIG. 7 (c)). The resistance value can be adjusted by the dose amount of ion implantation, the energy condition, and the dimensions and distance of the two ohmic electrodes 5a and 5b.

However, this method cannot be applied to a substrate on which HEMT is formed. This is because the HEMT heterojunction is broken when annealing is performed at a high temperature such as 800 ° C. after ion implantation for forming a resistor.

[0011]

When a resistor is formed thereon using a HEMT substrate, it is impossible to change the sheet resistance because a layer doped with impurities is formed during the formation of the HEMT. Cannot be changed at the stage of the wafer process.

In addition, the laminated structure is determined with the highest priority given to the transistor. In particular, since the electron supply layer is a layer for determining the two-dimensional electron gas concentration, it cannot be manufactured according to the resistance. Therefore, in order to change the resistance value, the area of the resistor must be changed. This means that in the case of MMIC, even if a small design change is made,
The layout of the resistor design pattern had to be changed, which required a great deal of man-hours.

In view of the above problems, an object of the present invention is to provide a method for forming a resistor having various resistance values that can coexist with a HEMT on a HEMT substrate.

[0014]

FIG. 1 is a perspective view showing a structure A (first embodiment), FIG. 2 is a perspective view showing a structure B (second embodiment), and FIG. FIGS. 4A to 4C are views showing the relationship between distance and resistance, and FIGS. 4A to 4C are perspective views showing various etching shapes.

The object is to provide a step of sequentially growing a first impurity-doped layer and a second impurity-doped layer on a compound semiconductor substrate, and having a source electrode and a drain electrode on the second impurity-doped layer. Forming a field-effect transistor including the first and second impurity-doped layers, forming two electrodes in ohmic contact with the second impurity-doped layers at an interval, By etching using the impurity-doped layer as a stopper, a part or all of the region of the second impurity-doped layer located between the two electrodes is selectively removed to remove the second impurity-doped layer from the first impurity-doped layer. of
The impurity is removed to the surface of the impurity doped layer and the second impurity is removed.
By adjusting the pattern shape and area of the
And a step of adjusting the resistance value.

The electron of the high electron mobility transistor
On the non-doped layer 2 serving as a transport layer, said first impurity doped layer 3 and the second impurity-doped layer 4, respectively, of said <br/> high electron mobility electron supply layer and the contact layer of the transistor The above problem is solved by the above-described method of forming the resistor simultaneously with the growth.

[0017]

The structure A of FIG. 1 has a second structure between the two electrodes 5a and 5b.
In the state where the impurity doped layer 4 is not removed at all, the structure B of FIG. 2 shows the second impurity doped layer 4 between the two electrodes 5a and 5b.
All selectively removed state, FIG. 4 (a) ~ (c) shows a state obtained by removing part of the second impurity doped layer 4 between the two electrodes 5a, 5b.

In these states, the two electrodes 5
The resistance between a and 5b can take various values as shown in FIG. That is, the values are the structure A, the structure B, and intermediate values. When etching the second impurity doped layer 4, the first impurity doped layer 3 acts as an etching stopper. Shape and surface product of the resistance value is etched region
Since it is possible to further adjust the two electrodes 5a, 5
The resistance can be changed over a wide range without changing the layout of b.

[0019]

FIG. 1 is a perspective view showing a structure A (first embodiment). The outline of the process is as follows.

GaAs substrate 1 on which buffer layer is formed
First, a non-doped GaAs layer having a thickness of, for example, 500 ° by MOVPE, a Si-doped (2 × 10 ¹⁸ cm ⁻³ ) AlGaAs layer having a thickness of, for example, 300 °, and a thickness of, for example, 300
A 500 ° Si-doped (2 × 10 ¹⁸ cm ⁻³ ) GaAs layer 4 is sequentially grown. AuGe / Au serving as electrodes is vapor-deposited thereon and patterned, and alloying is performed to form ohmic electrodes 5a and 5b. Patterning is ohmic electrode
The distance between 5a and 5b is set to a predetermined value, and the opposing width is, for example, 100 μm.

Non-doped GaAs layer 2, Si-doped Al
The growth of the GaAs layer 3 and the growth of the Si-doped GaAs layer 4 are performed simultaneously with the growth of the electron transit layer, the electron supply layer, and the contact layer of the HEMT. Perform at the same time.

FIG. 2 is a perspective view showing a structure B (second embodiment). In this structure, after the structure of FIG. 1 is formed, the Si-doped GaAs layer 4 is selectively etched and completely removed using the ohmic electrodes 5a and 5b as a mask.
The Si-doped AlGaAs layer 3 serves as an etching stopper.

FIG. 3 is a diagram showing the relationship between the distance between the ohmic electrodes and the resistance, and is a measured value for the structures A and B. The resistance has a linear relationship with the distance between the ohmic electrodes. The distance between the ohmic electrodes is x (μm), and the resistance is y.
(Ω), the following relational expression was obtained experimentally.

Structure A y = 1.47 + 1.50x Structure By y = 1.63 + 8.98x Further , an intermediate resistance value between structure A and structure B can be obtained by the following method . That is, when the distance between the ohmic electrodes is, for example, 20 μm, the resistance value can be adjusted between 30 and 180Ω.

FIGS. 4 (a) to 4 (c) are perspective views showing various etching shapes, and show another method for obtaining various resistance values. In these figures, the impurity doped layer 4 between the ohmic electrodes is selectively etched using a mask that exposes a part of the region between the ohmic electrodes 5a and 5b.

The etching region 6a shown in FIG. 4A limits the width of the etching region over both electrodes.
The etching region 6b in (b) is a region where the etching region is restricted to a region near both electrodes, and the etching region 6c in FIG. 4 (c) is a region where the etching region is restricted to a central portion between both electrodes. . Then, these etching regions 6a, 6b,
The impurity doped layer 4 of 6c is etched until the impurity doped layer 3 (etching stopper) is exposed.

By adjusting the shapes and areas of the etching regions 6a, 6b, 6c, various resistance values can be realized as required. If a more accurate resistance value is required, an electron beam lithography system or FIB (Focus)
By using sed ion beam), the etching area 6
Fine shape trimming of a, 6b, and 6c may be performed.

FIG. 5 is a circuit diagram showing an example of an MMIC to which the present invention is applied. An input matching resistor R is connected to the input terminal to the FET.
₁ and to for example 50Ω resistor, a feedback resistor R
₂ to e.g. resistor 200 [Omega, and the sum of the resistance R ₃ to obtain a constant-voltage power supply for example 10Ω resistor 3
An example using three resistors is shown. The laminated structure of these resistors is the same as the laminated structure of the FET, and can be formed in the same step together with the formation of the FET.

According to the present invention, when the resistance value of the MMIC to use several different resistance, when change occurs in the resistance value due to circuit design, a resistor etching pattern be a pattern layout without changing the by the change, it is possible to deal with it.

[0030]

As described above, according to the present invention,
In the case of the circuit design in the MMIC, it is possible to flexibly cope with the change of the resistance value by the etching process without changing the pattern layout of the resistor.

When the present invention is applied to MMIC resistance formation, it contributes to reduction of man-hours and improvement of resistance value accuracy. In particular,
It has a great effect in the development of a new MMIC.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a structure A (first embodiment).

FIG. 2 is a perspective view showing a structure B (second embodiment).

FIG. 3 is a diagram illustrating a relationship between a distance between ohmic electrodes and a resistance.

4 (a) to 4 (c) are perspective views showing various etching shapes.

FIG. 5 is a circuit diagram showing an example of an MMIC to which the present invention has been applied.

FIG. 6 is a cross-sectional view illustrating a structural example of a HEMT.

7 (a) to 7 (c) are cross-sectional views in the order of steps showing a conventional example of resistance formation using a semiconductor active layer.

[Explanation of symbols]

 1 is a compound semiconductor substrate, GaAs substrate 2 is a non-doped layer, i-GaAs 3 is a first impurity-doped layer, n-AlGaAs 4 is a second impurity-doped layer, and n-GaAs 5a, 5b is an ohmic electrode, and AuGe / Au 6a, 6b, 6c is an etching region 11, a buffer layer 12, an electron transit layer 13, an electron supply layer 14, a contact layer 15, a gate electrode 16, a source electrode 17, and a drain electrode.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/778 29/812 (72) Inventor Hiroshi Mino 1000, Azagami Azagami, Showa-cho, Nakakoma-gun, Yamanashi Prefecture Fujitsu Quantum Device Co., Ltd. (56) References JP-A-63-158864 (JP, A)

Claims (2)

(57) [Claims] A step of sequentially growing a first impurity-doped layer and a second impurity-doped layer on a compound semiconductor substrate; and a step of forming a source electrode and a drain electrode on the second impurity-doped layer. Forming a field-effect transistor including the first and second impurity-doped layers; forming two electrodes in ohmic contact with the second impurity-doped layers at an interval; By etching using the layer as a stopper, a part or all of the second impurity-doped layer located between the two electrodes is selectively removed to remove the second impurity-doped layer .
Removing the pure doped layer to the surface of the first doped layer;
And the pattern shape of the second impurity-doped layer and
Adjusting the resistance value by adjusting the area . 2. The method according to claim 1, wherein the first impurity-doped layer and the second impurity-doped layer are formed on a non-doped layer serving as an electron transit layer of the high electron mobility transistor, respectively. 2. The method for forming a resistor according to claim 1, wherein the method is performed simultaneously with the growth of the contact layer.