JPH0677019A - Formation of resistor - Google Patents

Abstract

PURPOSE:To form a resistor suitable for MMIC by the method for formation of a resistor to be used for a semiconductor active layer. CONSTITUTION:This resistor forming method is composed of a process in which a non-doped layer 1, the first impurity-doped layer 3 and the second impurity- doped layer 4 are grown sucessively on a compound semiconductor substrate 1, a process in which two electrodes 5a and 5b to be used to ohmic contact are formed leaving an interval on the second impurity-doped layer 4, and another process in which a resistance value is adjusted by selectively etching a part or the whole part of the second impurity-doped layer 4 located between the two electrodes 5a and 5b. Also, the growth of the non-doped layer 2, the first impurity-doped layer 3 and the second impurity-doped layer 4 is conducted simultaneously with the growth of the electron transit layer of a high electron mobility transistor, an electron feeding layer and a contact layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance forming method,
In particular, it relates to a method of forming a resistor using a semiconductor active layer.

In recent years, the use of microwave bands of 1 GHz or higher, such as mobile phones and satellite broadcasting, has become active. It is difficult to make a device used in the microwave band into an IC because the gain of the device is lowered and the structure of the device becomes non-uniform. Therefore, a HIC (Hybrid IC) is formed by hybridizing a single device to form a circuit. ) Is used.

The HIC requires various know-how in the circuit design and assembly, and the cost of the communication device using the HIC is increased because the circuit area becomes large, automation is difficult, and the cost increases. Was inviting a rise.

In order to solve the above problems, an MMIC (Microwave Monolithic IC) in which all microwave circuits are incorporated on a compound semiconductor substrate such as GaAs has been used for a mobile phone for the first time. Therefore, it is difficult to exceed the performance of the conventional HIC.

In order to improve the characteristics of MMIC, HE
MM using MT (High Electron Mobility Transistor) substrate
It is necessary to make an IC. In order to manufacture the MMIC, it is necessary to form transistors, resistors, capacitors and inductors on the semiconductor substrate.

As a method of forming a resistor, there is a method of using a metal thin film for a relatively small resistance, and a method of utilizing a semiconductor active layer for obtaining a relatively large resistance value. An object of the present invention is to form a resistor having an arbitrary sheet resistance value by using a semiconductor active layer formed on a compound semiconductor substrate.

[0007]

2. Description of the Related Art FIG. 6 is a cross-sectional view showing an example of the structure of a HEMT. 1 is a GaAs substrate, 11 is a buffer layer, 12 is an electron transit layer, 13 is an electron supply layer, 14 is a contact layer, and 15 is a gate electrode. Reference numeral 16 indicates a source electrode, and 17 indicates a drain electrode.

FIGS. 7A to 7C are sectional views in order of steps showing a conventional example of resistance formation using a semiconductor active layer. For example, a GaAs substrate is used as the semiconductor substrate 1, and phosphorus (P ⁺ ) ions are implanted therein (see FIG. 7A).

Thereafter, for example, annealing is performed at 800 ° C. for activation (see FIG. 7 (b)). Two ohmic electrodes 5a and 5b are formed at a certain interval (see FIG. 7 (c)). The resistance value can be adjusted by the dose amount of ion implantation, the energy condition, and the size and distance of the two ohmic electrodes 5a and 5b.

However, this method cannot be applied to the HEMT-formed substrate. This is because the HEMT heterojunction is broken by annealing at a high temperature such as 800 ° C. after ion implantation for forming the resistance.

[0011]

When a HEMT substrate is used to form a resistance therein, it is impossible to change the sheet resistance because a layer doped with impurities is formed during the HEMT formation. It is also impossible to change the value at the stage of the wafer process.

The laminated structure is determined with the transistor as the highest priority, and in particular, the electron supply layer is a layer that determines the two-dimensional electron gas concentration, so that it cannot be manufactured according to the resistance. Therefore, the resistance area must be changed in order to change the resistance value. This means that in the case of MMIC, even if a small design change is made,
The layout of the resistor design pattern had to be changed, which required a great deal of man-hours.

In view of the above problems, it is an object of the present invention to provide a method for forming a resistor which can coexist with HEMT on a HEMT substrate and has various resistance values.

[0014]

FIG. 1 is a perspective view showing a structure A (first embodiment), FIG. 2 is a perspective view showing a structure B (second embodiment), and FIG. 3 is between ohmic electrodes. FIGS. 4A to 4C are perspective views showing various etching shapes, showing the relationship between distance and resistance.

[0015] The above-mentioned problem is to grow the non-doped layer 2, the first impurity-doped layer 3 and the second impurity-doped layer 4 in sequence on the compound semiconductor substrate 1, and to make ohmic contact with the second impurity-doped layer 4. A step of forming two electrodes 5a, 5b with a space between them, and a step of selectively or partially etching the second impurity-doped layer 4 between the two electrodes 5a, 5b to adjust the resistance value And a method of forming a resistor having

Further, the growth of the non-doped layer 2, the first impurity-doped layer 3 and the second impurity-doped layer 4 is carried out with respect to the growth of the electron transit layer, the electron supply layer and the contact layer of the high electron mobility transistor, respectively. This is solved by the above-mentioned method of forming the resistance which is performed at the same time.

[0017]

The structure A of FIG. 1 is a state in which the second impurity-doped layer 4 between the two electrodes 5a and 5b is not removed at all, and the structure B of FIG. 2 is a second impurity-doped layer between the two electrodes 5a and 5b. 4 (a) to 4 (c) are the two electrodes
It shows a state in which the second impurity-doped layer 4 between a and 5b is partially removed.

In these states, the two electrodes 5a, 5b
The resistance between them can take various values as shown in FIG. That is, the values are Structure A, Structure B, and values in between. When etching the second impurity-doped layer 4, the second
The impurity doped layer 3 acts as an etching stopper. Since the resistance value can be adjusted by the shape and area of the etched region and the etching depth, the resistance can be changed over a wide range without changing the layout of the two electrodes 5a and 5b.

[0019]

1 is a perspective view showing a structure A (first embodiment). The outline of the process is as follows.

GaAs substrate 1 on which a buffer layer is formed
For example, by MOVPE method, a non-doped GaAs layer with a thickness of, for example, 500 Å, a Si-doped (2 × 10 ¹⁸ cm ^-3 ) AlGaAs layer with a thickness of, for example, 300 Å 3, and a thickness of, for example,
A 500 Å Si-doped (2 × 10 ¹⁸ cm ⁻³ ) GaAs layer 4 is sequentially grown. AuGe / Au to be an electrode is vapor-deposited thereon, patterned, and alloyed to form ohmic electrodes 5a and 5b. Ohmic electrode for patterning
The distance between 5a and 5b is a predetermined value, and the opposing width is 100 μm, for example.

Non-doped GaAs layer 2, Si-doped Al
The GaAs layer 3 and the Si-doped GaAs layer 4 are grown simultaneously with the growth of the electron transit layer, electron supply layer, and contact layer of the HEMT, and ohmic electrodes 5a and 5b are formed with the source / drain electrodes of the HEMT. Do at the same time.

FIG. 2 is a perspective view showing structure B (second embodiment). In this structure, after the structure shown in FIG. 1 is formed, the ohmic electrodes 5a and 5b are used as masks to selectively remove the Si-doped GaAs layer 4 by etching.
The Si-doped AlGaAs layer 3 serves as an etching stopper.

FIG. 3 is a diagram showing the relationship between the distance between the ohmic electrodes and the resistance, which is the measured value for the structure A and the structure B. The resistance has a linear relationship with the distance between the ohmic electrodes, the distance between the ohmic electrodes is x (μm), and the resistance value is y.
(Ω), the following relational expression was obtained experimentally.

Structure A y = 1.47 + 1.50x Structure B y = 1.63 + 8.98x If the etching amount is adjusted and the Si-doped GaAs layer 4 is etched to an intermediate depth, a resistance value between the structures A and B is obtained. Can be obtained. That is, assuming that the distance between the ohmic electrodes is 20 μm, the resistance value can be adjusted within the range of 30 to 180Ω.

4 (a) to 4 (c) are perspective views showing various etching shapes and show another method of obtaining various resistance values. In these figures, the impurity-doped layer 4 between the ohmic electrodes is selectively etched using a mask exposing a part of the region between the ohmic electrodes 5a and 5b.

The etching region 6a of FIG. 4 (a) limits the width of the etching region over both electrodes.
The etching area 6b in (b) is the etching area limited to the area close to both electrodes, and the etching area 6c in FIG. 4 (c) is the etching area limited to the central portion between both electrodes. . Then, these etching regions 6a, 6b,
The impurity-doped layer 4 of 6c is etched until the impurity-doped layer 3 (etching stopper) is exposed.

By adjusting the shapes and areas of the etching regions 6a, 6b, 6c, various resistance values can be realized according to requirements. When a more accurate resistance value is required, an electron beam lithography system or FIB (Focu
sed Ion Beam)
Fine shape trimming of a, 6b, and 6c may be performed.

FIG. 5 is a circuit diagram showing an example of an MMIC to which the present invention is applied. Input matching resistor R at the input to the FET
_{As 1} , for example, a resistor of 50Ω, a feedback resistor R
₂ as a resistance of 200 Ω, and resistance R ₃ for obtaining a constant voltage power supply as a resistance of ₃ Ω, for example, a total of 3
An example in which one resistor is used is shown. The laminated structure of these resistors is the same as the laminated structure of the FET, and can be formed in the same step together with the formation of the FET.

According to the present invention, in the case of an MMIC using several resistors having different resistance values, when the resistance value is changed by the circuit design, the etching pattern and the etching pattern can be changed without changing the pattern layout of the resistor. This can be dealt with by changing the etching conditions.

[0030]

As described above, according to the present invention,
In the case of circuit design in MMIC, it is possible to flexibly deal with the change of the resistance value by the etching process without changing the pattern layout of the resistor.

When the present invention is applied to the resistance formation of MMIC, it contributes to reduction of man-hours and improvement of accuracy of resistance value. In particular,
It has a great effect on the development of a new MMIC.

[Brief description of drawings]

FIG. 1 is a perspective view showing a structure A (first embodiment).

FIG. 2 is a perspective view showing a structure B (second embodiment).

FIG. 3 is a diagram showing a relationship between a distance between ohmic electrodes and resistance.

4A to 4C are perspective views showing various etching shapes.

FIG. 5 is a circuit diagram showing an example of an MMIC to which the present invention is applied.

FIG. 6 is a cross-sectional view showing a structural example of a HEMT.

7A to 7C are cross-sectional views in order of the processes, showing a conventional example of resistance formation using a semiconductor active layer.

[Explanation of symbols]

 1 is a compound semiconductor substrate, GaAs substrate 2 is a non-doped layer, i-GaAs 3 is a first impurity-doped layer, n-AlGaAs 4 is a second impurity-doped layer, and n-GaAs 5a, 5b is an ohmic electrode, and AuGe / Au 6a, 6b, 6c are etching regions 11 buffer layer 12 electron transit layer 13 electron supply layer 14 contact layer 15 gate electrode 16 source electrode 17 drain electrode

Claims (2)

[Claims] 1. A non-doped layer on a compound semiconductor substrate (1)
(2), a step of sequentially growing the first impurity-doped layer (3) and the second impurity-doped layer (4), and two electrodes (5a, 5a, which make ohmic contact with the second impurity-doped layer (4)). 5b) at intervals, and the second impurity-doped layer (4) between the two electrodes (5a, 5b)
And a step of adjusting the resistance value by selectively etching a part or all of the above. 2. The non-doped layer (2), the first impurity-doped layer (3), and the second impurity-doped layer (4) are grown in the electron transit layer and the electron supply layer of the high electron mobility transistor, respectively. 2. The method for forming a resistor according to claim 1, wherein the contact layer and the contact layer are grown at the same time.