KR19980020702A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR19980020702A KR19980020702A KR1019960039283A KR19960039283A KR19980020702A KR 19980020702 A KR19980020702 A KR 19980020702A KR 1019960039283 A KR1019960039283 A KR 1019960039283A KR 19960039283 A KR19960039283 A KR 19960039283A KR 19980020702 A KR19980020702 A KR 19980020702A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 소자에 관한 것으로, 특히 소자의 특성을 향상시키도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for improving the characteristics of the device.
이와같은 본 발명의 반도체 소자의 제조방법은 제1도전형 반도체 기판을 준비하는 단계; 상기 제1도전형 반도체 기판상에 제1절연막을 형성하는 단계; 상기 제1절연막상에 일정한 간격을 갖는 복수개의 제2절연막을 형성하는 단계; 상기 제2절연막 사이에 상기 제2절연막과 일정한 간격을 갖는 게이트 전극을 형성하는 단계; 상기 복수개의 제2절연막과 게이트 전극을 마스크로 하여 기판내에 제2도전형 저농도 불순물 영역을 형성하는 단계; 상기 복수개의 제2절연막과 게이트 전극을 마스크로 하여 필드이온을 주입하여 필드 산화막을 형성하는 단계; 상기 제2절연막을 제거하는 단계; 상기 제2절연막이 제거된 부분에 제2도전형 고농도 불순물 영역을 형성하는 단계를 포함하여 형성함에 그 특징이 있다.Such a method of manufacturing a semiconductor device of the present invention comprises the steps of preparing a first conductive semiconductor substrate; Forming a first insulating film on the first conductive semiconductor substrate; Forming a plurality of second insulating films having a predetermined interval on the first insulating film; Forming a gate electrode having a predetermined distance from the second insulating layer between the second insulating layers; Forming a second conductive low concentration impurity region in the substrate using the plurality of second insulating films and the gate electrodes as masks; Forming field oxide films by implanting field ions using the plurality of second insulating films and gate electrodes as masks; Removing the second insulating layer; And forming a second conductive high concentration impurity region in a portion where the second insulating film is removed.
Description
본 발명은 반도체 소자에 관한 것으로 특히, 소자의 특성을 향상시키도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a method for manufacturing a semiconductor device in which the characteristics of the device are improved.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a-도 1c는 종래의 반도체 소자의 제조방법을 나타낸 레이아웃도이고, 도 2a-도 2e는 도 1의 A-A'에 따른 공정단면도이다.1A to 1C are layout views illustrating a conventional method of manufacturing a semiconductor device, and FIGS. 2A to 2E are cross-sectional views of a process according to AA ′ of FIG.
먼저, 도 1a와 도 2a에 도시된 바와 같이 반도체 기판(11)상에 후공정에서 LOCOS(LOCal Oxidation of Silicon) 공정을 할때 질화막에 의해 유발되는 상기 반도체 기판(11)이 스트레스(Stress)를 줄이기 위해 완충(Cushion)역할을 하는 산화막(12)을 형성한다.First, as illustrated in FIGS. 1A and 2A, when the LOCOS process is performed on the semiconductor substrate 11 in a later process, the semiconductor substrate 11 induced by the nitride film may be stressed. In order to reduce, an oxide film 12 serving as a cushion is formed.
그리고 상기 산화막(12)상에 질화막(13)을 형성하고, 상기 질화막(13)상에 제1감광막(도면에 도시하지 않음)을 도포한 후, 상기 제1감광막을 노광 및 현상공정으로 패터닝(Pattering)한다.After the nitride film 13 is formed on the oxide film 12 and a first photosensitive film (not shown) is applied on the nitride film 13, the first photosensitive film is patterned by an exposure and development process ( Pattering).
이어서, 상기 패터닝된 제1감광막을 마스크로 하여 상기 질화막(13)을 선택적으로 제거한다.Subsequently, the nitride film 13 is selectively removed using the patterned first photoresist film as a mask.
이어, 도 1b와 도 2b에 도시된 바와 같이 상기 질화막(13)을 포함한 전면에 제2감광막(14)을 도포한 후, 상기 제2감광막(14)을 노광 및 현상공정으로 패터닝한다.Subsequently, as shown in FIGS. 1B and 2B, the second photosensitive film 14 is coated on the entire surface including the nitride film 13, and then the second photosensitive film 14 is patterned by an exposure and development process.
다음에, 도 1c와 도 2c에 도시된 바와 같이 상기 패터닝된 제2감광막(14)을 마스크로 하여 상기 질화막(13)을 선택적으로 제거하여 복수개의 질화막 패턴(13a)을 형성한다.Next, as illustrated in FIGS. 1C and 2C, the nitride film 13 is selectively removed using the patterned second photosensitive film 14 as a mask to form a plurality of nitride film patterns 13a.
그리고 상기 질화막 패턴(13a)을 마스크로 하여 전면에 저농도 불순물 이온을 주입하여 상기 질화막 패턴(13a) 양측의 반도체 기판(11)내에 저농도 불순물 영역(15)을 형성한다.A low concentration impurity region 15 is formed in the semiconductor substrate 11 on both sides of the nitride layer pattern 13a by implanting low concentration impurity ions into the entire surface using the nitride layer pattern 13a as a mask.
이어서, 도 2d에 도시된 바와같이 상기 질화막 패턴(13a)을 마스크로하여 전면에 필드이온을 주입한 후, 고온에서 성장시키므로써 필드 산화막(16)을 형성하고, 상기 질화막 패턴(13a)을 제거한다.Subsequently, as shown in FIG. 2D, field ions are implanted into the entire surface using the nitride film pattern 13a as a mask, and then grown at a high temperature to form a field oxide film 16, and the nitride film pattern 13a is removed. do.
이어서, 전면에 게이트 전극용 폴리 실리콘을 형성하고, 상기 폴리 실리콘상에 제3감광막(도면에 도시하지 않음)을 도포한 후, 상기 제3감광막을 노광 및 현상공정으로 패터닝하고, 상기 패터닝된 제3감광막을 마스크로 하여 상기 게이트 전극용 폴리 실리콘을 선택적으로 제거하여 게이트 전극(17)을 형성한다.Subsequently, polysilicon for gate electrodes is formed on the entire surface, a third photoresist film (not shown) is applied onto the polysilicon, and the third photoresist film is patterned by an exposure and development process, and the patterned agent The gate electrode 17 is formed by selectively removing the polysilicon for the gate electrode using the three photosensitive film as a mask.
그리고 상기 게이트 전극(17)을 마스크로 하여 전면에 고농도 불순물 이온을 주입하여 상기 게이트 전극(17) 양측의 상기 반도체 기판(11) 내에 고농도 불순물 영역(18)을 형성한다.A high concentration impurity region 18 is formed in the semiconductor substrate 11 on both sides of the gate electrode 17 by implanting high concentration impurity ions onto the entire surface using the gate electrode 17 as a mask.
그러나 이와 같은 종래의 반도체 소자의 제조방법에 있어서 다음과 같은 문제점이 있었다.However, such a conventional method of manufacturing a semiconductor device has the following problems.
첫째, 활성영역의 질화막을 선택적으로 제거하여 질화막 패턴을 형성할 때, 하부의 산화막까지 식각이 되어 기판에도 손상(Damage)을 준다.First, when the nitride film of the active region is selectively removed to form a nitride film pattern, the lower oxide film is etched to damage the substrate.
둘째, 필드 산화막의 형성공정에서 화이트 리본(White Ribbon)이 발생하여 소자의 특성이 저하된다.Second, a white ribbon is generated in the process of forming the field oxide film, thereby deteriorating the characteristics of the device.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 안정된 기판과 소자의 특성을 향상시키도록 한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a semiconductor device to improve the characteristics of the stable substrate and the device to solve the above problems.
도 1a-도 1c는 종래의 반도체 소자의 제조방법을 나타낸 레이아웃도.1A to 1C are layout views showing a conventional method for manufacturing a semiconductor device.
도 2a-도 2e는 도 1의 A-A'선에 따른 종래의 반도체 소자의 제조방법을 나타낸 공정단면도.2A to 2E are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device along the line AA ′ of FIG. 1.
도 3a-도 3c는 본 발명의 반도체 소자의 제조방법을 나타낸 레이아웃도.3A to 3C are layout views showing a method of manufacturing a semiconductor device of the present invention.
도 4a-도 4e는 도 3의 B-B'선에 따른 본 발명의 반도체 소자의 제조방법을 나타낸 공정단면도.4A to 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention taken along the line BB ′ of FIG. 3.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21:반도체기판22:산화막21: semiconductor substrate 22: oxide film
23:질화막24:폴리 실리콘23: nitride film 24: polysilicon
25:제2감광막26:게이트 전극25: second photosensitive film 26: gate electrode
27:저농도 불순물 영역28:필드 산화막27: low concentration impurity region 28: field oxide film
29:고농도 불순물 영역29: high concentration impurity region
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 제1도전형 반도체 기판을 준비하는 단계; 상기 제1도전형 반도체 기판상에 제1절연막을 형성하는 단계; 상기 제1절연막상에 일정한 간격을 갖는 복수개의 제2절연막을 형성하는 단계; 상기 제2절연막 사이에 상기 제2절연막과 일정한 간격을 갖는 게이트 전극을 형성하는 단계; 상기 복수개의 제2절연막과 게이트 전극을 마스크로 하여 기판내에 제2도전형 저농도 불순물 영역을 형성하는 단계; 상기 복수개의 제2절연막과 게이트 전극을 마스크로 하여 필드이온을 주입하여 필드 산화막을 형성하는 단계; 상기 제2절연막을 제거하는 단계; 상기 제2절연막이 제거된 부분에 제2도전형 고농도 불순물 영역을 형성하는 단계를 포함하여 형성함을 특징으로 한다.Method for manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of preparing a first conductive semiconductor substrate; Forming a first insulating film on the first conductive semiconductor substrate; Forming a plurality of second insulating films having a predetermined interval on the first insulating film; Forming a gate electrode having a predetermined distance from the second insulating layer between the second insulating layers; Forming a second conductive low concentration impurity region in the substrate using the plurality of second insulating films and the gate electrodes as masks; Forming field oxide films by implanting field ions using the plurality of second insulating films and gate electrodes as masks; Removing the second insulating layer; And forming a second conductive high concentration impurity region in a portion where the second insulating film is removed.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 3a-도 3c는 본 발명의 반도체 소자의 제조방법을 나타낸 레이아웃도이고, 도 4a-도 4e는 도 3의 B-B'선에 따른 본 발명의 반도체 소자의 제조방법을 나타낸 공정단면도이다.3A to 3C are layout views illustrating a method of manufacturing a semiconductor device of the present invention, and FIGS. 4A to 4E are process cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention along line BB ′ of FIG.
먼저, 도 3a와 도 4a에 도시된 바와 같이 반도체 기판(21)상에 후공정에서 LOCOS 공정을 할때 질화막에 의해 유발되는 상기 반도체 기판(21)의 스트레스(Stress)를 줄이기 위해 완충(Cushion)역할을 하는 산화막(22)을 형성한다.First, as shown in FIGS. 3A and 4A, in order to reduce the stress of the semiconductor substrate 21 caused by the nitride film when the LOCOS process is performed on the semiconductor substrate 21 in a later process, cushioning is performed. The oxide film 22 which functions is formed.
이어, 상기 산화막(22)상에 질화막(23)을 형성하고 상기 질화막(23)상에 제1감과막(도면에 도시되지 않음)을 도포한 후, 감광막을 노광 및 현상공정으로 패터닝(Pattering)한다.Subsequently, a nitride film 23 is formed on the oxide film 22 and a first photosensitive film (not shown) is applied on the nitride film 23, and then the photosensitive film is patterned by an exposure and development process. do.
그리고 상기 패터닝된 제1감광막을 마스크로 하여 상기 질화막(23)이 일정한 간격을 갖도록 선택적으로 제거한다.The nitrided film 23 is selectively removed to have a predetermined interval using the patterned first photoresist film as a mask.
이어서, 도 3b와 도 4b에 도시된 바와 같이 상기 질화막을 포함한 전면에 폴리 실리콘(24)을 형성한다.3B and 4B, polysilicon 24 is formed on the entire surface including the nitride film.
그리고 상기 폴리 실리콘(24)상에 제2감광막(25)을 도포한 후, 상기 제2감광막(25)을 노광 및 현상공정으로 패터닝한다.After the second photosensitive film 25 is coated on the polysilicon 24, the second photosensitive film 25 is patterned by an exposure and development process.
이어서, 도 3c와 도 4c에 도시된 바와 같이 상기 패터닝된 제2감광막(25)을 마스크로하여 상기 폴리 실리콘(24)을 선택적으로 제거하여 게이트 전극(26)을 형성하고, 상기 제4감광막(25)을 제거한다.Subsequently, as shown in FIGS. 3C and 4C, the polysilicon 24 is selectively removed using the patterned second photoresist layer 25 as a mask to form a gate electrode 26, and the fourth photoresist layer ( 25) Remove.
그리고 상기 게이트 전극(26)과 질화막(23)을 마스크로 하여 저농도 불순물 이온을 주입하여 양측의 반도체 기판(21)에 저농도 불순물 영역(27)을 형성한다.Low concentration impurity ions are implanted using the gate electrode 26 and the nitride film 23 as a mask to form the low concentration impurity regions 27 in the semiconductor substrates 21 on both sides.
이어서, 도 4d에 도시된 바와 같이 상기 게이트 전극(26)과 질화막(23)을 마스크로하여 전면에 필드이온을 주입한 후, 고온에서 성장시키므로써 필드 산화막(28)을 형성하고, 상기 질화막(23)은 제거한다.Subsequently, as shown in FIG. 4D, field ions are implanted into the entire surface using the gate electrode 26 and the nitride film 23 as a mask, and then grown at a high temperature to form a field oxide film 28 to form the nitride film ( 23) Remove.
그리고 도 4e에 도시된 바와 같이 상기 게이트 전극(26)을 마스크로 하여 전면에 고농도 불순물 이온을 주입하여 상기 게이트 전극(26) 양측의 상기 반도체 기판(21)내에 고농도 불순물 영역(29)을 형성한다.As shown in FIG. 4E, high concentration impurity ions are implanted into the entire surface using the gate electrode 26 as a mask to form a high concentration impurity region 29 in the semiconductor substrate 21 on both sides of the gate electrode 26. .
이상에서 설명한 바와 같이 본 발명의 반도체 소자의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the manufacturing method of the semiconductor device of the present invention has the following effects.
첫째, 질화막 식각시 게이트 전극이 형성될 부분만 감광막을 남기고 식각하기 때문에 기판의 손상이 없다.First, when the nitride film is etched, only the portion where the gate electrode is to be formed is etched leaving the photosensitive film, thereby preventing damage to the substrate.
둘째, 질화막과 게이트 전극을 마스크로 하여 필드이온을 주입하기 때문에 화이트 리본(White Ribbon)이 제거되어 소자의 특성을 향상시킨다.Second, since field ions are implanted using the nitride film and the gate electrode as masks, white ribbon is removed to improve device characteristics.
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