CN107527955A - The preparation method of polysilicon autoregistration raceway groove - Google Patents
The preparation method of polysilicon autoregistration raceway groove Download PDFInfo
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- CN107527955A CN107527955A CN201710554326.2A CN201710554326A CN107527955A CN 107527955 A CN107527955 A CN 107527955A CN 201710554326 A CN201710554326 A CN 201710554326A CN 107527955 A CN107527955 A CN 107527955A
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- polysilicon
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- raceway groove
- cushion
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 60
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 17
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000002347 injection Methods 0.000 claims description 16
- 239000007924 injection Substances 0.000 claims description 16
- 150000002500 ions Chemical class 0.000 claims description 11
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 229910002026 crystalline silica Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 abstract description 5
- 230000008021 deposition Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of preparation method of polysilicon autoregistration raceway groove, by in one layer of cushion of substrate surface pre-deposition, then in growing polycrystalline silicon layer thereon as ion implanting barrier layer and autoregistration oxide layer, and one layer of dielectric layer is deposited on its surface, as second layer ion implanting barrier layer.After ion implanting forms p-well or N traps, by polysilicon oxidation self-registered technology, N is then injected into+Or P+Afterwards, MOSFET channel structure is formed.The present invention is by strictly controlling buffer growth, the process conditions and thickness of polysilicon and cvd dielectric layer, avoid the too big caused surface undulation of polysilicon grain, etched line bar edge roughness problem caused by entering, the yield rate of device can be greatly improved, and the preparation for narrower channel device in next step provides Process ba- sis.
Description
Technical field
The invention belongs to field of semiconductor devices, more particularly to a kind of preparation method of polysilicon autoregistration raceway groove.
Background technology
Carbofrax material, relative to traditional silicon and GaAs material, has forbidden band wide as third generation semi-conducting material
Degree is big, breakdown field strength field is high, saturation drift velocity is big and a series of material superior functions such as thermal conductivity is big.Based on carborundum
The unique material property of material, make it that there is huge answer in high frequency, high-power, high pressure and high temperature resistant power electronic devices field
Use advantage.In terms of Switching Power Supply, new energy power vehicle and track traffic in high end performance, silicon carbide-based field effect transistor
Pipe (MOSFET) device has huge application advantage, and it can effectively reduce system dimension, weight and to HTHP
The demand of work.
In order to improve the saturation current density of silicon carbide-based MOSFET element, shorten length of effective channel and necessitate choosing
Select, the nearest channel width for generally believing silicon carbide-based MOSFET element at present is 0.5um, but it is to photoetching and alignment precision
Too high requirement is proposed, adds device technology cost.Self-registered technology prepares MOSFET channel can be with point-device reality
Now to the control of channel length and position, technique is simply and stably.Polysilicon oxidation is that current use must compare widely from right
Quasi- raceway groove preparation method, but based on the needs of energetic ion injection mask, it requires to grow thicker polysilicon layer, so as to lead
Cause polysilicon grain size it is excessive, further result in etching back edge smoothness and oxidation after edge pattern quality compared with
Difference.
The content of the invention
Goal of the invention：For problem above, the present invention proposes a kind of by reducing polysilicon grain size, raising etching circle
Face pattern, so as to improve the polysilicon autoregistration raceway groove preparation side that self-registered technology prepares ditch trace consistency and technology stability
Method.
Technical scheme：To realize the purpose of the present invention, the technical solution adopted in the present invention is：A kind of polysilicon autoregistration
The preparation method of raceway groove, specifically includes following steps：
(1) grown buffer layer on silicon carbide epitaxial layers；
(2) growing polycrystalline silicon layer on the buffer layer；
(3) metallization medium layer on the polysilicon layer；
(4) by photoetching p-well or N trap figures, then etch media layer, polysilicon layer and cushion, form p-well or N traps
Injection window；
(5) multiple energetic ion injection technology, shape are passed through as injection mask by dielectric layer, polysilicon layer and cushion
Into p-well or N well region；
(6) surface media is removed；
(7) high-temperature oxydation polysilicon layer and cushion, oxide layer is formed；
(8) by multiple energetic ion injection technology, N+ or P+ source regions are formed；It is ditch to inject mask stand out twice
Road.
Beneficial effect：On the one hand the present invention is improved by introducing buffer growth and polysilicon surface cvd dielectric layer
Polycrystalline silicon material growth quality, reduces crystallite dimension；On the other hand the demand to polysilicon thickness is reduced.Pass through multilayer material
Material etching, go the technology such as polysilicon oxidation after medium, improve etching interface pattern and polysilicon lines and oxidation after lines
Uniformity.The present invention realizes to channel dimensions and uniformity to be accurately controlled, and improves the yield rate and device of device
Reliability.And the optimization that the technology etches to polycrystalline silicon growth so that self-registered technology can apply to the ditch of more narrow linewidth
In prepared by road.
Brief description of the drawings
Fig. 1 is the schematic diagram of the structure obtained on silicon carbide epitaxial layers after grown buffer layer；
Fig. 2 is the schematic diagram of the structure obtained on the buffer layer after growing polycrystalline silicon layer；
Fig. 3 is the schematic diagram of the structure obtained on growing polycrystalline silicon layer after deposition injection block media layer；
Fig. 4 is the schematic diagram for being layered the structure after etch media layer, polysilicon layer and cushion；
Fig. 5 is the schematic diagram for the p-well or N well region structure to be formed；
Fig. 6 is the schematic diagram for removing the structure obtained after surface injection mask medium layer；
Fig. 7 is the schematic diagram of the increased structure of polysilicon layer volume after high-temperature oxydation polysilicon layer；
Fig. 8 is the schematic diagram of the structure for the N+ or P+ source regions and raceway groove to be formed.
Embodiment
Technical scheme is further described with reference to the accompanying drawings and examples.
The preparation method of polysilicon autoregistration raceway groove of the present invention, comprises the following steps：
(1) as shown in figure 1, on silicon carbide epitaxial layers 1 grown buffer layer 2, cushion 2 can be non-crystalline silicon, annealing after
The materials such as non-crystalline silicon, silica or silicon nitride, its thickness range are 20-100nm, and it functions as the slow of polycrystalline silicon growth
Layer is rushed, to reduce polycrystalline silicon growth crystallite dimension, avoids the roughness at etching polysilicon edge.
(2) as shown in Fig. 2 growing polycrystalline silicon layer 3 on the buffer layer 2.
(3) as shown in figure 3, metallization medium layer 4, dielectric layer 4 can be silica or silicon nitride etc. on polysilicon layer 3
Material, its thickness range are 200-1000nm, and it acts on right and wrong crystal silicon layer collectively as p-well or N trap ion implantings barrier layer.
The presence of dielectric layer 4 can reduce energetic ion injection to the demand of polysilicon barrier layer thickness, avoid because of polycrystalline silicon growth
Crystallite dimension increase caused by blocked up.
(4) as shown in figure 4, by photoetching p-well or N trap figures, then etch media layer 4, polysilicon layer 3 and cushion 2,
Form the injection window of p-well or N traps.Layering etching technics to trilaminate material, the pattern of etching polysilicon lines can be improved,
Improve channel dimensions uniformity.
(5) as shown in figure 5, by dielectric layer 4, polysilicon layer 3 and cushion 2 as injection mask, by multiple high energy from
Sub- injection technology, form p-well or N well region 5.Multilayer material is selected to be improved to ion implanting as ion implantation mask
Barrier effectiveness, further improve ion implantation energy, so as to form deeper p-well or N trap ion implanting depth, improve
The breakdown characteristics and reliability of MOSFET element.
(6) as shown in fig. 6, removing surface media 4；
(7) as shown in fig. 7, high-temperature oxydation polysilicon layer 3, forms oxide layer 6, volume can expand after it is aoxidized, original P
Trap or N traps ion implanted region can reduce.
Because N+ or P+ source regions are low to injection depth requirements, i.e., ion implantation energy is relatively low, so as to injecting mask thickness
Degree requires relatively low, can be individually using the polysilicon after oxidation as mask.Remove the rear oxidation polysilicon of dielectric layer 4, Ke Yiti
The oxidation efficiency and uniformity of high polysilicon, improve the uniformity and uniformity of raceway groove.
(8) as shown in figure 8, by multiple energetic ion injection technology, N+ or P+ source regions 7 are formed, wherein injecting twice
Mask stand out is the raceway groove needed for us.
Pass through different oxidization times, it is possible to achieve the preparation of a variety of channel widths.By above cushion 2, dielectric layer 4
Etc. series of process, it can greatly reduce the crystallite dimension of polysilicon layer 3, the uniformity and surface for improving polycrystalline silicon material are put down
The optimization of whole degree and etching lines.Polysilicon oxidation interface based on process above is more smooth, improves the finished product of device
Rate, and can realize prepared by the raceway groove of more narrow linewidth by changing the scheme of polysilicon oxidation time.
Claims (5)
- A kind of 1. preparation method of polysilicon autoregistration raceway groove, it is characterised in that：Specifically include following steps：(1) grown buffer layer (2) on silicon carbide epitaxial layers (1)；(2) the growing polycrystalline silicon layer (3) on cushion (2)；(3) metallization medium layer (4) on polysilicon layer (3)；(4) by photoetching p-well or N trap figures, then etch media layer (4), polysilicon layer (3) and cushion (2), form p-well Or the injection window of N traps；(5) work is injected by multiple energetic ion as injection mask by dielectric layer (4), polysilicon layer (3) and cushion (2) Skill, form p-well or N well region (5)；(6) surface media (4) is removed；(7) high-temperature oxydation polysilicon layer (3) and cushion (2), oxide layer (6) is formed；(8) by multiple energetic ion injection technology, N+ or P+ source regions (7) are formed；It is raceway groove to inject mask stand out twice.
- 2. the preparation method of polysilicon autoregistration raceway groove according to claim 1, it is characterised in that：In the step (1), Cushion (2) is non-crystalline silicon, non-crystalline silicon, silica or silicon nitride after annealing, thickness 20-100nm.
- 3. the preparation method of polysilicon autoregistration raceway groove according to claim 1, it is characterised in that：In the step (3), Dielectric layer (4) is silica or silicon nitride, thickness 200-1000nm.
- 4. the preparation method of polysilicon autoregistration raceway groove according to claim 1, it is characterised in that：In the step (7), Individually using the polysilicon after oxidation as mask.
- 5. the preparation method of polysilicon autoregistration raceway groove according to claim 1, it is characterised in that：In the step (7), Oxidization time difference realizes the preparation of different in width raceway groove.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2017102518875 | 2017-04-17 | ||
| CN201710251887 | 2017-04-17 |
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| Publication Number | Publication Date |
|---|---|
| CN107527955A true CN107527955A (en) | 2017-12-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710554326.2A Pending CN107527955A (en) | 2017-04-17 | 2017-07-07 | The preparation method of polysilicon autoregistration raceway groove |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110648997A (en) * | 2019-09-23 | 2020-01-03 | 中国电子科技集团公司第五十五研究所 | SiC chip photoetching mark forming method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6979635B1 (en) * | 2004-01-20 | 2005-12-27 | Advanced Micro Devices, Inc. | Method of forming miniaturized polycrystalline silicon gate electrodes using selective oxidation |
| US20090057679A1 (en) * | 2007-09-03 | 2009-03-05 | Chunghwa Picture Tubes, Ltd. | Thin film transistor and manufacturing method thereof |
| CN103219237A (en) * | 2013-04-27 | 2013-07-24 | 中国东方电气集团有限公司 | Manufacturing method of self-aligned insulated gate bipolar transistor |
| CN105161539A (en) * | 2015-09-10 | 2015-12-16 | 中国科学院微电子研究所 | Silicon carbide MOSFET device and manufacturing method thereof |
-
2017
- 2017-07-07 CN CN201710554326.2A patent/CN107527955A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6979635B1 (en) * | 2004-01-20 | 2005-12-27 | Advanced Micro Devices, Inc. | Method of forming miniaturized polycrystalline silicon gate electrodes using selective oxidation |
| US20090057679A1 (en) * | 2007-09-03 | 2009-03-05 | Chunghwa Picture Tubes, Ltd. | Thin film transistor and manufacturing method thereof |
| CN103219237A (en) * | 2013-04-27 | 2013-07-24 | 中国东方电气集团有限公司 | Manufacturing method of self-aligned insulated gate bipolar transistor |
| CN105161539A (en) * | 2015-09-10 | 2015-12-16 | 中国科学院微电子研究所 | Silicon carbide MOSFET device and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110648997A (en) * | 2019-09-23 | 2020-01-03 | 中国电子科技集团公司第五十五研究所 | SiC chip photoetching mark forming method |
| CN110648997B (en) * | 2019-09-23 | 2021-09-28 | 中国电子科技集团公司第五十五研究所 | SiC chip photoetching mark forming method |
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