CN110634950A - Gallium oxide vertical structure semiconductor electronic device and manufacturing method thereof - Google Patents
Gallium oxide vertical structure semiconductor electronic device and manufacturing method thereof Download PDFInfo
- Publication number
- CN110634950A CN110634950A CN201810657127.9A CN201810657127A CN110634950A CN 110634950 A CN110634950 A CN 110634950A CN 201810657127 A CN201810657127 A CN 201810657127A CN 110634950 A CN110634950 A CN 110634950A
- Authority
- CN
- China
- Prior art keywords
- current
- type
- layer
- vertical structure
- electronic device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 31
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 238000012545 processing Methods 0.000 claims abstract description 6
- 230000000903 blocking effect Effects 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 15
- 208000037516 chromosome inversion disease Diseases 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 150000002500 ions Chemical class 0.000 abstract description 7
- 238000002347 injection Methods 0.000 abstract description 4
- 239000007924 injection Substances 0.000 abstract description 4
- 238000002360 preparation method Methods 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000004134 energy conservation Methods 0.000 description 2
- 241001354791 Baliga Species 0.000 description 1
- 241000984642 Cura Species 0.000 description 1
- 206010063385 Intellectualisation Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 230000003137 locomotive effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
Abstract
The invention discloses a gallium oxide vertical structure semiconductor electronic device and a preparation method thereof. The gallium oxide vertical structure semiconductor electronic device comprises a buffer layer, a current barrier layer and a channel layer which are sequentially arranged, current through holes formed by ion injection processing are further distributed in the current barrier layer, a source electrode and a grid electrode are arranged on the channel layer, the buffer layer is connected with the drain electrode, the drain electrode and the current barrier layer are oppositely arranged, the current through holes are located below the grid electrode, and the channel layer and the buffer layer are electrically connected through the current through holes. The gallium oxide vertical structure semiconductor electronic device provided by the invention has a simple structure, can well meet the requirements of a high-power switch, has a series of advantages of large saturation current, high breakdown voltage and the like, and greatly exerts the Ga2O3The material characteristics enable the gallium oxide vertical structure semiconductor electronic device to play a greater role in the field of power semiconductor electronic devices.
Description
Technical Field
The invention particularly relates to a gallium oxide vertical structure semiconductor electronic device and a manufacturing method thereof, belonging to the technical field of semiconductor devices.
Background
In modern society, power electronic technology is the core for realizing conversion and utilization of various energy sources and electric energy, and also the foundation and important pillar of the national economy and national safety field, and power electronic devices play a decisive role in the application and market of the power electronic technology field, are bridges between weak current control and strong current operation, are information technology and advanced manufacturing technology, and are foundation supports for realizing automation, intellectualization, energy conservation and mechanical and electrical integration in the traditional and modern industries. With the continuous development of high-voltage frequency conversion, alternating-current transmission locomotives/motor train units, urban rail transit, electric/hybrid electric vehicles, communication, new-generation data center servers, wireless communication, unmanned aerial vehicles and other wireless technologies, power electronic devices with higher performance are urgently needed to meet the development requirements.
Generally, any solid state energy conversion system is composed of circuits in which switching power supplies are widely implanted as a foundation for energy conversion. If the switch device is used for realizing high efficiency and energy conservation in the field of energy conversion, the loss of the whole system can be reduced, and meanwhile, the cost can be saved. Therefore, to implement a zero loss system, first a zero loss power switch is made. The key to realizing a zero loss power switch is to find a suitable semiconductor material so that the resistance of the switch in the on state is almost zero.
Current technologyThe most mature silicon (Si) -based power devices have reached the limit of silicon materials, and the requirements and development trends of electronic devices with high breakdown voltage, low on-resistance, high current, high temperature resistance and miniaturization, and novel ultra-wideband gap semiconductors (Ga) are more difficult to realize2O3) Compared with the traditional semiconductor material, the material and the device have great advantages, are particularly suitable for high-voltage, high-power and high-temperature application, and are one of the most potential materials for power electronic application.
Currently, Field Effect Transistors (FETs) mainly have two types of structures: the first is a horizontal structure device, and the second is a Vertical structure device (Vertical Field Effect Transistor, mainly including a Vertical MOSFET and a Vertical Current Aperture Transistor CAVET, Current Aperture Vertical electron Transistor). However, the horizontal type device has the following disadvantages with respect to the vertical type device: when the horizontal electronic device is in an off state, electrons can reach the drain end from the semi-insulating buffer layer to form a buffer layer leakage phenomenon, and the drain current can reach the breakdown judgment condition under a lower voltage due to the severe buffer layer leakage phenomenon. Meanwhile, the horizontal electronic device mainly depends on the active region between the grid and the drain to bear withstand voltage, and a large gap between the grid and the drain needs to be designed to obtain large breakdown voltage, so that the area required by the chip is increased, the requirement on miniaturization is not met, and the manufacturing cost is not reduced. High power conversion applications require high currents and voltages, and chips designed using horizontal structures are not economical and difficult to fabricate.
In addition, in the horizontal device, the high electric field region is located at the edge of the gate near the drain side, and electrons are injected into a trap on the surface by the high electric field, so that current collapse is caused, and the application of the lateral device in the high-voltage field is further limited by the serious reliability problem.
Disclosure of Invention
The invention mainly aims to provide a gallium oxide vertical structure semiconductor electronic device and a manufacturing method thereof, so as to overcome the defects of the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
the embodiment of the invention provides a gallium oxide vertical structure semiconductor electronic device which comprises a buffer layer, a current barrier layer and a channel layer which are sequentially arranged, wherein current through holes formed by ion injection processing are further distributed in the current barrier layer, a source electrode and a grid electrode are arranged on the channel layer, the buffer layer is connected with the drain electrode, the drain electrode and the current barrier layer are oppositely arranged, the current through holes are positioned below the grid electrode, and the channel layer and the buffer layer are electrically connected through the current through holes.
The embodiment of the invention also provides a manufacturing method of the gallium oxide vertical structure semiconductor electronic device, which comprises the following steps:
a current blocking layer is formed on the buffer layer,
processing partial area of the current blocking layer by adopting an ion implantation mode to form a current through hole, wherein the current through hole is positioned below the grid electrode,
forming a channel layer on the current blocking layer, and the channel layer and a buffer layer being capable of being electrically connected via the current via,
and manufacturing a grid electrode, a source electrode and a drain electrode, wherein the source electrode and the grid electrode are arranged on the channel layer, and the drain electrode is connected with the buffer layer and arranged opposite to the current blocking layer.
The embodiment of the invention also provides the gallium oxide vertical structure semiconductor electronic device manufactured by the manufacturing method of the gallium oxide vertical structure semiconductor electronic device.
Compared with the prior art, the gallium oxide vertical structure semiconductor electronic device provided by the invention has a simple structure, can well meet the requirements of a high-power switch, has a series of advantages of large saturation current, high breakdown voltage and the like, and greatly exerts the Ga2O3The material characteristics enable the gallium oxide vertical structure semiconductor electronic device to play a greater role in the field of power semiconductor electronic devices.
Drawings
Fig. 1 is a schematic structural diagram of a gallium oxide vertical structure semiconductor electronic device in an exemplary embodiment of the invention.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.
The embodiment of the invention provides a gallium oxide vertical structure semiconductor electronic device which comprises a buffer layer, a current barrier layer and a channel layer which are sequentially arranged, wherein current through holes formed by ion injection processing are further distributed in the current barrier layer, a source electrode and a grid electrode are arranged on the channel layer, the buffer layer is connected with the drain electrode, the drain electrode and the current barrier layer are oppositely arranged, the current through holes are positioned below the grid electrode, and the channel layer and the buffer layer are electrically connected through the current through holes.
Further, when the device is in an on state, the source electrode, the channel layer, the current through hole and the drain electrode are sequentially conducted, and when the device is in an off state, the gate can deplete the channel under the gate.
Furthermore, the current through hole is formed by performing inversion treatment on part of the current blocking layer.
Further, the buffer layer is formed on a first surface of the substrate, the drain electrode is arranged on a second surface of the substrate, and the first surface and the second surface are arranged oppositely.
Preferably, the substrate has a thickness of 1 μm to 1 mm.
Preferably, the material of the substrate comprises N-type or P-type Ga2O3。
Furthermore, the material of the channel layer comprises N + type or P + type Ga2O3。
Furthermore, the material of the buffer layer comprises N-type or P-type Ga2O3。
Preferably, the buffer layer has a thickness of 1nm to 100 μm.
Furthermore, the material of the current blocking layer comprises P-type or N-type Ga2O3。
Preferably, the material of the current through hole comprises N-type or P-type Ga2O3。
Furthermore, the gallium oxide vertical structure semiconductor electronic device comprises two source electrodes, and the grid electrode is distributed between the two source electrodes.
Further, a gate insulating layer is distributed between the gate and the channel layer.
The embodiment of the invention also provides a manufacturing method of the gallium oxide vertical structure semiconductor electronic device, which comprises the following steps:
a current blocking layer is formed on the buffer layer,
processing at least partial area of the current blocking layer to form a current through hole, wherein the current through hole is positioned below the grid electrode,
forming a channel layer on the current blocking layer, and the channel layer and a buffer layer being capable of being electrically connected via the current via,
and manufacturing a grid electrode, a source electrode and a drain electrode, wherein the source electrode and the grid electrode are arranged on the channel layer, and the drain electrode is connected with the buffer layer and arranged opposite to the current blocking layer.
Further, the manufacturing method comprises the following steps: and performing inversion treatment on partial area of the current blocking layer so that the current through hole is formed on partial current blocking layer.
Preferably, the current blocking layer is treated by ion implantation at room temperature to 500 ℃.
Furthermore, the material of the channel layer comprises N + type or P + type Ga2O3。
Furthermore, the material of the buffer layer comprises N-type or P-type Ga2O3。
Furthermore, the material of the current blocking layer comprises P-type or N-type Ga2O3。
Furthermore, the material of the current through hole comprises N-type or P-type Ga2O3。
Furthermore, the manufacturing method comprises the step of manufacturing two source electrodes, and the grid electrode is distributed between the two source electrodes.
Further, the manufacturing method comprises the following steps: and arranging a gate insulating layer on the channel layer, and then manufacturing a gate on the gate insulating layer.
Further, the buffer layer is formed on a first surface of the substrate, the drain electrode is arranged on a second surface of the substrate, and the first surface and the second surface are arranged oppositely.
Further, the manufacturing method further comprises: and forming ohmic contact between the source electrode and the channel layer, and forming ohmic contact between the drain electrode and the buffer layer or the substrate.
The embodiment of the invention also provides the gallium oxide vertical structure semiconductor electronic device manufactured by the manufacturing method of the gallium oxide vertical structure semiconductor electronic device.
For semiconductor power electronics, Baliga's figure of merit (which is a low loss index) is used as a figure of merit, FOM ═ BV2/Ron) Is an index for comprehensive evaluation of power devices and is recognized by many researchers in the industry, wherein breakdown field strength (BV) and on-resistance (R)on) Are two important parameters that affect device performance.
Ga provided by the embodiment of the invention2O3The forbidden band of the material is 4.7-5.3 eV, the breakdown field strength is 8-10 MV/cm, and therefore Ga2O3The critical field intensity of the semiconductor is more than 20-30 times of that of Si and more than 2 times of that of the third-generation semiconductor GaN and SiC, and Ga2O3The Bariga merit value is more than 2-4 times of that of GaN, SiC and other materials; higher in low frequency devices, Ga based on the above excellent performance2O3Compared with the traditional Si and the third generation semiconductor material, the material and the device have the great advantages on high-power and high-voltage devices, and have the potential of influencing the whole power conversion field.
At present Ga2O3Field Effect Transistors (FETs) have two main types of structures: one is a horizontal structure device, and the other is a Vertical structure device (Vertical Field Effect Transistor) which mainly comprises a Vertical MOSFET and a Vertical current aperture Transistor CAVET, CurA current Aperture Vertical Electron transistor). The majority of the current research objects are transverse structure Ga2O3The device is mainly a vertical structure device, and therefore, the embodiment of the invention provides a novel Ga device2O3Vertical structure devices to meet high pressure/high flow applications.
The technical solution, the implementation process and the principle thereof will be further explained with reference to the drawings.
Referring to fig. 1, in an embodiment of the present invention, a gallium oxide vertical structure semiconductor electronic device may include: sequentially arranged N-type or P-type Ga2O3Substrate (1 μm-1mm) and N-type or P-type Ga2O3Buffer layer (1nm-100 μm), the N-type or P-type Ga2O3P-type or N-type Ga is arranged above the buffer layer2O3Current blocking layer (1nm-100 μm) in P-type or N-type Ga2O3An N-type or P-type Ga is formed in the current blocking layer2O3Current through holes in the P-type or N-type Ga2O3Current blocking layer and N-type or P-type Ga2O3An N + type or P + type Ga is formed above the current through hole2O3A channel layer (1nm-100 μm), and Ga in N + type or P + type2O3Two source electrodes and a grid electrode are arranged on the channel layer, the grid electrode is positioned between the two source electrodes, and the drain electrode is arranged on the N-type or P-type Ga2O3The back side of the substrate (i.e., below); in the gate and N + type or P + type Ga2O3A gate insulating layer is arranged between the channel layers and can be made of high-K dielectric materials such as aluminum nitride and the like; wherein the current via is partially composed of P-type or N-type Ga2O3The current barrier layer is formed by N-type or P-type Ga after inversion treatment in an ion injection mode2O3Current through hole, N-type or P-type Ga2O3The current through hole is positioned below the grid electrode.
In particular, in the gallium oxide vertical structure semiconductor electronic device provided by the embodiment of the invention, the source electrode and the grid electrode are positioned at the top of the device, and the drain electrode is positioned at the bottom of the deviceBuffer layer (N-type or P-type Ga)2O3) And a channel layer (N + type or P + type Ga)2O3) A current blocking layer (P-type or N-type Ga) is present nearby2O3) So that electrons cannot pass through the buffer layer, and the electrons can only flow into the buffer layer from the horizontal channel layer through the current through hole. In the on state, electrons from the source sequentially pass through the horizontal channel (N + type or P + type Ga)2O3) A control region under the gate, a current blocking layer (P-type or N-type Ga)2O3) Pore diameter of between, N-type or P-type Ga2O3Buffer layer and N-type or P-type Ga2O3A substrate, eventually reaching the drain; in the off state, the gate electrode is connected with the channel layer (N + type or P + type Ga) below the gate electrode2O3) Completely exhausted, and the voltage resistance of the device is mainly reverse biased N-type or P-type Ga2O3Buffer layer/P-type or N-type Ga2O3The formed P-N junction is sustained. Thus, it is possible to control Ga of N type or P type2O3The thickness of the buffer layer improves the withstand voltage of the device. Since Ga is2O3The material has strong breakdown field, and under the same voltage withstanding condition, the thickness of the drift region can be greatly reduced, so that smaller on-resistance is obtained, and the device with the structure has the characteristics of high breakdown voltage, low on-resistance and large current.
The embodiment can be applied to N-type or P-type Ga by semiconductor thin film epitaxy technology2O3Growing N-type or P-type Ga with a certain thickness on a substrate2O3Thin film (i.e. buffer layer) and then epitaxial with a layer of P-type or N-type Ga2O3Thin film (i.e., current blocking layer), and then epitaxially growing a second layer of P-type or N-type Ga using a patterned mask2O3Ion implantation is carried out on partial area of the film to make the film form N-type or P-type Ga in an inversion mode2O3Then epitaxially growing P-type or N-type Ga on the second layer by epitaxial technique2O3Growing high concentration N + type or P + type Ga on film2O3A thin film (i.e., channel layer), followed by the deposition of an insulating dielectric and a metal electrode (gate) over the inversion region to control the on and off flow of current, on both sides over the device in the inversion region and on the back of the substrateOhmic contact electrodes are prepared on the surface to form a source electrode (source) and a drain electrode (drain) of the electronic device with the vertical structure.
Ion implantation of the current blocking layer: because the crystal lattice damage caused by ion bombardment in the ion implantation process can further affect the performance of the semiconductor film, the high-temperature ion implantation can be carried out in the key process of the ion implantation, namely, the device substrate is heated to the room temperature to 500 ℃ (namely, the ion implantation process is carried out under the condition of the room temperature to 500 ℃, the ion implantation and the high-temperature treatment can be carried out simultaneously or alternatively, or the high-temperature treatment is carried out after the ion implantation is finished, wherein the temperature ranges from the room temperature to 500 ℃); the introduction of the high-temperature process can repair the lattice damage caused by ion implantation, improve the activation rate of implanted ions to a certain extent and improve the performance of devices.
Since ohmic contacts of the source and drain affect device performance, ion implantation is performed on this region to improve device performance. Wherein the N-type implanted ions include: si, Sn, Ge, etc., P-type implanted ions including: mg, B, In, etc.
It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (12)
1. The utility model provides a gallium oxide vertical structure semiconductor electron device which characterized in that is including buffer layer, current barrier layer and the channel layer that sets gradually, still distribute in the current barrier layer and handle the current through-hole that forms through the mode of ion implantation, be provided with source electrode and grid on the channel layer, the buffer layer is connected with the drain electrode, the drain electrode sets up with current barrier layer back to back, the current through-hole is located the grid below, the channel layer passes through with the buffer layer the current through-hole electricity is connected.
2. The gallium oxide vertical structure semiconductor electronic device of claim 1, wherein: when the device is in an on state, the source electrode, the channel layer, the current through hole and the drain electrode are sequentially conducted, and when the device is in an off state, the grid electrode can deplete the channel under the grid electrode.
3. The gallium oxide vertical structure semiconductor electronic device according to claim 1 or 2, wherein: the current through hole is formed by performing inversion treatment on part of the current blocking layer.
4. The gallium oxide vertical structure semiconductor electronic device of claim 3, wherein: the buffer layer is formed on a first surface of the substrate, the drain electrode is arranged on a second surface of the substrate, and the first surface and the second surface are arranged oppositely; preferably, the thickness of the substrate is 1 μm to 1 mm; preferably, the material of the substrate comprises N-type or P-type Ga2O3(ii) a And/or the material of the channel layer comprises N + type or P + type Ga2O3(ii) a And/or the buffer layer is made of N-type or P-type Ga2O3(ii) a Preferably, the thickness of the buffer layer is 1nm-100 μm; and/or the material of the current barrier layer comprises P-type or N-type Ga2O3(ii) a Preferably, the material of the current through hole comprises N-type or P-type Ga2O3。
5. The gallium oxide vertical structure semiconductor electronic device according to claim 1, comprising two source electrodes, wherein the gate electrode is disposed between the two source electrodes.
6. The gallium oxide vertical structure semiconductor electronic device according to claim 1 or 5, wherein: and a gate insulating layer is also distributed between the gate and the channel layer.
7. A method for manufacturing a gallium oxide vertical structure semiconductor electronic device is characterized by comprising the following steps:
a current blocking layer is formed on the buffer layer,
processing partial area of the current blocking layer by adopting an ion implantation mode to form a current through hole, wherein the current through hole is positioned below the grid electrode,
forming a channel layer on the current blocking layer, and the channel layer and a buffer layer being capable of being electrically connected via the current via,
and manufacturing a grid electrode, a source electrode and a drain electrode, wherein the source electrode and the grid electrode are arranged on the channel layer, and the drain electrode is connected with the buffer layer and arranged opposite to the current blocking layer.
8. The method of manufacturing according to claim 7, comprising: performing inversion treatment on a partial region of the current blocking layer so that the current through hole is formed on the partial current blocking layer; preferably, the current blocking layer is treated by ion implantation at room temperature to 500 ℃.
9. The manufacturing method according to claim 7 or 8, characterized in that: the channel layer is made of N + type or P + type Ga2O3(ii) a And/or the buffer layer is made of N-type or P-type Ga2O3(ii) a And/or the material of the current barrier layer comprises P-type or N-type Ga2O3(ii) a Preferably, the material of the current through hole comprises N-type or P-type Ga2O3。。
10. The method of claim 7, further comprising forming two sources, wherein the gate is disposed between the two sources.
11. The method of manufacturing according to claim 7, comprising: arranging a gate insulating layer on the channel layer, and then manufacturing a gate on the gate insulating layer;
and/or the buffer layer is formed on a first surface of the substrate, the drain electrode is arranged on a second surface of the substrate, and the first surface and the second surface are arranged oppositely.
And/or the manufacturing method further comprises the following steps: and forming ohmic contact between the source electrode and the channel layer, and forming ohmic contact between the drain electrode and the buffer layer or the substrate.
12. A gallium oxide vertical structure semiconductor electronic device fabricated by the method of fabricating a gallium oxide vertical structure semiconductor electronic device of any one of claims 7-11.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810657127.9A CN110634950A (en) | 2018-06-22 | 2018-06-22 | Gallium oxide vertical structure semiconductor electronic device and manufacturing method thereof |
| PCT/CN2018/103268 WO2019242100A1 (en) | 2018-06-22 | 2018-08-30 | Gallium oxide semiconductor electronic device with vertical structure and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810657127.9A CN110634950A (en) | 2018-06-22 | 2018-06-22 | Gallium oxide vertical structure semiconductor electronic device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110634950A true CN110634950A (en) | 2019-12-31 |
Family
ID=68967396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810657127.9A Pending CN110634950A (en) | 2018-06-22 | 2018-06-22 | Gallium oxide vertical structure semiconductor electronic device and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110634950A (en) |
| WO (1) | WO2019242100A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785776A (en) * | 2020-07-16 | 2020-10-16 | 西安电子科技大学 | Vertical structure Ga2O3Preparation method of metal oxide semiconductor field effect transistor |
| CN113066857A (en) * | 2021-03-24 | 2021-07-02 | 中国科学技术大学 | High-quality factor gallium oxide transistor and preparation method thereof |
| CN113224142A (en) * | 2021-04-16 | 2021-08-06 | 西安电子科技大学 | Gallium oxide heterojunction structures and heterojunction devices based on bound-charge enhanced 2DEG |
| CN113421914A (en) * | 2021-06-22 | 2021-09-21 | 西安电子科技大学 | P-type metal oxide current blocking layer Ga2O3Vertical metal oxide semiconductor field effect transistor |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103608923A (en) * | 2011-06-20 | 2014-02-26 | 加利福尼亚大学董事会 | Current aperture vertical electron transistors |
| CN104701359A (en) * | 2015-03-10 | 2015-06-10 | 苏州能屋电子科技有限公司 | Vertical-structure AlGaN/GaN HEMT device and manufacturing method thereof |
| CN205692835U (en) * | 2016-06-08 | 2016-11-16 | 苏州能屋电子科技有限公司 | Enhancement mode self-supporting vertical stratification III group-III nitride HEMT device and AlGaN/GaN HEMT device |
| CN106935661A (en) * | 2017-01-23 | 2017-07-07 | 西安电子科技大学 | Vertical-type Schottky diode and preparation method thereof |
| CN107134491A (en) * | 2017-03-29 | 2017-09-05 | 西安电子科技大学 | Vertical stratification power electronic devices based on arcuate source field plate |
| US20180151715A1 (en) * | 2016-11-28 | 2018-05-31 | Srabanti Chowdhury | Diamond based current aperture vertical transistor and methods of making and using the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015176002A1 (en) * | 2014-05-15 | 2015-11-19 | The Regents Of The University Of California | Doping in iii-nitride devices |
| JP2016143840A (en) * | 2015-02-04 | 2016-08-08 | 国立研究開発法人情報通信研究機構 | Semiconductor device |
| CN106941117B (en) * | 2017-03-09 | 2019-07-16 | 西安电子科技大学 | Gallium nitride radical heterojunction current apertures device based on suspension superjunction and preparation method thereof |
-
2018
- 2018-06-22 CN CN201810657127.9A patent/CN110634950A/en active Pending
- 2018-08-30 WO PCT/CN2018/103268 patent/WO2019242100A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103608923A (en) * | 2011-06-20 | 2014-02-26 | 加利福尼亚大学董事会 | Current aperture vertical electron transistors |
| CN104701359A (en) * | 2015-03-10 | 2015-06-10 | 苏州能屋电子科技有限公司 | Vertical-structure AlGaN/GaN HEMT device and manufacturing method thereof |
| CN205692835U (en) * | 2016-06-08 | 2016-11-16 | 苏州能屋电子科技有限公司 | Enhancement mode self-supporting vertical stratification III group-III nitride HEMT device and AlGaN/GaN HEMT device |
| US20180151715A1 (en) * | 2016-11-28 | 2018-05-31 | Srabanti Chowdhury | Diamond based current aperture vertical transistor and methods of making and using the same |
| CN106935661A (en) * | 2017-01-23 | 2017-07-07 | 西安电子科技大学 | Vertical-type Schottky diode and preparation method thereof |
| CN107134491A (en) * | 2017-03-29 | 2017-09-05 | 西安电子科技大学 | Vertical stratification power electronic devices based on arcuate source field plate |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785776A (en) * | 2020-07-16 | 2020-10-16 | 西安电子科技大学 | Vertical structure Ga2O3Preparation method of metal oxide semiconductor field effect transistor |
| CN111785776B (en) * | 2020-07-16 | 2022-06-03 | 西安电子科技大学 | Vertical structure Ga2O3Preparation method of metal oxide semiconductor field effect transistor |
| CN113066857A (en) * | 2021-03-24 | 2021-07-02 | 中国科学技术大学 | High-quality factor gallium oxide transistor and preparation method thereof |
| CN113224142A (en) * | 2021-04-16 | 2021-08-06 | 西安电子科技大学 | Gallium oxide heterojunction structures and heterojunction devices based on bound-charge enhanced 2DEG |
| CN113421914A (en) * | 2021-06-22 | 2021-09-21 | 西安电子科技大学 | P-type metal oxide current blocking layer Ga2O3Vertical metal oxide semiconductor field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2019242100A1 (en) | 2019-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI520337B (en) | Step trench metal-oxide-semiconductor field-effect transistor and method of fabrication the same | |
| US11322606B2 (en) | Heterojunction semiconductor device having high blocking capability | |
| CN103337516B (en) | Enhancement mode switching device and manufacture method thereof | |
| CN103258847B (en) | Reverse block (RB)-insulated gate bipolar transistor (IGBT) device provided with double-faced field stop with buried layers | |
| CN106783851B (en) | SiCJFET device integrated with Schottky diode and manufacturing method thereof | |
| CN102364688B (en) | Vertical double-diffusion metal oxide semiconductor field effect transistor (MOSFET) | |
| CN110634950A (en) | Gallium oxide vertical structure semiconductor electronic device and manufacturing method thereof | |
| CN102184956B (en) | Longitudinal conduction GaN enhancement type MISFET (Metal Integrated Semiconductor Field Effect Transistor) device and manufacturing method thereof | |
| CN106158948B (en) | III-nitride enhanced HEMT device and manufacturing method thereof | |
| CN109148586B (en) | Gallium oxide field effect transistor | |
| WO2023142393A1 (en) | High-speed flyback diode-integrated silicon carbide split gate mosfet and preparation method | |
| CN104701380B (en) | Dual-direction MOS-type device and manufacturing method thereof | |
| CN107808899A (en) | Lateral power with hybrid conductive pattern and preparation method thereof | |
| CN105932055A (en) | Plane gate IGBT and manufacturing method therefor | |
| CN106298911A (en) | A kind of double junction gate gallium nitride heterojunction field effect transistor | |
| CN104538450A (en) | SiC VDMOSFET structure with low specific on-resistance and manufacturing method thereof | |
| CN105993076A (en) | Bi-directional MOS device and manufacturing method thereof | |
| CN102779839A (en) | Insulated gate bipolar transistor (IGBT) with deep energy level impurity implantation | |
| CN115579397A (en) | Two-stage trench gate silicon carbide MOSFET and preparation method thereof | |
| CN117080269A (en) | Silicon carbide MOSFET device and preparation method thereof | |
| CN117497601A (en) | Structure, manufacturing method and electronic equipment of planar silicon carbide transistor | |
| CN210897283U (en) | Semiconductor device with a plurality of transistors | |
| CN102290434B (en) | Metal-semiconductor field effect transistor with under-grid buffer layer structure and manufacturing method | |
| CN116504805A (en) | High electron mobility transistor with vertical AlGaN/GaN structure and preparation method thereof | |
| CN103117309A (en) | Horizontal power device structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191231 |