CN110610860A - 半导体器件及用于制造半导体器件的方法 - Google Patents

半导体器件及用于制造半导体器件的方法 Download PDF

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Publication number
CN110610860A
CN110610860A CN201811405916.XA CN201811405916A CN110610860A CN 110610860 A CN110610860 A CN 110610860A CN 201811405916 A CN201811405916 A CN 201811405916A CN 110610860 A CN110610860 A CN 110610860A
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type
region
forming
gate electrode
substrate
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李泰勋
赵准煕
郑真诚
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Key Foundry Co Ltd
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Megner Semiconductor Co Ltd
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Abstract

本公开内容涉及半导体器件及用于制造半导体器件的方法。用于制造半导体器件的方法包括：在基板上形成栅极绝缘膜和多晶硅层；通过蚀刻多晶硅层来形成多晶硅图案；通过在多晶硅图案上形成掩模图案来在多晶硅图案上形成暴露多晶硅图案的一部分的开口；通过蚀刻经由开口暴露的多晶硅图案的所述一部分来形成栅电极；通过使用栅电极作为掩模将P型掺杂剂离子注入至基板上来形成P型体区；通过使用栅电极作为掩模将N型掺杂剂离子注入至基板上来在P型体区上形成N型LDD区；在栅电极的侧表面上形成间隔物；以及在间隔物的侧表面上形成N型源极区。

Description

半导体器件及用于制造半导体器件的方法
相关申请的交叉引用
本申请要求在35 USC 119(a)下的于2018年6月14日在韩国知识产权局提交的韩国专利申请第10-2018-0068367号的权益，其全部公开内容为了所有目的通过引用并入本文。
技术领域
以下的描述涉及半导体器件及用于制造半导体器件的方法。以下的描述还涉及n-LDMOS器件及用于制造n-LDMOS器件的方法。
背景技术
具有高开关频率和低功耗的金属氧化物半导体场效应晶体管(MOSFET)器件已经广泛用于功率转换和功率控制电路。在这样的示例中，存在被称为双扩散MOS(DMOS)晶体管的各种类型的功率MOSFET器件。例如，存在作为垂直型DMOS的垂直双扩散金属氧化物半导体(VDMOS)器件和作为横向型DMOS的横向双扩散金属氧化物半导体(LDMOS)器件。
这样的LDMOS广泛用作用于控制应用、逻辑应用和功率应用的开关。需要这样的LDMOS不但具有高的击穿电压(BV)以承受施加至其的高电压，而且具有低的导通电阻(on-resistance)以使传导损耗最小化。
在LDMOS中，形成体区以形成沟道区。此外，在LDMOS的体区上形成栅电极。在该示例中，使用体掩模图案形成LDMOS的体区，并且使用栅电极掩模图案形成栅电极。通过体掩模图案和栅电极掩模图案来调整LDMOS的沟道长度。因为通过两个掩模图案来调整沟道长度，所以发生沟道宽度分散。随着沟道宽度分散降低，阈值电压分散也降低。然而，因为使用两个掩模，所以光刻工艺的分散增加。相应地，沟道和阈值电压的分散彼此不同。如上所述，因为通过两个掩模图案而不是一个掩模图案来确定沟道长度，所以出现如下问题：沟道和阈值电压的各自的分散均变得较大。
发明内容
本发明内容被提供来以简化的形式介绍一系列概念，上述概念下面在具体实施方式中进一步描述。本发明内容不旨在识别所要求保护的主题的关键特征或必要特征，也不旨在用作帮助确定所要求保护的主题的范围。
在一个一般的方面中，一种用于制造半导体器件的方法包括：在基板上形成栅极绝缘膜和多晶硅层；通过蚀刻多晶硅层来形成多晶硅图案；通过在多晶硅图案上形成掩模图案来在多晶硅图案上形成开口，该开口暴露多晶硅图案的一部分；通过蚀刻经由开口暴露的多晶硅图案的所述一部分来形成栅电极；通过使用栅电极作为掩模将P型掺杂剂离子注入至基板上来形成P型体区；通过使用栅电极作为掩模将N型掺杂剂离子注入至基板上来在P型体区上形成N型LDD区；在栅电极的侧表面上形成间隔物；以及在间隔物的侧表面上形成N型源极区。
P型体区可以包括多个体离子注入区。
可以通过使用栅电极作为掩模的倾斜离子注入来形成P型体区。
P型体区可以被形成为与栅电极交叠。
P型体区可以随着其变得更接近于基板的顶表面而具有更长的宽度。
形成栅电极可以包括形成彼此间隔开的第一栅电极和第二栅电极。
制备基板可以包括：形成N型埋层、P型埋层和N型漂移区；形成连接至P型埋层的P型阱区；以及形成连接至N型埋层的N型阱区。
N型埋层可以具有比P型埋层的长度更大的长度。
栅电极可以由多晶硅、钨(W)、钨氮化物(WN)、钛(Ti)、钼(Mo)、钴(Co)、镍(Ni)、铜(Cu)或铝(Al)形成。
栅极绝缘膜可以由硅氧化物膜(SiO2)或硅氮化物膜(SiN)、硅氮氧化物膜(SiON)和高k材料膜中的任意一种或者任意两种或更多种的任意组合形成。
高k材料膜可以包括铝氧化物(Al2O3)、钽氧化物(Ta2O5)和铪氧化物(HfO2)中的任意一种或者任意两种或更多种的任意组合。
在另一个一般的方面中，一种用于制造半导体器件的方法包括：在基板上形成栅极绝缘膜和多晶硅层；在多晶硅层上形成掩模图案；使用P型掺杂剂执行至基板上的离子注入工艺，该离子注入工艺注入穿过多晶硅层的掺杂剂；通过使用掩模图案蚀刻多晶硅层来形成栅电极；通过使用栅电极作为掩模执行至基板上的二次离子注入来在基板上形成与栅电极交叠的P型体区；使用栅电极作为掩模来在P型体区上形成N型LDD区；在栅电极上形成间隔物；以及在P型体区上形成N型源极区。
方法还可以包括:形成与栅电极间隔开的N型漏极区。
方法还可以包括:在基板上形成栅极绝缘膜和多晶硅层之前，形成接触P型体区的P型埋层。
在另一个一般方面中，半导体器件包括：在基板上形成的第一传导类型埋层；在第一传导类型埋层上形成并且具有比第一传导类型埋层的宽度更小的宽度的第二传导类型埋层；在第二传导类型埋层上形成的第一传导类型的第一漂移区和第二漂移区；分别在第一漂移区和第二漂移区上形成的第一栅电极和第二栅电极；布置在第一漂移区与第二漂移区之间并且连接至第二传导类型埋层的第二传导类型体区；以及布置在第一漂移区与第二漂移区之间并且形成在第二传导类型体区上的第一传导类型源极区。
半导体器件还可以包括：分别与第一栅电极和第二栅电极间隔开形成的第一传导类型的第一漏极区和第二漏极区。
体区可以包括具有不同深度的多个体离子注入区。
根据以下详细的描述、附图和权利要求，其他的特征和方面将变得明显。
附图说明
图1是示出根据示例的半导体器件的图。
图2至图10是示出根据示例的用于形成半导体器件的方法的图。
图11A至图11D是示出根据另一示例的用于形成半导体器件的方法的图。
图12A至图12D是示出根据另一示例的用于形成半导体器件的方法的图。
遍及附图和详细描述，相同的附图标记指代相同的元件。附图可以不按比例绘制，并且为了清楚、说明和方便，可以夸大附图中的元件的相对尺寸、比例和描绘。
具体实施方式
提供了以下详细描述以帮助读者获得对本文中描述的方法、装置和/或系统的全面理解。然而，在理解本申请的公开内容之后，本文中描述的方法、装置和/或系统的各种变化、修改和等同物将变得明显。例如，除了必须以特定顺序发生的操作之外，本文中描述的操作的序列仅是示例，并且不限于本文中阐述的那些，而是可以如在理解本申请的公开内容之后将变得明显的那样被改变。此外，为了更加的清楚和简洁，可以省略对本领域已知的特征的描述。
本文中描述的特征可以以不同的形式实施，并且不被解释为限制于本文中描述的示例。而是，已经提供了本文中描述的示例仅为了说明在理解本申请的公开内容之后将变得明显的实现本文中描述的方法、装置和/或系统的许多可能方式中的一些。
在下文中，将参照附图详细地描述本公开内容的优选实施方式，使得本领域普通技术人员中之一可以容易地实施本公开内容。本公开内容可以以各种不同的类型来实现，并且不限于下文中描述的实施方式。
遍及说明书，当元件例如层、区或基板被描述为“在”另一元件“上”、“连接至”另一元件或“耦接至”另一元件时，该元件可以直接“在”另一元件“上”、“连接至”另一元件或“耦接至”另一元件，或者可以存在介入其间的一个或更多个其他元件。相比之下，当元件被描述为“直接在”另一元件“上”、“直接连接至”另一元件或“直接耦接至”另一元件时，可以不存在介入其间的其他元件。
如本文中使用的，术语“和/或”包括相关联的所列项中的任意一个以及任意两个或更多个的任意组合。
尽管在本文中可以使用术语例如“第一”、“第二”和“第三”来描述各种构件、部件、区、层或部分，这些构件、部件、区、层或部分不受这些术语限制。而是，这些术语仅用于将一个构件、部件、区、层或部分与另一构件、部件、区、层或部分相区别。因此，在不偏离示例的教导的情况下，本文中描述的示例中提及的第一构件、部件、区、层或部分还可以被称为第二构件、部件、区、层或部分。
为了便于描述，在本文中可以使用空间相对术语例如“上方”、“上面”“下方”和“下面”来描述如附图中所示的一个元件与另一元件的关系。除了附图中描绘的定向之外，这样的空间相对术语旨在包括使用或操作中器件的不同定向。例如，如果附图中的器件被翻转，则相对于另一元件被描述为“上方”或“上面”的元件然后将相对于另一元件处于“下方”或“下面”。因此，术语“上方”根据器件的空间定向包括上方和下方定向两者。器件还可以以其他方式被定向(例如，旋转90度或者处于其他定向)，并且相应地解释本文中使用的空间相对术语。
本文中使用的术语仅用于描述各种示例，并且不用于限制本公开内容。除非上下文另外明确指示之外，冠词“一(a)”、“一个(an)”和“该(the)”也旨在包括复数形式。术语“包含”、“包括”和“具有”指定所述特征、数目、操作、构件、元件和/或其组合的存在，但不排除一个或更多个其他特征、数目、操作、构件、元件和/或其组合的存在或者添加。
由于制造技术和/或公差，可能出现附图中示出的形状的变化。因此，本文中描述的示例不限于附图中示出的特定形状，而是包括在制造期间出现的形状的改变。
如在理解本申请的公开内容之后将变得明显的那样，本文中描述的示例的特征可以以各种方式组合。此外，尽管本文中描述的示例具有各种配置，但是如在理解本申请的公开内容之后将变得明显的那样，其他配置是可能的。
如本文中使用的表达例如“第一传导类型”和“第二传导类型”可以指代相反的传导类型例如N和P传导类型，并且在本文中使用这样的表达描述的示例还包括互补示例。例如，第一传导类型是N并且第二传导类型是P的示例包括第一传导类型是P并且第二传导类型是N的示例。
在本公开内容的整个描述中，为了其容易理解，将省略与描述无关的部分，并且跨各个附图，相同的附图标记用于相同的元件。
通过参考参照附图要详细描述的实施方式，本公开内容的各个方面和特征以及用于实现各个方面和特征的方法将变得明显。然而，本公开内容不限于下文中公开的实施方式，而是可以以各种形式实现。说明书中限定的内容(例如详细的结构和元件)只是为了帮助本领域普通技术人员全面理解本公开内容而提供的具体的细节，并且本公开内容仅被限定在所附权利要求的范围内。在对本公开内容的整个描述中，跨各个附图，相同的附图标记用于相同的元件。
此外，将参照作为本公开内容的理想示例性视图的截面图和/或平面图来描述说明书中描述的本公开内容的示例性实施方式。在附图中，为了有效地说明技术内容，夸大膜和区的厚度。因此，由于制造技术和/或允许的误差，可以修改示例性视图的形状。因此，本公开内容的示例性实施方式不限于如所示的特定的形状，而是可以包括根据制造工艺产生的形状改变。例如，以直角示出的刻蚀区可以是圆形的或者可以具有特定的曲率。因此，在附图中示例性示出的区具有示意性属性，并且在附图中示例性示出的区的形状是为了例示器件的区的特定形状，而不限于本公开内容的范围。
在本文中，应注意的是，关于示例或实施方式的术语“可以”的使用，(例如关于示例或实施方式可以包括或实现什么)意味着存在包括或实现这样的特征的至少一个示例或实施方式，然而所有的示例和实施方式不限于此。
根据本示例的各个方面，可以降低由于光刻工艺的套刻(overlay)分散引起的特性分散，并且可以使用于形成LDMOS沟道的设计最小化以降低芯片尺寸。
本示例的一方面是为了提供用于利用一个掩模图案而不是两个掩模图案来形成n-LDMOS器件的沟道的方法。
本示例的另一方面是为了提供半导体器件和用于制造半导体器件的方法，其可以通过以特定角度倾斜的入射角注入杂质来在栅电极的下部上形成沟道区。
本示例的另一方面是为了提供半导体器件和用于制造半导体器件的方法，其可以使用栅电极作掩模来形成体区以解决如下问题：由于在光刻工艺期间出现的分散引起的阈值电压和击穿电压的分散。
图1是示出根据示例的半导体器件的图。
参考图1的示例，半导体器件可以包括P型基板110、N型埋层(NBL)120、P型外延层(P外延层)130、P型埋层(PBL)150、第一N漂移区170a和第二N漂移区170b、沟槽隔离区(STI)210、P型阱区(PW区)220、N型阱区(NW区)240、P型体区(P体区)250、N-LDD区290、栅极绝缘膜300a和300b、栅电极320a和320b、N+源极区410、N+漏极区430和P+接触区440。在这样的示例中，N型可以被称为第一传导类型，并且P型可以被称为第二传导类型。例如，N型埋层可以被称为第一传导类型埋层，并且P型埋层可以被称为第二传导类型埋层。以相似的方式指代剩余的区。
基板140包括P型基板110和P型外延层130。可以使用N型外延层代替P型外延层130。还可以在基板140中依次布置NBL 120和PBL 150。例如，NBL 120可以是掺杂有高浓度N型杂质的层，并且PBL 150可以是掺杂有高浓度P型杂质的层。这样的NBL 120可以用于高电压器件中的完全隔离的MOS器件。因为NBL 120和NW 240彼此电连接并且完全围绕N-LDMOS器件100，所以NBL 120和NW 240用于将N-LDMOS器件100与其他器件电隔离。因此，NBL 120和NW 240用作一种类型的保护环。在示例中，仅示出两个对称的n-LDMOS器件存在于公共源极区410的周围。然而，在其他示例中，两个或更多个n-LDMOS器件可以以阵列的形式成行地布置。因为NBL 120布置在基板110中，所以可以相应地降低高电压器件的噪声。此外，也可以降低n-LDMOS器件100的漏电流。PBL150形成为具有比NBL 120的长度小的长度。PBL 150的长度可以指代从PBL 150沿相对于朝向NBL 120的方向垂直的方向延伸的空间距离。
因为掺杂有P型杂质的PBL150布置在第一N漂移区170a和第二N漂移区170b下方，所以有助于增加N漂移区170a和170b的浓度，这提供了期望的特性。例如，如果N漂移区170a和170b的浓度增加，则可以在N-LDMOS器件100的导通状态期间降低N漂移区170a和170b的电阻。此外，可以在N-LDMOS器件100的截止状态中通过PBL 150来延伸耗尽区，并且因此可以获得期望的击穿电压。
N漂移区170a和170b以及P体区250可以布置在PBL 150上。例如，N漂移区170a和170b可以是掺杂有N型杂质的区域，并且P体区250可以是掺杂有P型杂质的区域。然而，如果N漂移区170a和170b的掺杂浓度低，则N-LDMOS器件100的击穿电压增加。因此，P体区250可以是以低浓度掺杂有P型杂质的沟道区。例如，P体区250可以是在其上在源极与漏极之间形成沟道的区域。P体区250与PBL 150物理接触以电连接至PBL 150。此外，PBL150与PW区220物理接触以电连接至PW区220。在这样的示例中，如果PW区220不存在，则在NW区240与N漂移区170a和170b之间可能出现漏电流，这可能导致操作问题。此外，可以使用PW区220将偏置电流施加至在N漂移区170a和170b下方的PBL150。
N漂移区170a和170b以及PBL150可以使用相同的掩模被离子注入，并且还可以在横向上具有相似的长度。然而，在另一示例中，PBL 150可以替选地形成为长于N漂移区170a和170b的横向长度。
可以在基板140上设置场氧化膜或器件隔离膜(沟槽隔离区210)。可以以沟槽的形式设置场氧化膜或器件隔离膜以用于相邻器件之间的绝缘。例如，器件隔离膜可以是用于将相邻的器件彼此隔离的氧化膜。
栅电极320a和320b可以布置在N漂移区170a和170b以及P体区250上。在这样的示例中，栅电极320a和320b可以由传导材料或金属层形成。可以使用多晶硅(poly-Si)作为传导材料。可以使用钨(W)、钨氮化物(WN)、钛(Ti)、钼(Mo)、钴(Co)、镍(Ni)、铜(Cu)或铝(Al)作为金属层。然而，这些仅是示例材料，并且在其他示例中，可以使用具有相似特性的其他相似材料作为传导材料或金属层。栅极绝缘膜300a和300b可以布置在栅电极320a和320b、N漂移区170a和170b以及P体区250之间。在示例中，栅极绝缘膜300a和300b可以由硅氧化物膜(SiO2)或硅氮化物膜(SiN)、硅氮氧化物膜(SiON)或高k材料制成，其中高k材料指代具有高介电常数的材料。高k材料例如铝氧化物(Al2O3)、钽氧化物(Ta2O5)和铪氧化物(HfO2)可以单独地或组合地形成，或者替选地通过堆叠第一高k材料和第二高k材料来形成。
N+漏极区430可以设置在N漂移区170a和170b上。例如，N+漏极区430可以是掺杂有N型杂质的区域。例如，N+漏极区430形成为以预定间隔与栅电极间隔开以增加N-LDMOS器件100的耐受电压。耐受电压可以随着N+漏极区进一步远离栅电极而相应地增加。在这样的示例中，在布置在N+漏极区430与栅电极320a和320b之间的N漂移区170a和170b上不存在单独的器件隔离膜。此外，在N+漏极区430与栅电极320a和320b之间的基板140具有共面结构。
N-LDD区290和N+源极区410可以设置在P体区250上。例如，N-LDD区290和N+源极区410可以是掺杂有N型杂质的区域。在布置在N-LDD区290与栅电极320a和320b之间的P体区250中形成沟道区。另外，在P体区250上，可以设置与N+源极区410相邻地布置的第二传导类型拾取区。例如，第二传导类型拾取区可以是掺杂有P型杂质的区域。
图2至图10是示出根据示例的用于形成半导体器件的方法的图。
参考图2的示例，在P型基板110上形成NBL 120。通过离子注入N型掺杂剂并且随后执行退火来形成NBL 120。此外，在生长P外延层130之后，在P外延层130的表面上形成沟槽隔离区210。例如，可以使用浅沟槽隔离(STI)、中沟槽隔离(MTI)、深沟槽隔离(DTI)和硅局部氧化(LOCOS)结构来形成沟槽隔离区210。此外，可以形成STI结构和DTI结构彼此组合的STI+DTI结构。此外，可以形成LOCOS结构和DTI结构彼此组合的LOCOS+DTI结构。此外，可以形成MTI结构和DTI结构彼此组合的MTI+DTI结构。因此，STI、MTI、DTI和LOCOS结构的各种组合用于沟槽隔离区210以实现各种效果。
参考图3的示例，使用N漂移掩模图案600来依次形成PBL 150和N漂移区170。通过使用N漂移掩模图案600来形成用于使基板140敞开的第一开口610。利用第一开口610空间，执行用于形成PBL和N漂移区的离子注入195。例如，可以通过注入高浓度P型杂质来形成PBL150。此外，需要高能量离子注入以形成PBL150。例如，P型杂质可以包括硼(B)离子，然而这是P型杂质的仅一个示例，并且其他示例可以使用其他适当的P型杂质。N漂移区170可以是掺杂有N型杂质的漂移区。使用相同的掩模来对N漂移区170和PBL150进行离子注入，并且因此N漂移区170和PBL 150具有在基板140的横向上延伸的相似长度。然而，因为通过比N漂移区170的离子注入更深的离子注入来形成PBL 150，所以PBL 150可以替选地形成为具有比N漂移区170的横向长度更长的横向长度。在形成了PBL 150和N漂移区170之后，N漂移掩模图案600随后被移除。
参考图4的示例，在基板140上形成NW区240和PW区220。PBL150与PW区220物理接触，并且因此可以电连接至PW区220。根据图4的示例，如果PW区220不存在，则可能在NW区240与N漂移区170之间出现漏电流。此外，可以使用PW区220将偏置施加至在N漂移区170下方的PBL 150。因此，NW区240和NBL 120彼此接触并且彼此电连接，以由此形成保护环的形状。NW区240和NBL 120可以相应地将N-LDMOS器件100与其他器件分离。通过使用连续形成技术，可以在N漂移区170上形成栅极绝缘膜300和多晶硅层310。栅极绝缘膜300可以由硅氧化物膜(SiO2)、硅氮化物膜(SiN)或硅氮氧化物膜(SiON)或者高k材料例如铪氧化物层、钽氧化物层或铝氧化物层制成。然而，这些仅是示例材料，并且在其他示例中，使用其他适当的材料来形成栅极绝缘膜300。
参考图5的示例，可以在多晶硅层310上形成栅极掩模图案700。通过使用栅极掩模图案700蚀刻多晶硅层310来形成多晶硅图案310-1。随着多晶硅图案310-1形成，可以暴露栅极绝缘膜300，并且因此可以相应地蚀刻栅极绝缘膜300的一部分。在间隔物形成工艺中，可以完全移除暴露至基板140上的栅极绝缘膜300。
参考图6的示例，在栅极绝缘膜300和多晶硅图案310-1上形成P体掩模图案800以暴露多晶硅图案310-1的一部分。通过P体掩模图案800形成第二开口810。通过第二开口810，多晶硅图案310-1被暴露。在此处，在第二开口810中执行离子注入225。例如，P型杂质可以通过穿过暴露的多晶硅图案310-1被离子注入至基板140上。如果使用高离子注入能量来注入P型杂质，则P型杂质在穿过多晶硅图案310-1之后到达基板。因此，可以在多晶硅图案310-1下方的N漂移区170上形成第一体离子注入区260。使用连续方法，可以通过使用中等离子注入能量的P型杂质的二次离子注入来在N漂移区170上形成第二体离子注入区270。第一体离子注入区260和第二体离子注入区270以堆叠结构的形式形成在N漂移区170上。如上所述，可以使用不同的离子注入能量来形成多个P型体离子注入区。例如，可以通过两次离子注入工艺将P型杂质注入至N漂移区170中。在这样的示例中，随着第一体离子注入区260和第二体离子注入区270形成，N漂移区170可以相应地被分为第一N漂移区170a和第二N漂移区170b。
参考图7的示例，通过在存在P体掩模图案800的状态下蚀刻暴露的多晶硅图案310-1的中央区域来形成第一栅电极320a和第二栅电极320b。被蚀刻的多晶硅图案310-1可以是与第一体离子注入区260和第二体离子注入区270垂直交叠的部分。随着多晶硅图案310-1被蚀刻，栅极绝缘膜300也被暴露。此外，可以根据蚀刻速率来蚀刻栅极绝缘膜300的一部分或全部。如果栅极绝缘膜300的全部被蚀刻，则可以相应地暴露第一N漂移区170a和第二N漂移区170b的部分。在这样的示例中，第一栅电极320a和第二栅电极320b变成n-LDMOS器件100的栅电极。
参考图8的示例，利用开口810将P型杂质第三次离子注入235至第一栅电极320a与第二栅电极320b之间的基板140中。亦即，通过执行至第一N漂移区170a和第二N漂移区170b上的第三离子注入来形成第三体离子注入区280。使用第一栅电极320a和第二栅电极320b作为掩模来形成第三体离子注入区280。P体掩模图案800用于防止第三体离子注入区280在其他位置处形成。
在这样的示例中，可以以与相对于栅电极的侧壁的特定角度θ对应的倾斜角度来将P型杂质注入至第一N漂移区170a和第二N漂移区170b中。注入P型杂质的倾斜角度可以是如基于栅电极的侧壁测量的锐角。由此，可以将P型杂质注入至第一栅电极320a和第二栅电极320b的下部中。在P型杂质的离子注入发生之后，可以执行高温退火工艺以用于P型杂质的后续的扩散或激活。
可以通过控制注入P型杂质的倾斜角度和P型杂质的浓度来控制朝向栅电极320a和320b的下部延伸的第三体离子注入区的长度。亦即，可以根据注入P型杂质的倾斜角度和P型杂质的浓度来控制延伸至栅电极320a和320b的下部的第三体离子注入区的长度。因此，可以容易地执行形成具有适于半导体器件的期望尺寸的长度的沟道的工艺。如上所述，使用栅电极320a和320b作为掩模以自对准方式来形成P体区。因此，在P体区的形成期间，不会出现套刻问题。在这样的示例中，套刻问题指代在用于形成栅电极320a和320b的栅极掩模图案700与用于形成P体区250的P体掩模图案800之间出现的差异。如图8的示例中所示，因为使用栅电极320a和320b作为掩模来形成P体区250，所以套刻问题消失并且可以避免套刻问题。
可以通过第一体离子注入区260和第二体离子注入区270以及第三体离子注入区280的组合来形成P体区250。在这样的示例中，第三体离子注入区280具有比第一体离子注入区260和第二体离子注入区270的横向长度更长的横向长度。出现上述更长的横向长度的原因是第一体离子注入区260和第二体离子注入区270以垂直方向被离子注入，而第三体离子注入区280倾斜地被离子注入。例如，可以使用倾斜离子注入将P型杂质直接注入至栅电极320a和320b的下部中。然而，还由于倾斜离子注入的使用，第三体离子注入区280的深度可能与第一体离子注入区260和第二体离子注入区270的深度相比更薄和更浅。此外，在这样的示例中，第一体离子注入区260和第二体离子注入区270以及第三体离子注入区280存在于第一栅电极320a与第二栅电极320b之间。此外，在这样的示例中，P体区250布置在第一N漂移区170a与第二N漂移区170b之间。
参考图9的示例，可以通过将N型杂质注入至第三体离子注入区280中来形成N-LDD区290。LDD离子注入245是使用栅电极320a和320b作为掩模的离子注入。因为N-LDD区形成在P型体区250上，所以在该阶段中确定沟道区的长度。在本示例中，使用栅电极作为掩模来形成P型体区和N-LDD区。作为结果，该方法意味着，使用用于这样的形成的相同的栅电极来确定沟道长度。通过该技术，不会出现套刻问题。该示例示出与没有涉及光刻工艺所获得的效果相同的效果。
在这样的示例中，LDD离子注入245可以以垂直方向而不倾斜地离子注入掺杂剂。通过执行这样的扩散工艺，N-LDD区290可以被形成为与栅电极320a和320b交叠。从N-LDD区290的一个边缘至第三体离子注入区280的一个边缘测量的长度可以被称为沟道长度。亦即，N-LDD区290的一个边缘可以表示N-LDD区290在朝向栅电极320a和320b的方向上的边缘部分。在这样的示例中，N-LDD区290的横向长度短于第三体离子注入区280的横向长度。
参考图10的示例，在栅电极320a和320b的侧表面上形成间隔物绝缘膜400。此外，使用N+掩模，形成N+源极区410和N+漏极区。如上所述，N+源极区410被形成为与N-LDD区290交叠。N-LDD区290用作栅电极320a和320b与N+源极区之间的连接。此外，在NW区240上形成N+区450。另外，使用P+掩模在PW区220上形成P+接触区440。P+接触区440还形成在P体区250上以便将偏置施加至P体区250。
在形成源极区410和漏极区430之后，可以在基板140以及栅电极320a和320b上形成硅化物层。此外，可以形成接触插塞以将互连线与硅化物层彼此连接。因此，可以以该方式形成N-LDMOS器件100。
图11A至图11D是示出根据另一示例的用于形成半导体器件的方法的图。图11A至图11D的示例的该方法涉及用于在N漂移区170上形成第一体离子注入区260和第二体离子注入区270以及第三体离子注入区280的方法。
参考图11A的示例，在已经形成多晶硅层310的状态下形成P体掩模图案800。此外，当使用不同的离子注入能量时，如图11A的示例中所示，通过P型离子注入在N漂移区170上依次执行第一体离子注入工艺和第二体离子注入工艺225。因为离子被注入成穿过多晶硅层310，所以第一体离子注入区260和第二体离子注入区270相应地形成在多晶硅层的下部上。然而，第一体离子注入区260需要比第二体离子注入区270的离子注入能量更大的离子注入能量。
此外，参考图11B的示例，通过使多晶硅层图案化来形成栅电极320。此外，使用栅电极320作为掩模来执行倾斜离子注入235。在这样的示例中，在N漂移区170的表面上形成第三体离子注入区280。因此，可以通过倾斜离子注入将P型杂质注入至栅电极320的下部中，并且通过倾斜离子注入形成的第三体离子注入区280的横向长度可以相应地长于第一体离子注入区260和第二体离子注入区270的横向长度。执行这样的第一体离子注入工艺至第三体离子注入工艺，以完成用于形成沟道的P体区250。因为P体区250相对于栅电极320以自对准方式形成，所以相应地降低了阈值电压和击穿电压的分散。该效果出现的原因是通过这样的技术降低了光刻工艺的套刻分散。此外，通过数次改变离子注入能量来形成P型体区250的原因是均匀地分布P型体区250的浓度。如果浓度变得均匀，则由此有利于相应地确保半导体器件的开关速度。
参考图11C的示例，使用N型掺杂剂来执行离子注入245以在P体区250上形成N-LDD区290a。在形成间隔物400之前，执行离子注入245。N-LDD区290a被形成为与栅电极320交叠。
参考图11D的示例，在栅电极320的侧表面上形成间隔物400，并且执行离子注入255以便形成N+源极区410。源极区410被形成为与间隔物400对准。源极区410被形成为与N-LDD区290a交叠。
图12A至图12D是示出根据另一示例的用于形成半导体器件的方法的图。
参考图12A的示例，在已经形成多晶硅层310的状态下形成P体掩模图案800。在这样的示例中，可以在P体掩模图案800上形成开口810以暴露多晶硅层310的一部分。参考图12B的示例，通过使用P体掩模图案800蚀刻多晶硅层310来形成栅电极320。栅电极320可以被分为两个部分，并且N漂移区170可以被暴露在两个栅电极320之间。
参考图12C的示例，通过使用栅电极320作为掩模用P型掺杂剂依次执行至N漂移区170中的第一体离子注入和第二体离子注入225以及第三体离子注入235来形成P体区250。在此，使用倾斜的离子注入235来执行第三体离子注入。
参考图12D的示例，在存在P体掩模图案800的状态下，使用N型掺杂剂来连续地执行离子注入245。因此，形成N-LDD区290。剩余的阶段(即间隔物和源极区/漏极区的形成)与以上参考图2至图10以及图11A至图11D的示例描述的阶段相同。
依据根据示例的n-LDMOS器件，使用栅电极作为掩模来形成P体区，并且因此击穿电压和阈值电压的分散相对于彼此变得均匀。此外，可以通过如上进一步讨论的形成PBL层来形成具有高击穿电压的n-LDMOS器件。
相对于根据示例的n-LDMOS器件，可以通过控制注入P型杂质的倾斜角度和P型杂质的浓度来调整沟道长度。因此，可以形成体区250以实现适于半导体器件的尺寸的沟道长度。
尽管本公开内容包括具体的示例，但是在理解本申请的公开内容之后将明显的是，在不偏离权利要求及其等同物的精神和范围的情况下，可以在这些示例中做出形式和细节上的各种改变。本文中描述的示例被认为仅是描述性的，并且不是为了限制的目的。对每个示例中的特征或方面的描述被认为是适于其他示例中的相似特征或方面。如果以不同的顺序来执行所描述的技术，以及/或者如果所描述的系统、架构、器件或电路中的部件以不同的方式被组合和/或被其他部件或其等同物来代替或补充，则可以实现合适的结果。因此，并非通过具体实施方式而是通过权利要求及其等同物来限定本公开内容的范围，并且在权利要求及其等同物的范围内的各种变化被认为包括在本公开内容内。

Claims (17)

1.一种用于制造半导体器件的方法，包括：
在基板上形成栅极绝缘膜和多晶硅层；
通过蚀刻所述多晶硅层来形成多晶硅图案；
通过在所述多晶硅图案上形成掩模图案来在所述多晶硅图案上形成开口，所述开口暴露所述多晶硅图案的一部分；
通过蚀刻经由所述开口暴露的所述多晶硅图案的所述一部分来形成栅电极；
通过使用所述栅电极作为掩模将P型掺杂剂离子注入至所述基板上来形成P型体区；
通过使用所述栅电极作为掩模将N型掺杂剂离子注入至所述基板上来在所述P型体区上形成N型LDD区；
在所述栅电极的侧表面上形成间隔物；以及
在所述间隔物的侧表面上形成N型源极区。
2.根据权利要求1所述的方法，其中，所述P型体区包括多个体离子注入区。
3.根据权利要求1所述的方法，其中，通过使用所述栅电极作为掩模的倾斜离子注入来形成所述P型体区。
4.根据权利要求1所述的方法，其中，所述P型体区被形成为与所述栅电极交叠。
5.根据权利要求1所述的方法，其中，随着所述P型体区变得更接近于所述基板的顶表面，所述P型体区具有更长的宽度。
6.根据权利要求1所述的方法，其中，形成所述栅电极包括形成彼此间隔开的第一栅电极和第二栅电极。
7.根据权利要求1所述的方法，其中，制备所述基板包括：
形成N型埋层、P型埋层和N型漂移区；
形成连接至所述P型埋层的P型阱区；以及
形成连接至所述N型埋层的N型阱区。
8.根据权利要求7所述的方法，其中，所述N型埋层具有比所述P型埋层的长度更大的长度。
9.根据权利要求1所述的方法，其中，所述栅电极由多晶硅、钨(W)、钨氮化物(WN)、钛(Ti)、钼(Mo)、钴(Co)、镍(Ni)、铜(Cu)或铝(Al)形成。
10.根据权利要求1所述的方法，其中，所述栅极绝缘膜由硅氧化物膜(SiO2)或硅氮化物膜(SiN)、硅氮氧化物膜(SiON)和高k材料膜中的任意一种或者任意两种或更多种的任意组合形成。
11.根据权利要求10所述的方法，其中，所述高k材料膜包括铝氧化物(Al2O3)、钽氧化物(Ta2O5)和铪氧化物(HfO2)中的任意一种或者任意两种或更多种的任意组合。
12.一种用于制造半导体器件的方法，包括：
在基板上形成栅极绝缘膜和多晶硅层；
在所述多晶硅层上形成掩模图案；
使用P型掺杂剂执行至所述基板上的离子注入工艺，所述离子注入工艺注入穿过所述多晶硅层的掺杂剂；
通过使用所述掩模图案蚀刻所述多晶硅层来形成栅电极；
通过使用所述栅电极作为掩模执行至所述基板上的二次离子注入来在所述基板上形成与所述栅电极交叠的P型体区；
使用所述栅电极作为掩模来在所述P型体区上形成N型LDD区；
在所述栅电极上形成间隔物；以及
在所述P型体区上形成N型源极区。
13.根据权利要求12所述的方法，还包括：形成与所述栅电极间隔开的N型漏极区。
14.根据权利要求12所述的方法，还包括：在所述基板上形成所述栅极绝缘膜和所述多晶硅层之前，形成接触所述P型体区的P型埋层。
15.一种半导体器件，包括：
在基板上形成的第一传导类型埋层；
第二传导类型埋层，其形成在所述第一传导类型埋层上并且具有比所述第一传导类型埋层的宽度更小的宽度；
在所述第二传导类型埋层上形成的第一传导类型的第一漂移区和第二漂移区；
分别在所述第一漂移区和所述第二漂移区上形成的第一栅电极和第二栅电极；
第二传导类型体区，其布置在所述第一漂移区与所述第二漂移区之间并且连接至所述第二传导类型埋层；以及
第一传导类型源极区，其布置在所述第一漂移区与所述第二漂移区之间并且形成在所述第二传导类型体区上。
16.根据权利要求15所述的半导体器件，还包括：分别与所述第一栅电极和所述第二栅电极间隔开地形成的第一传导类型的第一漏极区和第二漏极区。
17.根据权利要求15所述的半导体器件，其中，所述体区包括具有不同深度的多个体离子注入区。
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