CN110600382B - 一种芯片封装工艺及产品 - Google Patents

一种芯片封装工艺及产品 Download PDF

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CN110600382B
CN110600382B CN201810606043.2A CN201810606043A CN110600382B CN 110600382 B CN110600382 B CN 110600382B CN 201810606043 A CN201810606043 A CN 201810606043A CN 110600382 B CN110600382 B CN 110600382B
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electrode
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conductive metal
metal foil
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何忠亮
徐光泽
沈正
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Shenzhen Dinghua Xintai Technology Co ltd
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Abstract

本发明涉及一种芯片封装工艺及产品，其公开了一种芯片封装工艺，由于采用剥离式封装载板的加工工艺，制作工艺流程更简单、更环保，且芯片布线设计也有了更大自由度，后续封装的效率也获得了极大提高；此外，通过该封装工艺生产出了品质更可靠、应用更广的芯片封装产品，其无电极基板，电极嵌入在封装胶中，由于没有传统QFN电极所附着的筋线的限制，框架间隙更小、所需键合线更少，封装体结构更简单、设计自由度更高、成本更低。本发明可应用于需要进行芯片加工和设计的各种行业。

Description

一种芯片封装工艺及产品
技术领域
本公开属于电子技术领域，特别涉及一种芯片封装工艺及产品。
背景技术
芯片封装是集成电路的重要生产环节之一，在现有技术中，通常采用方形扁平无引脚封装(Quad Flat No-lead Package，QFN)技术，芯片封装通常是在QFN的支架上完成，封装工艺较为复杂，且由于支架蚀刻受限于框架铜厚及支撑筋，使得这类框架的精度和应用大大受限制，难以设计孤岛电极，增加I/O数会带来的生产成本和可靠性问题，限制了芯片和PCB板的设计自由度，不适用于可靠性和自由度要求高的芯片的封装及产业效率的提高。
正是由于现有技术的种种缺陷，目前，亟需获得一种制作工艺流程更为简单环保，且可降低生产成本、提高封装效率的芯片封装工艺，从而获得一种高可靠性和自由度、结构简单、且低成本的芯片封装产品；这对于积极推动我国电子技术相关产业的发展，提升核心竞争力，都具有极为重要的作用。
发明内容
针对现有技术的不足，本发明提出了一种芯片封装工艺及产品，其技术方案为：
一种芯片封装工艺，包括以下步骤：
S1、准备导电金属箔A、粘接层B及承载片C；
S2、在导电金属箔上选择性电镀形成电极，及，贴合导电金属箔A，粘接层B和承载片C；
其中：先在导电金属箔A上选择性电镀形成电极，再进行导电金属箔A、粘接层B和承载片C的贴合；或者先进行导电金属箔A、粘接层B和承载片C的贴合，后在导电金属箔A上选择性电镀形成电极；
S3、除去没有被电极保护的导电金属箔；
S4、在电极上固晶、封胶；
S5、剥离承载片C。
较佳的，其还包括步骤S6、对剥离后加工品的电极底面再次封胶。
较佳的，所述导电金属箔A为铜箔。
较佳的，所述粘接层B为耐高温的可剥胶。
较佳的，所述承载片C为金属，或合成树脂。
较佳的，步骤S2中，所述选择性电镀形成顶电极D及底电极E，该选择性电镀采用感光材料曝光显影、再图形电镀的方式，或采用模板掩模电镀法。
较佳的，所述电极分布为多圈的环形线结构。
较佳的，所述电极为单层金属材料构成，所述单层金属包括如下任一或其合金：铝、金、银、镍、铜；或者，所述电极为多层金属构成，其包括内核金属和表面金属构成的多层结构，其中内核金属和表面金属包括如下任一或其任意组合：银、金、镍、铜。
较佳的，所述电极的纵截面为“T”形结构或“I”形结构。
与上述芯片封装工艺相应的，还公开了一种芯片封装产品，所述芯片封装产品通过上述芯片封装工艺加工获得，其具有无基板的电极结构，包括电极、芯片元件、及封装胶，其中，芯片元件通过固晶形成在电极上，封装胶对上述电极和芯片元件进行封装，所述电极嵌入在封装胶中。
本公开具有以下有益效果：
1、由于采用剥离式封装载板的加工工艺，制作工艺流程更简单、更环保，且芯片布线设计也有了更大自由度，后续封装的效率也获得了极大提高；
2、通过该封装工艺生产出了品质更可靠，应用更广的芯片封装产品，其无电极基板，电极嵌入在封装胶中，由于没有传统QFN电极所附着的筋线的限制，框架间隙更小、所需键合线更少，封装体结构更简单、成本更低；
3、由于工艺中侧刻蚀的存在，其具有“拉后”(pull-back)电极，即，电极在封装胶里电极为上大下小(“T”结构)或中间小两头大(“I”结构)，从而，可将电极牢固地锁定在封装胶里，提高了芯片封装产品的可靠性。
附图说明
图1为本发明中芯片封装工艺的主流程图；
图2为本发明中芯片封装工艺过程中的加工结构图；
图3为本发明一个实施例中芯片封装结构图；
图4为本发明另一个实施例中芯片封装结构图；
其中：1、导体；2、IC芯片；3、键合线；4、电极；5、粘合层；6、载板。
具体实施方式
下面结合附图1至4和具体的实施例对本公开进行具体的说明：
在一个实施例中，本公开提出了一种芯片封装工艺，图1为其主要流程图，所述工艺包括以下步骤：
S1、准备导电金属箔A、粘接层B及承载片C；
S2、在导电金属箔上选择性电镀形成电极，及，贴合导电金属箔A，粘接层B和承载片C；
其中：先在导电金属箔A上选择性电镀形成电极，再进行导电金属箔A、粘接层B和承载片C的贴合；或者先进行导电金属箔A、粘接层B和承载片C的贴合，后在导电金属箔A上选择性电镀形成电极；S3、除去没有被电极保护的导电金属箔；如图2所示；
S4、在电极上固晶、封胶；
S5、剥离承载片C。
在具体的实施例中，对上述各个步骤的工艺进行了进一步更为优化的限定：
在一些实施例中，步骤S1中，所述导电金属箔A为特定厚度的铜箔，依据产品的精度及设计要求选择相应铜厚；所述粘接层B为耐高温的可剥胶，封装体剥离后嵌入封装体的电极上不会留有残胶，粘接层可以为导电可剥胶或其他氧化物粉体填充的可剥胶；所述的承载片C为有一定厚度及刚性的金属片，也可以是合成树脂类如FR4，塑料类，具体依据涨缩系数匹配的原则进行选用；
在一些具体实施例中，步骤S2中，所述选择性电镀形成顶电极D及底电极E，选择性电镀可以采用感光材料的曝光显影，再图形电镀的方式，也可以采用模板掩模电镀法，所述顶电极及底电极是可以直接邦定或焊接的金属镀层；
且，较优的，电极可由单层金属构成，也可以是多层金属构成：当为单层金属材料构成时，所述单层金属包括如下任一或其合金——铝、金、银、镍、铜；当为多层金属构成，其包括内核金属和表面金属构成的多层结构，其中内核金属和表面金属包括如下任一或其任意组合——银、金、镍、铜等，优选的，内核金属为铜。较优的，其电极分布为多圈的环形线结构，如一到三圈(如图3和图4所示)。
在一些具体实施例中，步骤S3中，所述蚀刻除去没有被顶电极D保护的导电金属，得到独立的封装载体；其中抗蚀层可以是顶电极镀层，也可以采用感光材料的图形转移获得；
值得注意的，蚀刻法在去除多余的导电金属箔同时，也会对电极层下面的铜产生侧蚀，在截面方向电极层有T状形成，即，形成“拉后”(pull-back)电极，增加与后续封装材料的结合力；这也是采用该工艺的一个显著的优点。
在一些具体实施例中，步骤S4里，所述封胶所用的胶为保护性的胶体，通常为环氧树脂胶、硅胶、或荧光胶；且较优的，固晶的芯片元件可以设计为任意形状的图形分布，也可以是任意图形的立体组合。
在一些具体实施例中，该工艺还包括步骤S7，对获得的加工品进行分割、测试；更优的，在步骤S7之前还可包括步骤S6，对剥离后加工品的电极底面再次封胶。从而，获得最终合格的芯片封装产品。
基于该工艺的特点，芯片封装产品的布线设计有了更大的自由度，其电极分布可为连续多圈的环形线结构，图3和图4为相应的芯片产品俯视图(左侧为窄边框，右侧为宽边框)，图3中所述电极连续布线两圈，图4中所述电极连续布线三圈。
可见，该制作方法，由于采用剥离式承载片的加工工艺，制作工艺流程也更简单、更环保，且芯片产品的布线设计也有了更大自由度，后续封装的效率也获得了极大提高。
相对应的，本发明还公开了一种芯片封装产品，该产品正是可基于上述芯片封装工艺生产获得：
其采用无基板的电极结构，包括电极、芯片元件、及封装胶，所述芯片元件通过固晶形成在电极上，所述封装胶对上述电极和芯片元件进行封装，所述电极嵌入在封装胶中。
作为显著的优势，由于其采用了无基板的电极结构，电极嵌入在封装胶中，其没有筋线的限制，其框架的间隙可以做到0.05mm甚至更小，封装的效率高、可靠性高、成本低。
且，由于工艺中侧刻蚀的存在，其具有“拉后”(pull-back)电极，即，电极在封装胶里电极为上大下小(“T”结构)或中间小两头大(“I”结构)，从而，可将电极牢固地锁定在封装胶里，提高了芯片封装产品的可靠性。
此外，在具体实际生产加工时，根据不同的应用产业，可选用不同的芯片种类；较优的，该芯片封装产品中可包括一种以上的子芯片，子芯片间通过电极或键合线进行连接。在设计子芯片分布时，优选的，该子芯片的朝向一致，或者键合线的朝向一致，这样可以有利于固晶焊线的效率及后加工的良率。
综上可见，本发明公开了一种芯片封装工艺，由于采用剥离式封装载板的加工工艺，制作工艺流程更简单、更环保，且芯片布线设计也有了更大自由度，后续封装的效率也获得了极大提高；此外，通过该封装工艺生产出了品质更可靠，应用更广的芯片封装产品，其无电极基板，电极嵌入在封装胶中，由于没有传统QFN电极所附着的筋线的限制，框架间隙更小、所需键合线更少，封装体结构更简单、设计自由度更高、成本更低。
以上所述仅为本公开的优选实施例，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (10)

1.一种芯片封装工艺，其特征在于：所述工艺包括以下步骤：
S1、准备导电金属箔A、粘接层B及承载片C；
S2、在导电金属箔上选择性电镀形成电极，及，贴合导电金属箔A，粘接层B和承载片C；
其中：先在导电金属箔A上选择性电镀形成电极，再进行导电金属箔A、粘接层B和承载片C的贴合；或者，先进行导电金属箔A、粘接层B和承载片C的贴合，后在导电金属箔A上选择性电镀形成电极；
S3、除去没有被电极保护的导电金属箔；
S4、在电极上固晶、封胶；
S5、剥离承载片C。
2.根据权利要求1所述的工艺，其特征在于，优选的，其还包括步骤S6、对剥离后加工品的电极底面再次封胶。
3.根据权利要求1所述的工艺，其特征在于：所述导电金属箔A为铜箔。
4.根据权利要求1所述的工艺，其特征在于：所述粘接层B为耐高温的可剥胶。
5.根据权利要求1所述的工艺，其特征在于：所述承载片C为金属，或合成树脂。
6.根据权利要求1所述的工艺，其特征在于：步骤S2中，所述选择性电镀形成顶电极D及底电极E，该选择性电镀采用感光材料曝光显影、再图形电镀的方式，或采用模板掩模电镀法。
7.根据权利要求1所述的工艺，其特征在于：所述电极分布为多圈的环形线结构。
8.根据权利要求1所述的工艺，其特征在于：所述电极为单层金属材料构成，所述单层金属包括如下任一或其合金：铝、金、银、镍、铜；或者，所述电极为多层金属构成，其包括内核金属和表面金属构成的多层结构，其中内核金属和表面金属包括如下任一或其任意组合：银、金、镍、铜。
9.根据权利要求1所述的工艺，其特征在于，所述电极的纵截面为“T”形结构或“I”形结构。
10.一种芯片封装产品，其特征在于，所述芯片封装产品通过如权利要求1-9中任一项所述的芯片封装工艺加工获得，其具有无基板的电极结构，包括电极、芯片元件、及封装胶，其中，芯片元件通过固晶形成在电极上，封装胶对上述电极和芯片元件进行封装，所述电极嵌入在封装胶中。
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