CN110504217A - 晶体管的制造方法及晶体管 - Google Patents
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Abstract
本发明涉及晶体管的制造方法及晶体管,涉及半导体集成电路制造技术,在晶体管的侧墙的形成过程中,将侧墙分两次工艺形成,并使第二次形成的侧墙较易去除,在进行晶体管的轻掺杂漏注入工艺后去除第二次形成的侧墙,然后完成源/漏注入工艺、形成金属栅极以及形成金属互联结构而形成半导体器件中的晶体管,如此在不影响晶体管的期望的源漏极之间的距离,以及栅极到源漏极之间的距离的基础上,减小了由金属栅极和金属互联结构形成的金属电极与位于金属电极之间的介质层形成的电容值,因此可降低电子停留时间,提高组件的运作速度。
Description
技术领域
本发明涉及半导体集成电路制造技术,尤其涉及一种晶体管的制造方法及晶体管。
背景技术
在半导体集成电路制造技术领域,随着半导体技术的发展,半导体器件的尺寸不断减小,然对其性能的要求不断提高,因此对集成电路制造的制程及材料特性的限制也越来越显著。
半导体集成电路通常包括多个晶体管,因此晶体管的性能对半导体集成电路的性能来说至关重要,晶体管包括PMOS管和NMOS管。具体的,请参阅图1,图1为本发明一实施例的包括晶体管的集成电路示意图。如图1所示,一个晶体管通常包括位于半导体衬底100上的金属栅极110、位于金属栅极两侧的源极和漏极(图中未示出)以及将栅极、源极和漏极引出的金属互联结构120。金属互联结构120通常是在通孔中填充金属材料(如,钨)形成。另,更具体的,如图1所示,在金属栅极110的两侧包括侧墙130,侧墙是用来定义轻掺杂漏(LDD)区域和源漏结宽度并在通孔刻蚀时保护栅极的一种工艺,是通过淀积和刻蚀等工艺在栅极的两侧制作而成的结构,侧墙可由氧化硅、氮化硅或氮氧化硅等绝缘材料构成的单层结构,也可以是ONO(氧化硅-氮化硅-氧化硅)等多层结构。
随着半导体技术的进步,希望晶体管的运行速度越来越高,晶体管的运行速度与晶体管中的寄生电容有关,晶体管中的寄生电容越大晶体管的运行速度就越慢。晶体管中的寄生电容通常由晶体管中的金属材料构成的金属电极与位于金属电极之间的绝缘材料形成,如图1所示,两相邻金属栅极110构成的金属电极与位于金属栅极110之间侧墙130即会产生寄生电容,另金属栅极110和金属互联结构120构成的金属电极与位于金属栅极110和金属互联结构120之间侧墙也会产生寄生电容。
寄生电容与绝缘体的介电常数(如侧墙材料的介电常数)及几何尺寸相关,几何尺寸为极板的面积及极板间的距离有关。如何从绝缘体的介电常数及几何尺寸着手降低电路的寄生电容,从而提高半导体器件的性能成为业界研究的中点。
发明内容
本发明的目的在于提供一种晶体管的制造方法,减小了由金属栅极和金属互联结构形成的金属电极与位于金属电极之间的介质层形成的电容值,因此可降低电子停留时间,提高组件的运作速度。
本发明提供的晶体管的制造方法,包括:S1:提供一半导体衬底,在半导体衬底上包括由隔离结构隔离出的多个有源区,在有源区内形成阱结构,并在阱结构区域的半导体衬底表面形成多晶硅栅结构;S2:进行侧墙工艺,在多晶硅栅结构的侧面形成侧墙,其中侧墙包括第一层侧墙和第二层侧墙,并形成第二层侧墙时的沉积工艺为空心阴离子镀沉积;S3:进行轻掺杂漏注入工艺;S4:去除第二层侧墙;S5:进行源/漏注入工艺,多晶硅栅结构的两侧形成晶体管的源区和漏区;S6:去除多晶硅栅极,在多晶硅栅极的去除区域填充金属以形成金属栅极;以及S7:形成将金属栅极、源区和漏区引出的金属互联结构,以形成半导体器件的晶体管。
更进一步的,多晶硅栅结构包括多晶硅栅极和位于多晶硅栅极表面的第一层掩膜层和第二层掩膜层。
更进一步的,第一层掩膜层的材质为氮化硅,第二次掩膜层的材质为氧化硅。
更进一步的,步骤S2为进行第一次沉积工艺以在半导体衬底表面形成一层介质层,进行第一次刻蚀工艺以形成第一层侧墙,然后进行空心阴离子镀沉积工艺以在半导体衬底表面再沉积一层介质层,然后进行第二次刻蚀工艺以形成第二层侧墙。
更进一步的,步骤S2为进行第一次沉积工艺以在半导体衬底表面形成一层介质层,然后进行空心阴离子镀沉积工艺以在半导体衬底表面再沉积一层介质层,然后进行刻蚀工艺以形成第一层侧墙和第二层侧墙。
更进一步的,第一层侧墙较第二层侧墙厚。
更进一步的,第一层侧墙约占第一层侧墙与第二层侧墙的厚度之和的70%。
更进一步的,形成第一层侧墙时的沉积工艺为化学气相沉积或原子层沉积。
更进一步的,在进行“步骤S3:进行轻掺杂漏注入工艺”之后去除第二层侧墙。
更进一步的,采用磷酸湿法工艺去除第二层侧墙。
更进一步的,第一层侧墙与第二层侧墙的材质为氮化硅。
本发明还提供一种晶体管,该晶体管采用上述的晶体管的制造方法制造获得。
更进一步的,位于晶体管的金属栅极两侧的侧墙的厚度小于晶体管的源/漏极到金属栅极之间的距离。
本发明提供的晶体管的制造方法及晶体管,在晶体管的侧墙的形成过程中,将侧墙分两次工艺形成,并使第二次形成的侧墙较易去除,在进行晶体管的轻掺杂漏注入工艺后去除第二次形成的侧墙,然后完成源/漏注入工艺、形成金属栅极以及形成金属互联结构而形成半导体器件中的晶体管,如此在不影响晶体管的期望的源漏极之间的距离,以及栅极到源漏极之间的距离的基础上,减小了由金属栅极和金属互联结构形成的金属电极与位于金属电极之间的介质层形成的电容值,因此可降低电子停留时间,提高组件的运作速度。
附图说明
图1为本发明一实施例的包括晶体管的集成电路示意图。
图2为本发明一实施例的晶体管的制造方法的流程图。
图3a-3c为本发明一实施例的晶体管的制造过程示意图。
具体实施方式
下面将结合附图,对本发明中的技术方案进行清楚、完整的描述,显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例,都属于本发明保护的范围。
为了满足半导体器件对源漏结宽度及性能的要求,并在通孔刻蚀时保护栅极需要保证一定厚度的侧墙,然而如现有技术中所述,厚的侧墙也即意味着位于金属电极之间的绝缘材料较宽,也即增大了金属电极之间的距离,因此会增加寄生电容。本发明一实施例中,在于提供一种晶体管的制造方法,该方法能在满足半导体器件对源漏结宽度及性能要求的基础上,减少寄生电容。
具体的,请参阅图2,图2为本发明一实施例的晶体管的制造方法的流程图。本发明一实施例的晶体管的制造方法,包括:S1:提供一半导体衬底,在半导体衬底上包括由隔离结构隔离出的多个有源区,在有源区内形成阱结构,并在阱结构区域的半导体衬底表面形成多晶硅栅结构;S2:进行侧墙工艺,在多晶硅栅结构的侧面形成侧墙,其中侧墙包括第一层侧墙和第二层侧墙,并形成第二层侧墙时的沉积工艺为空心阴离子镀(HCD,Hollowcathode discharge deposition)沉积;S3:进行轻掺杂漏注入工艺(LDD);S4:去除第二层侧墙;S5:进行源/漏注入工艺,在多晶硅栅结构的两侧形成晶体管的源区和漏区;S6:去除多晶硅栅极,在多晶硅栅极的去除区域填充金属以形成金属栅极;以及S7:形成将金属栅极、源区和漏区引出的金属互联结构,以形成半导体器件的晶体管。
如上所述,现有技术中,侧墙厚度即为期望的栅极到源漏极之间的距离。而本发明,将侧墙分两次工艺形成,并使第二次形成的侧墙较易去除,在进行晶体管的轻掺杂漏注入工艺后去除第二次形成的侧墙,如此在不影响晶体管的期望的源漏极之间的距离,以及栅极到源漏极之间的距离的基础上,减小了由金属栅极和金属互联结构形成的金属电极与位于金属电极之间的介质层(侧墙)形成的电容值,因此可降低电子停留时间,提高晶体管的运作速度。
更具体的,请参阅图3a-3c,图3a-3c为本发明一实施例的晶体管的制造过程示意图。本发明一实施例的晶体管的制造方法,更具体的为:
请参阅图3a,S1:提供一半导体衬底100,在半导体衬底100上包括由隔离结构(图中未示出)隔离出的多个有源区(图中未示出),在有源区内形成阱结构(图中未示出),并在阱结构区域的半导体衬底100表面形成多晶硅栅结构200。
更具体的,请参阅图3a,多晶硅栅结构200包括多晶硅栅极210和位于多晶硅栅极210表面的第一层掩膜层220和第二层掩膜层230。更具体的,在本发明一实施例中,第一层掩膜层220的材质为氮化硅,第二次掩膜层230的材质为氧化硅。
请参阅图3a,S2:进行侧墙工艺,在多晶硅栅结构200的侧面形成侧墙,其中侧墙包括第一层侧墙310和第二层侧墙320,并形成第二层侧墙320时的沉积工艺为空心阴离子镀(HCD,Hollow cathode discharge deposition)沉积。
在本发明一实施例中,更具体的,步骤S2为进行第一次沉积工艺以在半导体衬底100表面形成一层介质层,进行第一次刻蚀工艺以形成第一层侧墙310,然后进行空心阴离子镀(HCD,Hollow cathode discharge deposition)沉积工艺以在半导体衬底100表面再沉积一层介质层,然后进行第二次刻蚀工艺以形成第二层侧墙320。
在本发明一实施例中,更具体的,步骤S2为进行第一次沉积工艺以在半导体衬底100表面形成一层介质层,然后进行空心阴离子镀(HCD,Hollow cathode dischargedeposition)沉积工艺以在半导体衬底100表面再沉积一层介质层,然后进行刻蚀工艺以形成第一层侧墙310和第二层侧墙320。
更具体的,请参阅图3a,在本发明一实施例中,第一层侧墙310较第二层侧墙320厚。更具体的,在本发明一实施例中,第一层侧墙310约占第一层侧墙310与第二层侧墙320的厚度之和的70%,也即,第二层侧墙320约占第一层侧墙310与第二层侧墙320的厚度之和的30%。当然,70%和30%可有一定的偏差,在本发明一实施例中,偏差为5%;较优的,为10%;更优的,为20%。
更具体的,在本发明一实施例中,形成第一层侧墙310时的沉积工艺为化学气相沉积或原子层沉积。
更具体的,在本发明一实施例中,第一层侧墙310与第二层侧墙320的材质为氧化硅、氮化硅或氮氧化硅等绝缘材料构成的单层结构,也可以是ONO(氧化硅-氮化硅-氧化硅)等多层结构。
S3:进行轻掺杂漏注入工艺(LDD)。
S4:去除第二层侧墙320。
更具体的,请参阅图3b,在进行“步骤S3:进行轻掺杂漏注入工艺(LDD)”之后去除第二层侧墙320。如此第一层侧墙310加第二层侧墙320的厚度共同决定了晶体管的源漏极之间的距离,以及栅极到源漏极之间的距离。对应的,本发明中的第一层侧墙310加第二层侧墙320的厚度即为现有技术如图1中的侧墙130的厚度。其可根据实际工艺中期望的源漏极之间的距离,以及栅极到源漏极之间的距离确定。
更具体的,由于在步骤S2中形成第二层侧墙320时的沉积工艺为空心阴离子镀(HCD,Hollow cathode discharge deposition)沉积,该沉积工艺使形成的第二层侧墙320较第一层侧墙310易去除。更具体的,在本发明一实施例中,采用磷酸湿法工艺去除第二层侧墙320。
然后,请参阅图3c,进行S5:进行源/漏注入工艺,在多晶硅栅结构的两侧形成晶体管的源区和漏区(图中未示出);S6:去除多晶硅栅极210,在多晶硅栅极210的去除区域填充金属以形成金属栅极400;S7:形成将金属栅极400、源区和漏区引出的金属互联结构500,以形成包括晶体管的半导体器件。
如此,如图3c所示,位于金属栅极400与金属互联结构500之间的介质层仅为第一层侧墙310,经去除第二层侧墙320后,较现有技术中如图1所示的侧墙130薄,因此可以减小由金属栅极400和金属互联结构500形成的金属电极与位于金属电极之间的介质层(侧墙)的电容值,因此可降低电子停留时间,提高组件的运作速度。
更具体的,在本发明一实施例中,还提供一种晶体管,该晶体管采用上述晶体管的制造方法制造获得。
并更具体的,在本发明一实施例中,位于晶体管的金属栅极400两侧的侧墙的厚度小于晶体管的源/漏极到金属栅极400之间的距离。而现有技术中,如图1所示,位于晶体管的金属栅极110两侧的侧墙130的厚度等于晶体管的源/漏极到金属栅极110之间的距离。由此,本发明减小了位于由金属栅极与金属互联结构形成的金属电极之间的介质层的厚度,因此减小了由金属栅极和金属互联结构形成的金属电极与位于金属电极之间的介质层形成的电容值,降低电子停留时间,提高了组件的运作速度。
综上所述,在晶体管的侧墙的形成过程中,将侧墙分两次工艺形成,并使第二次形成的侧墙较易去除,在进行晶体管的轻掺杂漏注入工艺后去除第二次形成的侧墙,然后完成源/漏注入工艺、形成金属栅极以及形成金属互联结构而形成半导体器件中的晶体管,如此在不影响晶体管的期望的源漏极之间的距离,以及栅极到源漏极之间的距离的基础上,减小了由金属栅极和金属互联结构形成的金属电极与位于金属电极之间的介质层形成的电容值,因此可降低电子停留时间,提高组件的运作速度。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
Claims (13)
1.一种晶体管的制造方法,其特征在于,包括:
S1:提供一半导体衬底,在半导体衬底上包括由隔离结构隔离出的多个有源区,在有源区内形成阱结构,并在阱结构区域的半导体衬底表面形成多晶硅栅结构;
S2:进行侧墙工艺,在多晶硅栅结构的侧面形成侧墙,其中侧墙包括第一层侧墙和第二层侧墙,并形成第二层侧墙时的沉积工艺为空心阴离子镀沉积;
S3:进行轻掺杂漏注入工艺;
S4:去除第二层侧墙;
S5:进行源/漏注入工艺,在多晶硅栅结构的两侧形成晶体管的源区和漏区;
S6:去除多晶硅栅极,在多晶硅栅极的去除区域填充金属以形成金属栅极;以及
S7:形成将金属栅极、源区和漏区引出的金属互联结构,以形成半导体器件的晶体管。
2.根据权利要求1所述的晶体管的制造方法,其特征在于,多晶硅栅结构包括多晶硅栅极和位于多晶硅栅极表面的第一层掩膜层和第二层掩膜层。
3.根据权利要求2所述的晶体管的制造方法,其特征在于,第一层掩膜层的材质为氮化硅,第二次掩膜层的材质为氧化硅。
4.根据权利要求1所述的晶体管的制造方法,其特征在于,步骤S2为进行第一次沉积工艺以在半导体衬底表面形成一层介质层,进行第一次刻蚀工艺以形成第一层侧墙,然后进行空心阴离子镀沉积工艺以在半导体衬底表面再沉积一层介质层,然后进行第二次刻蚀工艺以形成第二层侧墙。
5.根据权利要求1所述的晶体管的制造方法,其特征在于,步骤S2为进行第一次沉积工艺以在半导体衬底表面形成一层介质层,然后进行空心阴离子镀沉积工艺以在半导体衬底表面再沉积一层介质层,然后进行刻蚀工艺以形成第一层侧墙和第二层侧墙。
6.根据权利要求1所述的晶体管的制造方法,其特征在于,第一层侧墙较第二层侧墙厚。
7.根据权利要求6所述的晶体管的制造方法,其特征在于,第一层侧墙约占第一层侧墙与第二层侧墙的厚度之和的70%。
8.根据权利要求1所述的晶体管的制造方法,其特征在于,形成第一层侧墙时的沉积工艺为化学气相沉积或原子层沉积。
9.根据权利要求1所述的晶体管的制造方法,其特征在于,在进行“步骤S3:进行轻掺杂漏注入工艺”之后去除第二层侧墙。
10.根据权利要求1所述的晶体管的制造方法,其特征在于,采用磷酸湿法工艺去除第二层侧墙。
11.根据权利要求1所述的晶体管的制造方法,其特征在于,第一层侧墙与第二层侧墙的材质为氮化硅。
12.一种晶体管,其特征在于,该晶体管根据权利要求1所述的晶体管的制造方法制造获得。
13.根据权利要求12所述的晶体管,其特征在于,位于晶体管的金属栅极两侧的侧墙的厚度小于晶体管的源/漏极到金属栅极之间的距离。
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