CN110391225A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN110391225A
CN110391225A CN201910295529.3A CN201910295529A CN110391225A CN 110391225 A CN110391225 A CN 110391225A CN 201910295529 A CN201910295529 A CN 201910295529A CN 110391225 A CN110391225 A CN 110391225A
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layer
wiring region
semiconductor substrate
semiconductor device
unit area
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CN110391225B (zh
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吉田拓弥
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Mitsubishi Corp
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Mitsubishi Corp
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Abstract

本发明得到不会增加制造工序，能够抑制恢复电流的增大，实现高耐压、高耐破坏量的半导体装置。半导体基板(6)具有单元区域、终端区域以及配线区域，该终端区域配置于单元区域的外周。IGBT设于单元区域。在配线区域，绝缘膜(16)设于半导体基板(6)之上。与IGBT的栅极连接的栅极电极(17、18)设于绝缘膜(16)之上。p阱层(15)在终端区域设于半导体基板(6)的表面。二极管设于配线区域。二极管具有：p基极层(8)，其设于半导体基板(6)的表面；以及n阴极层(21)，其设于半导体基板(6)的背面。p基极层(8)共通地设于配线区域和单元区域，与p阱层(15)相比杂质浓度低、深度浅。

Description

半导体装置
技术领域
本发明涉及具有晶体管和续流二极管的、具有逆导通特性的半导体装置。
背景技术
对于绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor： IGBT)、功率MOSFET或二极管等功率半导体装置，谋求由导通状态下的稳态损耗和通断时的通断损耗之和构成的功率损耗的降低。对此，通过进行器件构造设计的优化来适应该市场要求。这些功率半导体装置通常大多被用作逆变器装置，该逆变器装置是将开关元件和与其反向并联连接的续流二极管组合多个而得到的。
逆导通型IGBT(Reverse Conducting Insulated Gate Bipolar Transistor，以下记载为RC-IGBT)是将IGBT和续流二极管的功能集成到一个半导体基板、即以1个芯片形成的器件。与通常的将IGBT 的芯片和续流二极管的芯片独立地进行组合的逆变器电路相比，如果由RC-IGBT构成逆变器电路，则能够将芯片数量减半，能够实现小型化、低成本化。像这样除了降低功率损耗之外还以小型化和低成本化为目的而进行着RC-IGBT的开发。
RC-IGBT中的IGBT和续流二极管设置在单元区域，该单元区域以通过向半导体基板的表、背面的电极施加电压而在半导体基板的纵向流过电流的方式进行动作。在单元区域的外周部配置有用于保持耐压的终端区域。在单元区域和终端区域之间或在单元区域之间配置有配线区域。在配线区域设有导线接合用栅极焊盘、以及将栅极焊盘和单元区域的IGBT单元的栅极之间电连接的栅极配线。在终端区域以及配线区域设有杂质浓度高、深度深的扩散层，在对半导体装置施加了反向偏置时向这些区域施加的电场得到缓和。另外，终端区域以及配线区域是无效区域，该无效区域是在构成pnp或npn双极型晶体管而施加了正向偏置时不流过电流，有意地不作为半导体装置进行动作的区域。
由于这样的无效区域宽，因此为了获得期望的性能，需要扩大单元区域，增大半导体装置的尺寸。对此，提出有如下构造：通过在配线区域在基板背面形成n阴极层，从而有意地作为二极管动作，扩大了有效区域(例如，参照专利文献1)。由此，能够提高二极管的性能。
专利文献1：日本特开2009-267394号公报
但是，与终端区域相同地，在配线区域形成有杂质浓度高、深度深的p+阱层而作为阳极层。因此，存在恢复电流增大的问题。为了防止这个问题，也可以在配线区域局部性地照射电子束或者氦束而控制寿命，或者在其他工序中在配线区域形成低浓度的阳极层，但是会增加制造工序。另外，在配线区域以及终端区域，如果将基板表面的p层的杂质浓度变低、使深度变浅，则担心耐压会降低，会有急剧的通断动作时的破坏等。
发明内容
本发明是为了解决上述问题而提出的，其目的在于获得不会增加制造工序，能够抑制恢复电流的增大，实现高耐压和高耐破坏量的半导体装置。
本发明涉及的半导体装置的特征在于，具有：半导体基板，其具有单元区域、终端区域以及配线区域，该终端区域配置于所述单元区域的外周；IGBT，其设于所述单元区域；绝缘膜，其在所述配线区域设于所述半导体基板之上；栅极电极，其设于所述绝缘膜之上，与所述IGBT的栅极连接；p阱层，其在所述终端区域设于所述半导体基板的表面；以及二极管，其设于所述配线区域，所述二极管具有设于所述半导体基板的所述表面的p基极层、以及设于所述半导体基板的背面的n阴极层，所述p基极层共通地设于所述配线区域和所述单元区域，与所述p阱层相比杂质浓度低、深度浅。
发明的效果
在本发明中，设于配线区域的二极管的p基极层与终端区域的p 阱层相比杂质浓度低、深度浅。由此，能够降低空穴的供给量，抑制恢复电流的增大。另外，由于二极管的p基极层共通地设于配线区域和单元区域，所以不会为了形成二极管而增加制造工序。另外，通过将杂质浓度高、深度深的p阱层形成于终端区域，从而能够抑制在终端区域产生的电场集中，实现高耐压、高耐破坏量。
附图说明
图1是表示实施方式1涉及的半导体装置的区域的俯视图。
图2是表示实施方式1涉及的半导体基板的俯视图。
图3是表示实施方式1涉及的半导体基板的仰视图。
图4是表示实施方式1涉及的半导体装置的剖面图。
图5是表示对比例涉及的半导体装置的剖面图。
图6是表示实施方式2涉及的半导体装置的剖面图。
图7是表示实施方式3涉及的半导体装置的剖面图。
图8是表示实施方式4涉及的半导体装置的剖面图。
图9是表示实施方式5涉及的半导体装置的剖面图。
图10是表示实施方式6涉及的半导体装置的剖面图。
标号的说明
6半导体基板，7 n-漂移层，8 p基极层，13表面电极， 15 p+阱层，16绝缘膜，17、18栅极电极，21 n+阴极层，24 p+发射极层。
具体实施方式
参照附图说明实施方式涉及的半导体装置。对于相同或对应的结构要素标注相同的标号，有时省略重复的说明。
实施方式1
图1是表示实施方式1涉及的半导体装置的区域的俯视图。在 RC-IGBT的单元区域1的外周配置有用于保持耐压的终端区域2。在单元区域1和终端区域2之间或者在单元区域1之间配置有配线区域 3。在该配线区域3设有栅极配线4以及栅极焊盘5。另外，为了与终端区域2区分，将包含单元区域1的由配线区域3包围的区域称为有源区域。
图2是表示实施方式1涉及的半导体基板的俯视图。图3是表示实施方式1涉及的半导体基板的仰视图。图4是表示实施方式1 涉及的半导体装置的剖面图，与图1～图3的沿Ⅰ-Ⅱ的剖面图对应。在单元区域设有IGBT以及续流二极管。
半导体基板6的n-漂移层7在整个区域是共通的。在单元区域以及配线区域，在半导体基板6的n-漂移层7之上设有p基极层8。在IGBT处，在p基极层8的表面设有n+发射极层9以及p+发射极层10。在贯穿n+发射极层9的沟槽内隔着栅极氧化膜11设有由多晶硅形成的沟槽栅极12。在续流二极管处，在p基极层8的表面设有 p+发射极层10。另外，为了保持耐压，在续流二极管也设有沟槽，但与沟槽栅极12电气分离以不作为栅极起作用。表面电极13与p基极层8、n+发射极层9以及p+发射极层10连接。通过层间绝缘膜 14使得沟槽栅极12和表面电极13电气分离。
此外，续流二极管的p基极层8以及p+发射极层10作为二极管的阳极电极起作用。为了低成本地进行制造，同时形成续流二极管和 IGBT的p基极层8以及p+发射极层10。但是，也可以重视性能方面而分别形成续流二极管和IGBT。
多个p+阱层15在终端区域局部性地设于半导体基板6的表面。如图2所示，在半导体基板6的表面，多个p+阱层15包围单元区域以及配线区域的p基极层8。最内侧的p+阱层15与p基极层8接触。通过将两者设为相同电位，从而能够缓和在单元区域或配线区域的终端侧产生的电场集中。
在配线区域以及终端区域，绝缘膜16设于半导体基板6之上。与IGBT的栅极连接的栅极电极17、18设于绝缘膜16之上。通过绝缘膜16使得p+阱层15与栅极电极17、18电分离。栅极电极17、18 与图1的栅极配线4或栅极焊盘5对应。
在整个区域共通地在n-漂移层7之下设有n缓冲层19。在IGBT 和终端区域，在n缓冲层19之下设有p集电极层20。在续流二极管以及配线区域，在n缓冲层19之下设有n+阴极层21。在整个区域共通地在p集电极层20以及n+阴极层21之下设有背面电极23。
由在配线区域设于半导体基板6的表面的p基极层8和设于半导体基板6的背面的n+阴极层21构成二极管。p基极层8与p+阱层 15相比杂质浓度低、深度浅。在终端区域，在半导体基板6的背面侧设有p集电极层20而构成pnp双极型晶体管，由此，成为有意地不使电流流过的构造。
接着，与对比例进行比较来说明本实施方式的效果。图5是表示对比例涉及的半导体装置的剖面图。在对比例中，与终端区域同样地，在配线区域将杂质浓度高、深度深的p+阱层15形成为阳极层。因此，恢复电流增大。与此相对，在本实施方式中，设于配线区域的二极管的p基极层8与终端区域的p+阱层15相比，杂质浓度低、深度浅。由此，能够降低空穴的供给量，抑制恢复电流的增大。
另外，在本实施方式中，由于二极管的p基极层8共通地设置于配线区域和单元区域，所以不会为了形成二极管而增加制造工序。另外，通过将杂质浓度高、深度深的p+阱层15形成于终端区域，从而能够抑制在终端区域产生的电场集中，实现高耐压、高耐破坏量。
实施方式2
图6是表示实施方式2涉及的半导体装置的剖面图。在本实施方式中，使从杂质浓度高、深度深的p+阱层15到n+阴极层21的距离D1大于或等于p+阱层15正下方的n-漂移层7的厚度t。这样，通过增大从p+阱层15到n+阴极层21的距离D1，从而能够抑制来自n+阴极层21的空穴的供给，降低恢复电流。另外，在将空穴从表面的 p+阱层15向背面的n+阴极层21扩散的角度设为45°的情况下，为了抑制来自n+阴极层21的空穴的供给，只要距离D1大于或等于n-漂移层7的厚度t即可。
实施方式3
图7是表示实施方式3涉及的半导体装置的剖面图。在本实施方式中，比p基极层8杂质浓度高的p+发射极层24在配线区域设于 p基极层8的表面。由此，能够降低与表面电极13的接触电阻，降低正向损耗。特别是，在表面电极13形成Ti、TiN、TiW等阻挡金属的情况下，通过提高接合表面的杂质浓度，能够获得与阻挡金属的良好的欧姆接触。
另外，p+发射极层24相对于p+阱层15离开的距离为D2，为了不使它们耦合在两者之间设有杂质浓度比较低的p基极层8。因此，能够抑制来自p+阱层15的空穴的供给，抑制恢复电流的增加。
另外，配线区域的p+发射极层24与IGBT以及续流二极管的p+发射极层10的杂质浓度以及深度相同。因此，p+发射极层24能够与 p+发射极层10同时形成，所以不需要新的制造工序。
实施方式4
图8是表示实施方式4涉及的半导体装置的剖面图。在本实施方式中，p+发射极层24在配线区域局部地设于与表面电极13连接的部分，不设于栅极配线4之下。这样，通过仅在与表面电极13接合的部分形成p+发射极层24，从而能够一边维持与表面电极13的良好的欧姆接触性能，一边削减杂质浓度高的p+发射极层24的体积而降低恢复电流。
实施方式5
图9是表示实施方式5涉及的半导体装置的剖面图。在本实施方式中，使从p+阱层15到n+阴极层21的距离D1大于或等于n-漂移层7的厚度t。并且，比p基极层8杂质浓度高的p+发射极层24在配线区域设于p基极层8的表面。由此，能够获得实施方式2以及3 的效果。
实施方式6
图10是表示实施方式6涉及的半导体装置的剖面图。在本实施方式中，使从p+阱层15到n+阴极层21的距离D1大于或等于n-漂移层7的厚度t。并且，p+发射极层24在配线区域局部地设于与表面电极13连接的部分，不设于栅极配线4之下。由此，能够获得实施方式2以及4的效果。
此外，半导体基板6不限于由硅形成，也可以由与硅相比带隙宽的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或金刚石。由这样的宽带隙半导体形成的半导体装置的耐电压性、容许电流密度高，所以能够小型化。通过使用该小型化的半导体装置，从而组装有该半导体装置的半导体模块也能够小型化、高集成化。另外，由于半导体装置的耐热性高，所以能够将散热器的散热鳍片小型化，能够将水冷部空冷化，所以能够使半导体模块进一步小型化。另外，由于半导体装置的电力损耗低而高效，所以能够使半导体装置高效化。

Claims (5)

1.一种半导体装置，其特征在于，
具有：
半导体基板，其具有单元区域、终端区域以及配线区域，该终端区域配置于所述单元区域的外周；
IGBT，其设于所述单元区域；
绝缘膜，其在所述配线区域设于所述半导体基板之上；
栅极电极，其设于所述绝缘膜之上，与所述IGBT的栅极连接；
p阱层，其在所述终端区域设于所述半导体基板的表面；以及
二极管，其设于所述配线区域，
所述二极管具有设于所述半导体基板的所述表面的p基极层、以及设于所述半导体基板的背面的n阴极层，
所述p基极层共通地设于所述配线区域和所述单元区域，与所述p阱层相比杂质浓度低、深度浅。
2.根据权利要求1所述的半导体装置，其特征在于，
在所述半导体基板，在所述p基极层和所述n阴极层之间设有n漂移层，
从所述p阱层到所述n阴极层的距离大于或等于所述n漂移层的厚度。
3.根据权利要求1或2所述的半导体装置，其特征在于，
还具有：
p发射极层，其在所述配线区域设于所述p基极层的表面，比所述p基极层杂质浓度高；以及
表面电极，其与所述p基极层以及所述p发射极层连接，
所述p发射极层与所述p阱层分离。
4.根据权利要求3所述的半导体装置，其特征在于，
所述p发射极层局部地设于与所述表面电极连接的部分。
5.根据权利要求1～4中任一项所述的半导体装置，其特征在于，
所述半导体基板由宽带隙半导体形成。
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