CN110391200B - 显示结构及其制备方法、显示装置 - Google Patents

显示结构及其制备方法、显示装置 Download PDF

Info

Publication number
CN110391200B
CN110391200B CN201910734585.2A CN201910734585A CN110391200B CN 110391200 B CN110391200 B CN 110391200B CN 201910734585 A CN201910734585 A CN 201910734585A CN 110391200 B CN110391200 B CN 110391200B
Authority
CN
China
Prior art keywords
electrode
flexible
substrate
layer
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910734585.2A
Other languages
English (en)
Other versions
CN110391200A (zh
Inventor
刘英伟
王珂
梁志伟
狄沐昕
曹占锋
梁爽
袁广才
姚琪
刘冬妮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201910734585.2A priority Critical patent/CN110391200B/zh
Publication of CN110391200A publication Critical patent/CN110391200A/zh
Priority to US16/920,771 priority patent/US11424232B2/en
Application granted granted Critical
Publication of CN110391200B publication Critical patent/CN110391200B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32111—Disposition the layer connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/3223—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供了一种显示结构及其制备方法、显示装置，该显示结构包括叠加设置的柔性背板以及显示基板，所述柔性背板包括用于与集成电路芯片绑定的绑定电极，所述柔性背板弯曲以形成弯曲部，所述绑定电极位于所述弯曲部上；从而实现窄边框或无边框的背板。

Description

显示结构及其制备方法、显示装置
技术领域
本发明涉及显示技术领域，具体涉及一种显示结构及其制备方法、显示装置。
背景技术
作为显示技术和发光二极管发光技术结合的复合集成技术，微发光二极管(Mini/Micro LED)拥有自发光、高效率、低功耗、高集成、高稳定性等诸多优点，具有广阔的市场前景。微发光二极管显示技术，需要将千万级别的RGB或单色微发光二极管芯片转移显示基板以实现大尺寸显示。为实现微发光二极管显示的大尺寸拼接，需要背板具有极窄的边框。然而，现有微发光二极管显示技术中，背板与显示基板贴合后，无法实现窄边框或无边框的背板。
发明内容
本发明实施例所要解决的技术问题是，提供一种显示结构及其制备方法、显示装置，从而实现窄边框或无边框的背板。
为了解决上述技术问题，本发明实施例提供了一种显示结构，包括叠加设置的柔性背板以及显示基板，所述柔性背板包括用于与集成电路芯片绑定的绑定电极，所述柔性背板弯曲以形成弯曲部，所述绑定电极位于所述弯曲部上。
可选地，所述绑定电极连接有集成电路芯片。
可选地，所述显示基板覆盖所述集成电路芯片。
可选地，所述显示基板包括基板衬底以及形成于所述基板衬底之上的驱动电路层，所述驱动电路层包括连接电极以及将所述连接电极与所述柔性背板连通的贯穿孔。
可选地，所述贯穿孔分别将所述驱动电路层和所述基板衬底贯穿。
可选地，所述柔性背板还包括柔性衬底、形成于所述柔性衬底之上的隔垫柱以及形成于所述柔性衬底和所述隔垫柱之上的第一电极层，所述隔垫柱插接于所述贯穿孔内，使所述隔垫柱上的第一电极层与所述连接电极电连接。
可选地，所述贯穿孔内设有导电胶层，所述导电胶层将所述第一电极层与所述连接电极电连接。
可选地，所述柔性背板还包括形成于除所述隔垫柱以外的第一电极层之上的钝化层，所述钝化层上开设有与所述第一电极层连通的开孔，所述绑定电极形成于所述钝化层之上，并贯穿所述开孔与所述第一电极层电连接。
可选地，所述柔性背板还包括柔性衬底以及形成于所述柔性衬底之上的第一电极层，所述第一电极层之上形成有金属导电层，所述金属导电层贯穿所述贯穿孔，与所述连接电极电连接。
可选地，所述柔性背板之上设有耐热胶层，所述耐热胶层位于所述柔性背板与所述显示基板之间。
本发明实施例还提供了一种显示装置，包括前述的显示结构。
为了解决上述技术问题，本发明实施例还提供了一种显示结构的制备方法，包括：
将显示基板与柔性背板贴合；
将所述柔性背板弯曲以形成弯曲部，并使所述柔性背板上的绑定电极位于所述弯曲部上。
本发明提供了一种显示结构及其制备方法、显示装置，在显示基板与柔性背板贴合后，通过将柔性背板弯曲，使柔性背板上的绑定电极位于弯曲部上，从而增加了绑定电极的绑定空间，方便绑定电极绑定。同时，绑定电极位于弯曲部上，使绑定电极能够被显示基板覆盖，即绑定电极能够位于显示基板的下方，从而使集成电路芯片与绑定电极绑定后能够被显示基板覆盖，从而使背板无需设置边框以用于容纳绑定电极与集成电路芯片的绑定，实现窄边框或无边框的背板。
本发明通过柔性背板上的隔垫柱与显示基板上的贯穿孔配合，实现柔性背板上的第一电极层与显示基板的连接电极的电连接，从而避免因贯穿孔内金属填充物与显示基板的热膨胀系数差异，在高温下，金属填充物膨胀导致显示基板断线的发生。
本发明通过将绑定电极设置于柔性背板的弯曲部上，避免因为双面裸露在外造成转移微发光二极管，同时，避免在绑定电极与集成电路芯片绑定过程中的电路划伤，以及绑定过程中的高温对显示基板以及微发光二极管的影响，减少不良。
当然，实施本发明的任一产品或方法并不一定需要同时达到以上所述的所有优点。本发明的其它特征和优点将在随后的说明书实施例中阐述，并且，部分地从说明书实施例中变得显而易见，或者通过实施本发明而了解。本发明实施例的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本发明的技术方案，并不构成对本发明技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本发明内容。
图1为本发明显示结构的结构示意图；
图2为本发明显示结构第一实施例中绑定电极与集成电路芯片绑定后的结构示意图；
图3为本发明显示结构第一实施例中显示基板的结构示意图；
图4为本发明显示结构第一实施例中柔性背板的结构示意图；
图5为本发明显示结构第一实施例中显示基板与柔性背板贴合后的结构示意图；
图6为本发明显示结构第二实施例中绑定电极与集成电路芯片绑定后的结构示意图。
附图标记说明:
1-柔性背板； 2-显示基板； 3-绑定电极；
4-弯曲部； 5-集成电路芯片； 6-耐热胶层；
101-柔性衬底； 102-隔垫柱； 103-第一电极层；
104-钝化层； 105-金属导电层； 201-基板衬底；
202-驱动电路层； 2021-接触电极； 2022-连接电极；
2023-贯穿孔； 2024-导电胶层。
具体实施方式
下面结合附图和实施例对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
图1为本发明显示结构的结构示意图。如图1所示，为了解决实现窄边框或无边框背板等问题。本发明提供一种显示结构，包括叠加设置的柔性背板1以及显示基板2，所述柔性背板1包括用于与集成电路芯片绑定的绑定电极3，所述柔性背板1沿着远离显示基板2的方向弯曲，以形成弯曲部4，所述绑定电极3位于所述弯曲部4上。本发明通过将柔性背板弯曲，使柔性背板上的绑定电极位于弯曲部上，从而增加了绑定电极的绑定空间，方便绑定电极绑定。同时，绑定电极位于弯曲部上，使绑定电极能够被显示基板覆盖，即绑定电极能够位于显示基板的下方，从而使集成电路芯片与绑定电极绑定后能够被显示基板覆盖，从而无需设置边框以用于绑定电极的绑定，实现窄边框或无边框的背板。
下面通过具体实施例，详细说明本发明的技术方案。
第一实施例
如图1所示，本发明提供一种显示结构，包括叠加设置的柔性背板1以及显示基板2，所述柔性背板1包括用于与集成电路芯片绑定的绑定电极3，所述柔性背板1的边部沿着远离显示基板2的方向弯曲，以形成弯曲部4，所述绑定电极3位于所述弯曲部4上。
图2为本发明显示结构第一实施例中绑定电极与集成电路芯片绑定后的结构示意图。如图2所示，柔性背板1的弯曲部4被显示基板2完全覆盖，即柔性背板1的弯曲部4位于显示基板2的正下方。弯曲部4上的绑定电极3连接有集成电路芯片5。集成电路芯片5与绑定电极3绑定后，被显示基板2完全覆盖，即集成电路芯片5位于显示基板2的正下方。从而使背板无需设置边框以用于容纳绑定电极3与集成电路芯片5的绑定，实现窄边框或无边框的背板。
本发明通过将绑定电极3设置于柔性背板1的弯曲部4上，避免因为双面裸露在外造成转移微发光二极管，同时，避免在绑定电极3与集成电路芯片5绑定过程中的电路划伤，以及绑定过程中的高温对显示基板以及微发光二极管的影响，减少不良。
图3为本发明显示结构第一实施例中显示基板的结构示意图。如图3所示，显示基板2包括基板衬底201以及形成于所述基板201衬底之上的驱动电路层202，所述驱动电路层202包括公共电极、薄膜晶体管、辅助电极、接触电极2021以及连接电极2022。接触电极2021用于与设置于显示基板之上的发光单元连接。其中，发光单元为OLED发光单元。连接电极2022位于驱动电路层202的顶部，与接触电极2021连接，用于将接触电极2021与柔性背板1上的第一电极层电连接，使柔性背板1实现对显示基板2的电连接。驱动电路层202还包括将连接电极2022与柔性背板1连通的贯穿孔2023，贯穿孔2023分别将驱动电路层202和基板衬底201贯穿。
现有技术中显示基板与柔性背板的连接方式，一般采用将显示基板与柔性背板贴合后，在贯穿孔中填充金属填充物，以金属铜为主，通过贯穿孔内的金属填充物实现将显示基板的接触电极与柔性背板上的第一电极层电连接。然而，由于高厚度的金属填充物与显示基板材质的热膨胀系数存在差异，在显示基板制程中的高温退火或者高温沉积薄膜等工艺过程中，在高温下，金属填充物会发生膨胀突出的情况，显示基板上与金属填充物接触的金属会在金属填充物与显示基板接触处发生断裂，使显示基板发生断线，导致显示基板电路的断路。
图4为本发明显示结构第一实施例中柔性背板的结构示意图。如图1和图4所示，为了解决上述显示基板由于金属填充物热膨胀导致显示基板电路断路的问题，本发明实施例的柔性背板1包括柔性衬底101、形成于柔性衬底101靠近显示基板2一侧的隔垫柱102以及形成于柔性衬底101和隔垫柱102之上的第一电极层103。当柔性背板1与显示基板2贴合后，隔垫柱102插接于显示基板2的贯穿孔内，使隔垫柱102上的第一电极层103与显示基板2上的连接电极电连接，从而实现柔性背板1与显示基板2的电连接。其中，隔垫柱102为高度大于10um的可图形化的树脂曝光形成的图形。
本实施例通过柔性背板上的隔垫柱与显示基板上的贯穿孔配合，实现柔性背板上的第一电极层与显示基板的连接电极电连接，从而避免因贯穿孔内金属填充物与显示基板的热膨胀系数差异，在高温下，金属填充物膨胀导致显示基板断线的发生。
如图1所示，显示基板2的贯穿孔2023内设有导电胶层2024，导电胶层2024用于填充隔垫柱102与贯穿孔2023之间的空隙，并将隔垫柱102上的第一电极层与显示基板2上的连接电极电连接。
如图1所示，柔性背板1之上还设有耐热胶层6，耐热胶层6位于柔性背板1与显示基板2之间，用于将柔性背板1与显示基板2贴合。
下面通过本实施例显示结构的制备过程进一步说明本实施例的技术方案。显示结构的制备过程包括：
(1)形成显示基板。形成显示基板包括：在第一玻璃基板表面涂覆聚酰亚胺层(PI层)，形成基板衬底201，并刻蚀出电极孔，孔径小于像素尺寸；然后按照常规构图工艺在基板衬底201之上制备公共电极、薄膜晶体管、辅助电极、接触电极2021以及连接电极2022，形成驱动电路层202；其中，连接电极2022与接触电极2021电连接，连接电极2022与接触电极2021均位于驱动电路层202的顶部；在制备上述图案的过程中，在基板衬底201的电极孔区域不留任何图形，以形成贯穿驱动电路层202和基板衬底201的贯穿孔2023；最后将第一玻璃基板剥离，形成显示基板2，如图3所示。
(2)形成柔性背板。形成柔性背板包括：在第二玻璃基板表面涂覆聚酰亚胺层(PI层)，形成柔性衬底101；然后在柔性衬底101之上沉积高厚度的隔垫柱102；在隔垫柱102以及柔性衬底101之上形成第一电极层103；在第一电极层103之上形成钝化层104，钝化层104覆盖除隔垫柱102以外的第一电极层103之上；在钝化层104上开设有与第一电极层103连通的第一开孔；在钝化层104之上形成绑定电极3，绑定电极3贯穿钝化层104上的第一开孔，与第一电极层103电连接；最后在钝化层104之上形成耐热胶层6，如图4所示。
(3)将显示基板与柔性背板贴合。将显示基板与柔性背板贴合包括：将显示基板2的基板衬底201与柔性背板1上的耐热胶层6贴合，并使柔性背板1上的隔垫柱102插接于显示基板2上的贯穿孔2023内；然后在贯穿孔2023内形成导电胶层2024，导电胶层2024将隔垫柱102上的第一电极层与显示基板2上的连接电极2022电连接；其中，导电胶层2024的材质为银胶或者铜胶，如图5所示。
(4)将柔性背板与集成电路芯片绑定。将柔性背板与集成电路芯片绑定包括：将柔性背板1设置有绑定电极3的部分沿着远离显示基板2的方向弯曲，以形成弯曲部4，并使绑定电极3位于弯曲部4上；然后将集成电路芯片5与绑定电极3绑定，使集成电路芯片5位于显示基板2的下方，如图2所示。
第二实施例
图6为本发明显示结构第二实施例中绑定电极与集成电路芯片绑定后的结构示意图。如图6所示，基于前述实施例的技术构思，本发明还提供了一种显示结构，本发明第二实施例的显示结构与第一实施例的显示结构的区别在于：柔性背板1包括柔性衬底、形成于柔性衬底之上的第一电极层以及形成于第一电极层之上的金属导电层105，金属导电层105将柔性背板1的第一电极层与显示基板2的连接电极电连接。
实施例中，形成金属导电层的方法包括：
(1)形成柔性背板。形成柔性背板包括：形成柔性衬底；在柔性衬底之上形成第一电极层；在第一电极层之上形成钝化层，在钝化层上刻蚀出与第一电极层连通的通孔；在钝化层之上形成耐热胶层，耐热胶层在钝化层的通孔处不留任何图形，以形成与第一电极层连通的第二开孔。
(2)将显示基板与柔性背板贴合。将显示基板与柔性背板贴合包括：将显示基板2的基板衬底与柔性背板1上的耐热胶层6贴合，并使柔性背板1上的第二开孔与显示基板2上的贯穿孔2023对应，然后利用柔性背板1第二开孔内的第一电极层为种子层，采用化学镀工艺或者直接点银胶方法，填充显示基板2的贯穿孔2023，在贯穿孔内形成金属导电层105，并通过金属导电层105将显示基板2的连接电极与柔性背板1的第一电极层电连接，如图6所示。
第三实施例
基于前述实施例的技术构思，本发明还提供了一种显示装置，包括前述实施例的显示结构。
在本发明实施例的描述中，需要理解的是，术语“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明实施例的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
虽然本发明所揭露的实施方式如上，但所述的内容仅为便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

1.一种显示结构，其特征在于，包括叠加设置的柔性背板以及显示基板，所述柔性背板包括用于与集成电路芯片绑定的绑定电极，所述柔性背板弯曲以形成弯曲部，所述绑定电极位于所述弯曲部上；其中，所述显示基板包括基板衬底以及形成于所述基板衬底之上的驱动电路层，所述驱动电路层包括连接电极以及将所述连接电极与所述柔性背板连通的贯穿孔；所述柔性背板还包括柔性衬底、形成于所述柔性衬底之上的隔垫柱、以及形成于所述柔性衬底和所述隔垫柱之上的第一电极层，所述隔垫柱插接于所述贯穿孔内，使所述隔垫柱上的第一电极层与所述连接电极电连接。
2.根据权利要求1所述的显示结构，其特征在于，所述绑定电极连接有集成电路芯片。
3.根据权利要求2所述的显示结构，其特征在于，所述显示基板覆盖所述集成电路芯片。
4.根据权利要求1所述的显示结构，其特征在于，所述贯穿孔分别将所述驱动电路层和所述基板衬底贯穿。
5.根据权利要求1所述的显示结构，其特征在于，所述贯穿孔内设有导电胶层，所述导电胶层将所述第一电极层与所述连接电极电连接。
6.根据权利要求1所述的显示结构，其特征在于，所述柔性背板还包括形成于除所述隔垫柱以外的第一电极层之上的钝化层，所述钝化层上开设有与所述第一电极层连通的开孔，所述绑定电极形成于所述钝化层之上，并贯穿所述开孔与所述第一电极层电连接。
7.根据权利要求1所述的显示结构，其特征在于，所述柔性背板还包括柔性衬底以及形成于所述柔性衬底之上的第一电极层，所述第一电极层之上形成有金属导电层，所述金属导电层贯穿所述贯穿孔，与所述连接电极电连接。
8.根据权利要求1所述的显示结构，其特征在于，所述柔性背板之上设有耐热胶层，所述耐热胶层位于所述柔性背板与所述显示基板之间。
9.一种显示装置，其特征在于，包括权利要求1-8任一所述的显示结构。
10.一种显示结构的制备方法，其特征在于，包括：
将显示基板与柔性背板贴合；所述显示基板包括基板衬底以及形成于所述基板衬底之上的驱动电路层，所述驱动电路层包括连接电极以及将所述连接电极与所述柔性背板连通的贯穿孔；所述柔性背板包括柔性衬底、形成于所述柔性衬底之上的隔垫柱、以及形成于所述柔性衬底和所述隔垫柱之上的第一电极层，所述隔垫柱插接于所述贯穿孔内，使所述隔垫柱上的第一电极层与所述连接电极电连接；所述柔性背板还包括用于与集成电路芯片绑定的绑定电极；
将所述柔性背板弯曲以形成弯曲部，并使所述柔性背板上的绑定电极位于所述弯曲部上。
CN201910734585.2A 2019-08-09 2019-08-09 显示结构及其制备方法、显示装置 Active CN110391200B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201910734585.2A CN110391200B (zh) 2019-08-09 2019-08-09 显示结构及其制备方法、显示装置
US16/920,771 US11424232B2 (en) 2019-08-09 2020-07-06 Display structure and preparation method thereof, and display apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910734585.2A CN110391200B (zh) 2019-08-09 2019-08-09 显示结构及其制备方法、显示装置

Publications (2)

Publication Number Publication Date
CN110391200A CN110391200A (zh) 2019-10-29
CN110391200B true CN110391200B (zh) 2021-10-01

Family

ID=68288698

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910734585.2A Active CN110391200B (zh) 2019-08-09 2019-08-09 显示结构及其制备方法、显示装置

Country Status (2)

Country Link
US (1) US11424232B2 (zh)
CN (1) CN110391200B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113488513B (zh) * 2021-06-23 2022-05-03 武汉华星光电半导体显示技术有限公司 显示模组及其制备方法
TWI791385B (zh) * 2022-02-10 2023-02-01 友達光電股份有限公司 顯示面板、包含其之拼接顯示裝置及其製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104851892A (zh) * 2015-05-12 2015-08-19 深圳市华星光电技术有限公司 窄边框柔性显示装置及其制作方法
CN105009188A (zh) * 2013-02-01 2015-10-28 乐金显示有限公司 具有柔性显示器的电子装置及其制造方法
CN110034088A (zh) * 2017-12-08 2019-07-19 乐金显示有限公司 用于驱动显示装置的膜元件和使用该膜元件的显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6305759B2 (ja) * 2013-12-26 2018-04-04 株式会社ジャパンディスプレイ 表示装置
CN106973520A (zh) * 2017-05-27 2017-07-21 京东方科技集团股份有限公司 一种显示面板、显示装置及显示面板的制作方法
JP7246136B2 (ja) * 2018-02-14 2023-03-27 キヤノン株式会社 半導体装置、カメラおよび半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105009188A (zh) * 2013-02-01 2015-10-28 乐金显示有限公司 具有柔性显示器的电子装置及其制造方法
CN104851892A (zh) * 2015-05-12 2015-08-19 深圳市华星光电技术有限公司 窄边框柔性显示装置及其制作方法
CN110034088A (zh) * 2017-12-08 2019-07-19 乐金显示有限公司 用于驱动显示装置的膜元件和使用该膜元件的显示装置

Also Published As

Publication number Publication date
US11424232B2 (en) 2022-08-23
CN110391200A (zh) 2019-10-29
US20210043619A1 (en) 2021-02-11

Similar Documents

Publication Publication Date Title
WO2020259337A1 (zh) 阵列基板及其制备方法、显示面板和显示装置
CN113301710B (zh) 显示装置及其制备方法
CN110310577B (zh) 显示面板及其制备方法
CN104421771B (zh) 发光二极管组件以及包括该组件的液晶显示装置
US20220320056A1 (en) Light-emitting substrate, method of manufacturing light-emitting substrate, and display device
CN101340777A (zh) 柔性印刷电路板和使用其的液晶显示装置及其制造方法
TW200812054A (en) Light source apparatus and liquid crystal display having the same
CN108089361B (zh) 显示装置及用于制造该显示装置的方法
WO2021223302A1 (zh) 显示面板及其制备方法
CN107464503B (zh) 显示基板及其制备方法和显示装置
CN113257121A (zh) 一种显示装置及其制作方法和拼接显示装置
CN110391200B (zh) 显示结构及其制备方法、显示装置
CN111627953B (zh) 一种显示面板及其制备方法、显示装置
CN110853572A (zh) 显示面板和显示装置
CN112366214A (zh) 一种led无缝拼接显示面板及其实现方法
CN113257143A (zh) 一种显示面板、显示装置和显示面板的制造方法
WO2021087726A1 (zh) 一种阵列基板及其制作方法、显示装置
CN111243495A (zh) 显示面板及显示装置
CN113257173A (zh) 一种主动发光器件、显示面板以及拼接显示装置
TWM268600U (en) Structure of chip on glass and liquid crystal display device using the structure
TW594274B (en) Display module
CN111029360B (zh) micro-LED显示器件的制作方法
WO2023020476A1 (zh) 一种透明led显示屏
CN113380777B (zh) 异质集成透明MicroLED显示装置及其制作方法
CN111430402B (zh) 发光组件及其制备方法、显示基板、背光模组、显示装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant