CN110390119A - 感测放大器的布局图 - Google Patents

感测放大器的布局图 Download PDF

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CN110390119A
CN110390119A CN201810361216.9A CN201810361216A CN110390119A CN 110390119 A CN110390119 A CN 110390119A CN 201810361216 A CN201810361216 A CN 201810361216A CN 110390119 A CN110390119 A CN 110390119A
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CN110390119B (zh
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永井享浩
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种感测放大器的布局图，其包含一等化器和预充电器区，在等化器和预充电器区内设置有一等化器晶体管和一预充电器晶体管以及一栅极线。栅极线和预充电器晶体管共用一共用插塞分别作为栅极线的栅极插塞以及预充电器晶体管的源极/漏极插塞。

Description

感测放大器的布局图
技术领域
本发明涉及一种感测放大器的布局图，特别是涉及一种具有共用插塞的感测放大器的布局图。
背景技术
随着目前科技的高速发展，存储器广泛用于电子装置中，例如电脑、服务器、诸如移动电话等的手持式装置、印表机和许多的电子装置及应用。存储器由多个存储单元、预充电电路、写入电路、行与列解码器与感测放大器等电路所构成。在存储器中，感测放大器用于通过差分信号来感测数据输送以用于写入到存储器或者从存储器读出。然而随着半导体元件的集成度增加，感测放大器中的金属线路的密度也随之上升，较大的金属线路的密度会造成感测放大器在制作工艺上的困难。
发明内容
有鉴于此，本发明提供了一种感测放大器的布局图，其具有改良后的金属线路密度。
根据本发明的一优选实施例，一种感测放大器的布局图，包含一基底包含一等化器和预充电器区，一第一方向和一第二方向互相垂直。等化器和预充电器区包含一主动区域设置于基底中，主动区域包含一第一长条区向第二方向延伸，一第二长条区和一第三长条区由第一长条区向第一方向延伸，并且第二长条区和第三长条区互相平行，第一长条区和第二长条区垂直。一绝缘元件设置于基底中，并且围绕主动区域。一等化器栅极线和一预充电器栅极线设置于基底上并且和第一长条区平行，等化器栅极线和预充电器栅极线覆盖第二长条区、绝缘元件和第三长条区。一栅极线设置于基底上并且和第一长条区平行，栅极线覆盖第一长条区和绝缘元件，预充电器栅极线位于等化器栅极线和栅极线之间。二源极/漏极插塞设置于第二长条区内并且分别位于等化器栅极线的两侧以及一共用插塞接触第一长条区以及栅极线。
本发明利用共用插塞节省了金属导电线的总数量，使得金属导电线的密度下降，因此图案化金属导电线的困难度也降低。
附图说明
图1为本发明的第一优选实施例所绘示的感测放大器的示意布局图；
图2为图1中的感测放大器的等效电路图；
图3为图1中的等化器和预充电器区的局部放大图；
图4为图3中沿AA’切线方向的侧视图；
图5为图3中沿BB’切线方向的侧视图；
图6为本发明的另一优选实施例所绘示的图3中沿AA’切线方向的侧视图；
图7为本发明的优选实施例所绘示的图3的布局图叠加上金属导电线的示意图；
图8为图7中沿着切线CC’方向和切线DD’方向所绘示的侧视图；
图9为本发明的第二优选实施例所绘示的感测放大器的布局示意图；
图10为图9中的等化器和预充电器区叠加上金属导电线的局部布局示意图。
主要元件符号说明
10 基底 12 开关区
12a 开关区 14 第一晶体管区
16 等化器和预充电器区 18 第二晶体管区
20 P型晶体管 22 P型晶体管
24 N型晶体管 26 N型晶体管
28 开关晶体管 28a 开关晶体管
30 等化器晶体管 32 预充电器晶体管
34 感测放大器 36 存储节点
38 存储节点 40 动态随机处理存储器
42 主动区域 44 第一长条区
46 第二长条区 48 第三长条区
50 绝缘元件 52 等化器栅极线
54 预充电器栅极线 56 栅极线
58 源极/漏极插塞 60 源极/漏极插塞
62 源极/漏极插塞 64 源极/漏极插塞
66 共用插塞 68 层间介电层
70 金属导电线 72 共用栅极线
74 源极/漏极插塞 76 源极/漏极插塞
78 源极/漏极插塞 80 预充电器晶体管
82 预充电器晶体管 84 等化器晶体管
86 栅极线插塞 100 感测放大器的布局图
116 等化器和预充电器区 156 第一上表面
200 感测放大器的布局图 256 第二上表面
BL1 位线 BL2 位线
CL 导线 D 距离
L1 长边 L2 长边
L3 长边 L4 长边
M 基准线 S1 间距
S2 间距 Vcc 电压源
Vss 电压源 W1 宽边
W2 宽边 W3 宽边
W4 宽边 X 第一方向
Y 第二方向
具体实施方式
图1为根据本发明的第一优选实施例所绘示的感测放大器的布局图。如图1所示，一感测放大器的布局图100包含有一基底10，基底10可以为一硅基底、一锗基底、一砷化镓基底、一硅锗基底、一磷化铟基底、一氮化镓基底或一碳化硅基底。基底10上划分有一开关区12、一第一晶体管区14、一等化器和预充电器区16和一第二晶体管区18。等化器和预充电器区16的两侧分别是第一晶体管区14和第二晶体管区18，第一晶体管区14较佳为一P型晶体管区，第二晶体管区18较佳为一N型晶体管区。开关区12是位于第一晶体管区14的一侧。在第一晶体管区14中设置至少二个晶体管，例如一P型晶体管20和一P型晶体管22；在第二晶体管18区中设置至少二个晶体管，例如一N型晶体管24和一N型晶体管26。
在开关区12内设置有至少一开关晶体管28，开关晶体管28较佳为N型晶体管，在等化器和预充电器区16内设置有一等化器晶体管30和一预充电器晶体管32。上述的开关区12、第一晶体管区14、等化器和预充电器区16和第二晶体管区18会以基底10上一基准线M为准在基底10的另一区呈镜像复制。在开关区12、第一晶体管区14、等化器和预充电器区16、第二晶体管区18中的晶体管以及镜像复制的开关区12a中的开关晶体管28a会共同组成一感测放大器。此外，本发明的感测放大器适合作为动态随机处理存储器的感测放大器。
图2绘示的是图1中的感测放大器的等效电路图。请同时参阅图1和图2，感测放大器34是由P型晶体管20、P型晶体管22、N型晶体管24和N型晶体管26构成栓锁电路(latch)，使数据可以栓锁在存储节点(Storage Node)36或38。P型晶体管22和N型晶体管24一同构成一反相器(inverter)，且这两者所构成的串接电路两端点分别耦接于一电压源Vcc与一电压源Vss；同样地，P型晶体管20和N型晶体管26构成另一反相器，而这两者所构成的串接电路两端点还分别耦接于电压源Vcc与电压源Vss。上述两反相器互相耦合以存储数据。
此外，在存储节点36处电连接有开关晶体管28a的源极；同样地，在存储节点38电连接有开关晶体管28的源极。至于开关晶体管28和开关晶体管28a的栅极则分别耦接至字符线WL1，而开关晶体管28和开关晶体管28a的漏极则分别耦接至相对应的位线BL1与BL2。
此外，等化器晶体管30的栅极和预充电器晶体管32的栅极分别耦接一导线CL。等化器晶体管的30源极和漏极分别耦接位线BL1与BL2，预充电器晶体管32的源极和漏极也分别耦接位线BL1与BL2。另外，一动态随机处理存储器40中的晶体管的源极电连接位线BL2，动态随机处理存储器40中的晶体管的栅极电连接一字符线WL2。
图3绘示的是图1中的等化器和预充电器区的局部放大图。如图1和图3所示，等化器和预充电器区16布局放大图，包含前述基底10，基底10上设置有等化器和预充电器区16，一第一方向X和一第二方向Y互相垂直。等化器和预充电器区16内包含一主动区域42设置于基底10上，主动区域42包含一第一长条区44、一第二长条区46和一第三长条区48。第一长条区44向第二方向Y延伸，第二长条区46和第三长条区48由第一长条区44向第一方向X延伸，并且第二长条区46和第三长条区48互相平行，第一长条区44和第二长条区46垂直。前述延伸的意思是指第一长条区44具有一长边L1和一宽边W1，长边L1大于宽边W1，长边L1和第二方向Y平行。而第二长条区46和第三长条区48也各自具有一长边L2和一长边L3，以及一宽边W2和一宽边W3，长边L2大于宽边W2，长边L3大于宽边W3，第二长条区46的长边L2和第三长条区48的长边L3是和第一方向X平行。
一绝缘元件50设置于基底10中，并且围绕主动区域42。主动区域42可以利用在基底10中蚀刻出多条沟槽，然后在沟槽中填入绝缘材料后形成绝缘元件，以定义出主动区域42，也就是说主动区域42的材料和基底10相同，绝缘元件50可以为浅沟槽隔离，其制作材料可以包含氧化硅。
此外，一等化器栅极线52和一预充电器栅极线54设置于基底10上并且和第一长条区44平行，等化器栅极线52和预充电器栅极线54可以各自包含一导电栅极和一栅极介电层。等化器栅极线52和预充电器栅极线54都覆盖第二长条区46、绝缘元件50和第三长条区48。一栅极线56设置于基底10上并且和第一长条区44平行，栅极线56包含一导电栅极和一栅极介电层。栅极线56覆盖第一长条区44和绝缘元件50。预充电器栅极线54位于等化器栅极线52和栅极线56之间，二个源极/漏极插塞58/60设置于第二长条区46内并且分别位于等化器栅极线52的两侧，另外二个源极/漏极插塞62/64设置于第三长条区48内并且分别位于于等化器栅极线的两侧52。一共用插塞66接触第一长条区44以及栅极线56。
预充电器栅极线54和位于等化器栅极线52和预充电器栅极线54之间的源极/漏极插塞60、共用插塞66以及主动区域42一起组成前述的预充电晶体管32。等化器栅极线52、位于等化器栅极线52的二侧且在第二长条区46的源极/漏极插塞58/60以及主动区域42共同组成前述的等化器晶体管30。值得注意的是由于共用插塞66同时接触主动区域42的第一长条区44和栅极线56，因此共用插塞66可以同时作为预充电晶体管32的源极/漏极插塞以及栅极线56的栅极插塞。栅极线56是为感测放大器在预充电待机状态时提供位线预充电电压(voltage of bit line pre-charge,VBLP)的导电线，如图2所示位线预充电电压施加于预充电器晶体管上。
图4为图3中沿AA’切线方向的侧视图。请同时参阅图3和图4，栅极线56具有一长边L4和一宽边W4，长边L4大于宽边W4，栅极线56的宽边W4同时覆盖绝缘元件50和第一长条区44。此外，共用插塞66同时接触第一长条区44以及栅极线56，一层间介电层68覆盖栅极线56。图5为图3中沿BB’切线方向的侧视图。请同时参阅图3和图5，层间介电层68覆盖等化器栅极线52和预充电器栅极线54。
图6为根据本发明的另一优选实施例所绘示的图3中沿AA’切线方向的侧视图。图6和图4的不同之处在于：图6的栅极线56的上表面形成一阶梯轮廓，详细来说，栅极线的上表面包含了一第一上表面156和一第二上表面256，由第一上表面156和第二上表面256构成阶梯轮廓，第一上表面156接触层间介电层68，第二上表面258接触共用插塞66并且和第一上表面156平行，第一上表面156和第二上表面256不切齐。因此，相较于图4中的共用插塞66，图6中的共用插塞66和栅极线56的接触面积增大，如此可使共用插塞66的电阻值下降。
图7为根据本发明的优选实施例所绘示的图3的布局图叠加上金属导电线。图8为图7中沿着切线CC’方向和切线DD’方向所绘示的侧视图。请同时参阅图7和图8，多条金属导电线70设置在等化器和预充电器区16，各条金属导电线70向都第一方向延伸，横跨主动区域42中的第一长条区44、第二长条区46和第三长条区48以及绝缘元件50。如前文所述，层间介电层68覆盖等化器栅极线52、预充电器栅极线54和栅极线56，源极/漏极插塞58/60/62/64和共用插塞66都穿透此层间介电层68，值得注意的是：共用插塞66不接触任何在层间介电层68上并且接触层间介电层68的金属导电线70。也就是说共用插塞66不藉由金属导电线70跟任何穿透层间介电层68的插塞电连接，源极/漏极插塞58/60/62/64都有金属导电线70通过，以和其它区域的插塞电连接。由于共用插塞66上没有金属导电线70通过，相较于源极/漏极插塞58/60/62/64上有金属导电线70，共用插塞66的位置节省了一条金属导电线70的空间，所以在共用插塞70两侧的金属导电线之间的间距S1会大于在源极/漏极插塞58/60/62/64上的金属导电线70和其相邻金属导电线70之间的间距S2。也就是说节省了一条金属导电线70的空间之后共用插塞66两侧的区域的金属导电线70密度降低，因此制作工艺难度也减低。此外，共用插塞66的上表面离相邻的金属导电线70有一距离D，并且与共用插塞相邻的金属导电线70的间距S2比源极/漏极插塞58/60/62/64上的金属导电线70的间距S1大，因此较不会产生寄生电容的现象。
图9为根据本发明的第二优选实施例所绘示的感测放大器的布局图，其中具有相同功能和位置的元件将给予第一优选实施例中的标号。图10为图9中的等化器和预充电器区叠加上金属导电线的局部布局图。
如图9所示，一感测放大器的布局图200包含有一基底10，基底上划分有一开关区12、一第一晶体管区14、一等化器和预充电器区116和一第二晶体管区18。值得注意的是：第一优选实施例和第二优选实施例中的等化器和预充电器区116的布局图案不同，第二优选实施例其它区域的布局图案都和第一优选实施例相同。第二优选实施例中预充电器晶体管和等化器晶体管的栅极线为共用、主动区域呈多个「工」字形并且等化器和预充电器区内没有共用插塞；而第一较佳实中的预充电器晶体管和等化器晶体管的栅极线不相连，主动区域呈梳子的形状并且有共用插塞。如图10所示，在第二优选实施例中，源极/漏极插塞74/76以及共用栅极线72组成一预充电器晶体管80，源极/漏极插塞76/78以及共用栅极线72组成另一预充电器晶体管82，源极/漏极插塞74/78以及共用栅极线组成一等化器晶体管84。
如此不同的布局图也造成后续叠加上金属导电线70后，金属导电线的密度和第一优选实施例中的不同，在第二优选实施例中，源极/漏极插塞74/76/78上都有金属导电线70通过，栅极线56上具有一栅极线插塞86，栅极线插塞86利用金属导电线70和预充电器晶体管80/82的源极/漏极插塞76电连接，所以第二优选实施例中没有共同插塞，并且比第一优选实施例有较多的金属导电线70，所以第二优选实施例中的栅极线插塞86上的金属导电线70与其相邻的金属导电线70之间的密度会大于第一优选实施例中，在共用插塞66两侧的金属导电线70的密度，如此在图案化第二优选实施例中的金属导电线70的制作工艺难度会提高。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (6)

1.一种感测放大器的布局图，其特征在于，包含：
基底，包含一等化器和预充电器区，一第一方向和一第二方向互相垂直，其中该等化器和预充电器区包含：
主动区域，设置于该基底中，该主动区域包含第一长条区向该第二方向延伸，第二长条区和第三长条区由该第一长条区向该第一方向延伸，并且该第二长条区和该第三长条区互相平行，该第一长条区和该第二长条区垂直；
绝缘元件，设置于该基底中，并且围绕该主动区域；
等化器栅极线和预充电器栅极线，设置于该基底上并且和该第一长条区平行，该等化器栅极线和该预充电器栅极线覆盖该第二长条区、该绝缘元件和该第三长条区；
栅极线，设置于该基底上并且和该第一长条区平行，该栅极线覆盖该第一长条区和该绝缘元件，该预充电器栅极线位于该等化器栅极线和该栅极线之间；
两个源极/漏极插塞，设置于该第二长条区内并且分别位于该等化器栅极线的两侧；以及
共用插塞，接触该第一长条区以及该栅极线。
2.如权利要求1所述的感测放大器的布局图，另包含：该两个源极/漏极插塞设置于该第三长条区内并且分别位于等化器栅极线的两侧。
3.如权利要求1所述的感测放大器的布局图，另包含：
层间介电层，覆盖该等化器栅极线、该预充电器栅极线和该栅极线，并且该两个源极/漏极插塞和该共用插塞都穿透该层间介电层；以及
多条金属导电线，设置该层间介电层上、接触该层间介电层和该两个源极/漏极插塞，并且该多条金属导电线向该第一方向延伸、横跨该主动区域；其中该共用插塞不接触任何位于该层间介电层上并且接触该层间介电层的该多条金属导电线。
4.如权利要求3所述的感测放大器的布局图，还包含：
N型晶体管区，包含二N型晶体管设置其中；
P型晶体管区，设置于该基底上并且位于该等化器和预充电器区的另一侧，该P型晶体管区包含二P型晶体管设置其中；以及
开关区，设置于该P型晶体管区的一侧，其中该开关区包含：
开关晶体管。
5.如权利要求3所述的感测放大器的布局图，其中该栅极线的上表面形成一阶梯轮廓。
6.如权利要求1所述的感测放大器的布局图，其中部分的该等化器栅极线、该两个源极/漏极插塞和部分的该主动区域共同构成一等化器晶体管，部分的该预充电器栅极线、位于该等化器栅极线和该预充电器栅极线之间的该源极/漏极插塞、该共用插塞和部分的该主动区域共同组成一预充电晶体管。
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