US20190325943A1 - Layout of sense amplifier - Google Patents
Layout of sense amplifier Download PDFInfo
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- US20190325943A1 US20190325943A1 US15/975,790 US201815975790A US2019325943A1 US 20190325943 A1 US20190325943 A1 US 20190325943A1 US 201815975790 A US201815975790 A US 201815975790A US 2019325943 A1 US2019325943 A1 US 2019325943A1
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L27/10897—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Definitions
- the present invention relates to layout of a sense amplifier, and more particularly to layout of a sense amplifier which has a share plug.
- Sense amplifiers are used in memory devices to allow for reduced voltage swing on bit lines.
- DRAM dynamic random access memory
- each data bit is stored in a small storage capacitor that is discharged quickly.
- a sense amplifier detects a signal representing the bit on a bit line and amplifies the signal to an amplitude close to the DRAM circuit's supply voltage.
- the capacitor is recharged as the signal is amplified.
- the data bit is refreshed before it ceases to be detectable, as the sense amplifier detects and amplifies the signal on a periodic basis, such as every few milliseconds.
- a layout of a sense amplifier includes a substrate comprising a pre-charge and equalizer area.
- a first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other.
- the pre-charge and equalizer area includes an active area disposed in the substrate, wherein the active area includes a first area extending toward the second direction, a second area and a third area extending from the first area toward the first direction.
- the second area and the third area are parallel to each other, and the first area is perpendicular to the second area.
- An insulating element is disposed in the substrate and surrounds the active area.
- An equalizer gate line and a pre-charge gate line are disposed on the substrate, wherein the equalizer gate line and the pre-charge gate line are parallel to the first area, and the equalizer gate line and the pre-charge gate line cover the second area, the insulating element and the third area.
- a gate line is disposed on the substrate and parallel to the first area. The gate line covers the first area and the insulating element, wherein the pre-charge gate line is disposed between the equalizer gate line and the gate line.
- Two source/drain plugs are disposed in the second area and respectively at two sides of the equalizer gate line. A share plug directly contacts the first area and the gate line.
- the present invention uses a share plug to decrease the number of metal lines, thereby reducing their density. In this way, it becomes easier to pattern the metal lines.
- FIG. 1 depicts a layout of a sense amplifier according to a first preferred embodiment of the present invention.
- FIG. 2 depicts an equivalent circuit diagram of the sense amplifier shown in FIG. 1 .
- FIG. 3 depicts magnified view of a portion of a pre-charge and equalizer area shown in FIG. 1 .
- FIG. 4 shows a sectional view taken along line AA′ in FIG. 3 .
- FIG. 5 shows a sectional view taken along line BB′ in FIG. 3 .
- FIG. 6 shows a sectional view taken along line AA′ in FIG. 3 according to another preferred embodiment of the present invention.
- FIG. 7 depicts the layout shown in FIG. 3 stacked with metal lines.
- FIG. 8 are sectional view taken along line CC′ and line DD′ in FIG. 7 .
- FIG. 9 shows a layout of a sense amplifier according to a second preferred embodiment of the present invention.
- FIG. 10 depicts a magnified view of a portion of a pre-charge and equalizer area shown in FIG. 9 stacked with metal lines.
- FIG. 1 depicts a layout of a sense amplifier according to a first preferred embodiment of the present invention.
- a layout of a sense amplifier 100 includes a substrate 10 .
- the substrate 10 may be a bulk silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, or a silicon carbide substrate.
- the substrate 10 is divided into a switch area 12 , a first transistor area 14 , a pre-charge and equalizer area 16 and a second transistor area 18 .
- the first transistor area 14 and the second transistor area 18 are respectively at two sides of the pre-charge and equalizer area 16 .
- the first transistor area 14 is preferably a P-type transistor area
- the second transistor area 18 is preferably an N-type transistor area.
- the switch area 12 is disposed at one side of the first transistor area 14 .
- At least two transistors, such as P-type transistors 20 / 22 are disposed within the first transistor area 14 .
- At least two transistors, such as N-type transistors 24 / 26 are disposed within the second transistor area 18 .
- a switch transistor 28 is disposed in the switch area 12 .
- the switch transistor 28 is preferably an N-type transistor.
- An equalizer transistor 30 and pre-charge transistor 32 are disposed within the pre-charge and equalizer area 16 .
- the switch area 12 , the first transistor area 14 , the pre-charge and equalizer area 16 and the second transistor area 18 are arranged symmetrically about the center line M.
- the sense amplifier of the present invention is suitable for being applied in a DRAM (dynamic random access memory).
- FIG. 2 depicts an equivalent circuit diagram of the sense amplifier in FIG. 1 of the present invention. Please refer to FIG. 1 and FIG. 2 together.
- the P-type transistor 20 , the P-type transistor 22 , the N-type transistor 24 , and the N-type transistor 26 constitute a latch circuit that stores data in the storage nodes 36 or 38 .
- the P-type transistor 22 and the N-type transistor 24 form an inverter, and respectively electrically connect to a voltage source Vcc and a voltage source Vss.
- the P-type transistor 20 and the N-type transistor 26 form another inverter, and respectively electrically connect to the voltage source Vcc and the voltage source Vss.
- the aforesaid inverters couple to each other to store data.
- the storage node 36 electrically connects to a source of the switch transistor 28 a
- the storage node 38 electrically connects to a source of the switch transistor 28 .
- the gates of the switch transistor 28 a and the switch transistor 28 are respectively coupled to a word line WL 1 ; the drain of the switch transistor 28 a and the switch transistor 28 are respectively coupled to a bit line BL 1 and a bit line BL 2 .
- the gates of the equalizer transistor 30 , and pre-charge transistor 32 respectively couple to a conductive line CL.
- a source and a drain of the equalizer transistor 30 respectively couple to the bit line BL 1 and bit line BL 2 .
- a source and a drain of the pre-charge transistor 32 respectively couple to the bit line BL 1 and bit line BL 2 .
- a drain of a transistor in the DRAM 40 electrically connects to the bit line BL 2 .
- a gate of the transistor in the DRAM 40 electrically connects to a word line WL 2 .
- FIG. 3 depicts a magnified view of a portion of the pre-charge and equalizer area shown in FIG. 1 .
- the pre-charge and equalizer area 16 includes the substrate 10 .
- a pre-charge and equalizer area 16 is disposed on the substrate 10 .
- a first direction X and a second direction Y are perpendicular to each other.
- An active area 42 is disposed on the substrate 10 .
- the active area 42 includes a first area 44 , a second area 46 and a third area 48 .
- the first area 44 extends toward the second direction Y, and the second area 46 and the third area 48 extend from the first area 44 toward the first direction X.
- the second area 46 and the third area 48 are parallel to each other, and the first area 44 is perpendicular to the second area 46 .
- the aforesaid term “extend” means that the first area 44 has a long side L 1 and a wide side W 1 , wherein the long side L 1 is greater than the wide side W 1 .
- the long side L 1 is parallel to the second direction Y.
- the second area 46 has a long side L 2 and a wide side L 2
- the third area 48 has a long side L 3 and a wide side W 3 .
- the long side L 2 is greater than the wide side W 2
- the long side L 3 is greater than the wide side W 3 .
- the long side L 2 and the long side L 3 are parallel to the first direction X.
- An insulating element 50 is disposed in the substrate 10 and surrounds the active area 42 .
- the active area 42 may be formed by etching the substrate 10 to form numerous trenches, which are then filled with an insulating material to form the insulating element 50 .
- the insulating element 50 defines the active area 42 on the substrate 10 , i.e. the material of the active area 42 and the substrate 10 is the same.
- the insulating element 50 can be a shallow trench isolation formed by silicon oxide.
- An equalizer gate line 52 and a pre-charge gate line 54 are disposed on the substrate 10 .
- the equalizer gate line 52 and the pre-charge gate line 54 are parallel to the first area 44 .
- the equalizer gate line 52 and the pre-charge gate line 54 respectively include a conductive gate and a gate dielectric layer.
- the equalizer gate line 52 and the pre-charge gate line 54 cover the second area 46 , the insulating element 50 and the third area 48 .
- a conductive line 56 is disposed on the substrate 10 and parallel to the first area 44 .
- the conductive line 56 includes a conductive gate and a gate dielectric layer.
- the conductive line 56 covers the first striped are 44 and the insulating element 50 .
- the pre-charge gate line 54 is disposed between the equalizer gate line 52 and the gate line 56 .
- Two source/drain plugs 58 / 60 are disposed in the second area 46 and respectively at two sides of the equalizer gate line 52 .
- Another two source/drain plugs 62 / 64 are disposed within the third area 48 and at two sides of the equalizer gate line 52 .
- a share plug 66 directly contacts the first area 44 and the gate line 56 .
- the pre-charge gate line 54 , the source/drain plug 60 between the equalizer gate line 52 and the pre-charge gate line 54 , the share plug 66 , and part of the active area 42 form a pre-charge transistor 32 .
- the equalizer gate line 52 , the two source/drain plugs 58 / 60 , and part of the active area 42 form an equalizer transistor 30 .
- the share plug 66 directly contacts the first area 44 of the active area 44 and the gate line 56 , the share plug 66 serving as a source/drain plug of the pre-charge transistor 32 and a gate plug of the gate line 56 simultaneously.
- the gate line 56 is a conductive line providing the sense amplifier 34 with a voltage of bit line pre-charge (VBLP) during a pre-charge stage. As shown in FIG. 2 , the VBLP is applied to the pre-charge transistor 32 .
- VBLP bit line pre-charge
- FIG. 4 shows a sectional view taken along line AA′ in FIG. 3 .
- the gate line 56 has a long side L 4 and a wide side W 4 .
- the long side L 4 is greater than the wide side W 4 .
- the wide side W 4 of the gate line 56 covers both the insulating element 50 and the first area 44 .
- the share plug 66 directly contacts both the first area 44 and the gate line 56 .
- An interlayer dielectric layer 68 covers the gate line 56 .
- FIG. 5 shows a sectional view taken along line BB′ in FIG. 3 . Please refer to FIG. 3 and FIG. 5 together.
- the interlayer dielectric layer 68 covers the equalizer gate line 52 and the pre-charge gate line 54 .
- FIG. 6 shows a sectional view taken along line AA′ in FIG. 3 according to another preferred embodiment of the present invention.
- the top surface of the gate line 56 in FIG. 6 forms a step profile.
- the top surface of the gate line 56 includes a first top surface 156 and a second top surface 256 .
- the first top surface 156 and the second top surface 256 form the step profile.
- the first top surface 156 directly contacts the interlayer dielectric layer 68 .
- the second top surface 256 directly contacts the share plug 66 and is parallel to the first top surface 156 .
- the first top surface 156 and the second top surface 256 are not coplanar. Therefore, the contact area between the share plug 66 and the gate line 56 in FIG. 6 is greater than in FIG. 4 . In this way, the resistance of the share plug 66 can be reduced.
- FIG. 7 depicts the layout in FIG. 3 stacked with metal lines.
- FIG. 8 is a sectional view taken along line CC′ and line DD′ in FIG. 7 . Please refer to FIG. 7 and FIG. 8 together.
- Numerous metal lines 70 are disposed in the pre-charge and equalizer area 16 .
- Each metal line 70 extends toward the first direction X, and crosses the first area 44 , the second area 46 , and the third area of the active area 42 , and crosses the insulating element 50 .
- the interlayer dielectric layer 68 covers the equalizer gate line 52 , the pre-charge gate line 54 , and the gate line 56 .
- the source/drain plugs 58 / 60 / 62 / 64 and the share plug 66 penetrate the interlayer dielectric layer 68 .
- the share plug 66 does not contact any metal line 70 disposed on and contacting the interlayer dielectric layer 68 .
- the share plug 66 does not electrically connect through the metal lines 70 to any plug which penetrates the interlayer dielectric layer 68 .
- the metal lines 70 pass the source/drain plugs 58 / 60 / 62 / 64 to electrically connect to contact plugs in other regions. Because no metal line 70 passes the share plug 66 , the space above the share plug 66 is not occupied by the metal lines 70 .
- metal lines 70 pass the source/drain plugs 58 / 60 / 62 / 64 , meaning the space above the source/drain plugs 58 / 60 / 62 / 64 is occupied by the metal lines 70 . Therefore, the space S 1 between two metal lines 70 at two sides of the share plug 70 is greater than the space S 2 between the metal line 70 directly above the source/drain plug 58 and the metal line 70 adjacent to the metal line 70 directly above the source/drain plug 58 . The space S 2 is also between the metal line 70 directly above the source/drain plugs 60 / 62 / 64 and the metal line 70 adjacent to the metal line 70 directly above the source/drain plugs 60 / 62 / 64 .
- a distance D is between the top surface of the share plug 66 and the metal line 70 adjacent to the share plug 66 , wherein the space S 1 is greater than the space S 2 . Therefore, the parasitic capacitance around the share plug 66 is reduced.
- FIG. 9 shows a layout of a sense amplifier according to a second preferred embodiment of the present invention, wherein elements which are substantially the same as those in the first preferred embodiment are denoted by the same reference numerals; an accompanying explanation is therefore omitted.
- FIG. 10 depicts a magnified view of a portion of the pre-charge and equalizer area in FIG. 9 stacked with metal lines.
- a layout of a sense amplifier 200 includes a substrate 10 .
- the substrate 10 is divided into a switch area 12 , a first transistor area 14 , a pre-charge and equalizer area 116 and a second transistor area 18 .
- the layout of the pre-charge and equalizer area 116 in the second preferred embodiment is different from the layout of the pre-charge and equalizer area 16 in the first preferred embodiment.
- Other areas in the second preferred embodiment are the same as in the first preferred embodiment.
- pre-charge transistors 80 / 82 and an equalizer transistor 84 share one common gate line 72 , the active area is constituted by numerous “I”-shaped patterns, and there is no share plug in the pre-charge and equalizer area 116 .
- the gate line of the pre-charge transistor 32 , and the gate line of the equalizer transistor 30 do not connect to each other, the active area 42 is comb-shaped, and there is a share plug 66 .
- the source/drain plugs 74 / 76 and the common gate line 72 constitute the pre-charge transistor 80 .
- the source/drain plugs 76 / 78 and the common gate line 72 constitute another pre-charge transistor 82 .
- the source/drain plugs 74 / 78 and the common gate line 72 constitute the equalizer transistor 84 .
- the different layout in the pre-charge and equalizer area 116 in this second preferred embodiment make the density of the metal lines 70 greater than in the first preferred embodiment.
- metal lines 70 pass the source/drain plugs 74 / 76 / 78 .
- a gate line plug 86 is directly above the gate line 56 .
- the gate line plug 86 electrically connects to the pre-charge transistor 80 / 82 through the metal lines 70 .
- the density of the metal lines 70 around the gate line plug 86 is greater than the density of the metal lines 70 at two sides of the share plug 66 . As a result, the fabricating process of patterning the metal lines 70 in the second preferred embodiment is more difficult.
Abstract
Description
- The present invention relates to layout of a sense amplifier, and more particularly to layout of a sense amplifier which has a share plug.
- Sense amplifiers are used in memory devices to allow for reduced voltage swing on bit lines. In a dynamic random access memory (DRAM) circuit, each data bit is stored in a small storage capacitor that is discharged quickly. A sense amplifier detects a signal representing the bit on a bit line and amplifies the signal to an amplitude close to the DRAM circuit's supply voltage. The capacitor is recharged as the signal is amplified. The data bit is refreshed before it ceases to be detectable, as the sense amplifier detects and amplifies the signal on a periodic basis, such as every few milliseconds.
- As the size of semiconductors is scaled down, the density of metal lines on the sense amplifier are increased. This larger density of metal lines makes them more difficult to be patterned.
- Therefore, there is a need to provide a sense amplifier layout having a lower density of metal lines than in the conventional art.
- According to a preferred embodiment of the present invention, a layout of a sense amplifier includes a substrate comprising a pre-charge and equalizer area. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. The pre-charge and equalizer area includes an active area disposed in the substrate, wherein the active area includes a first area extending toward the second direction, a second area and a third area extending from the first area toward the first direction. The second area and the third area are parallel to each other, and the first area is perpendicular to the second area. An insulating element is disposed in the substrate and surrounds the active area. An equalizer gate line and a pre-charge gate line are disposed on the substrate, wherein the equalizer gate line and the pre-charge gate line are parallel to the first area, and the equalizer gate line and the pre-charge gate line cover the second area, the insulating element and the third area. A gate line is disposed on the substrate and parallel to the first area. The gate line covers the first area and the insulating element, wherein the pre-charge gate line is disposed between the equalizer gate line and the gate line. Two source/drain plugs are disposed in the second area and respectively at two sides of the equalizer gate line. A share plug directly contacts the first area and the gate line.
- The present invention uses a share plug to decrease the number of metal lines, thereby reducing their density. In this way, it becomes easier to pattern the metal lines.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1 depicts a layout of a sense amplifier according to a first preferred embodiment of the present invention. -
FIG. 2 depicts an equivalent circuit diagram of the sense amplifier shown inFIG. 1 . -
FIG. 3 depicts magnified view of a portion of a pre-charge and equalizer area shown inFIG. 1 . -
FIG. 4 shows a sectional view taken along line AA′ inFIG. 3 . -
FIG. 5 shows a sectional view taken along line BB′ inFIG. 3 . -
FIG. 6 shows a sectional view taken along line AA′ inFIG. 3 according to another preferred embodiment of the present invention. -
FIG. 7 depicts the layout shown inFIG. 3 stacked with metal lines. -
FIG. 8 are sectional view taken along line CC′ and line DD′ inFIG. 7 . -
FIG. 9 shows a layout of a sense amplifier according to a second preferred embodiment of the present invention. -
FIG. 10 depicts a magnified view of a portion of a pre-charge and equalizer area shown inFIG. 9 stacked with metal lines. -
FIG. 1 depicts a layout of a sense amplifier according to a first preferred embodiment of the present invention. As shown inFIG. 1 , a layout of asense amplifier 100 includes asubstrate 10. Thesubstrate 10 may be a bulk silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, or a silicon carbide substrate. Thesubstrate 10 is divided into aswitch area 12, afirst transistor area 14, a pre-charge andequalizer area 16 and asecond transistor area 18. Thefirst transistor area 14 and thesecond transistor area 18 are respectively at two sides of the pre-charge andequalizer area 16. Thefirst transistor area 14 is preferably a P-type transistor area, and thesecond transistor area 18 is preferably an N-type transistor area. Theswitch area 12 is disposed at one side of thefirst transistor area 14. At least two transistors, such as P-type transistors 20/22, are disposed within thefirst transistor area 14. At least two transistors, such as N-type transistors 24/26, are disposed within thesecond transistor area 18. - A
switch transistor 28 is disposed in theswitch area 12. Theswitch transistor 28 is preferably an N-type transistor. Anequalizer transistor 30 and pre-chargetransistor 32 are disposed within the pre-charge andequalizer area 16. Theswitch area 12, thefirst transistor area 14, the pre-charge andequalizer area 16 and thesecond transistor area 18 are arranged symmetrically about the center line M. The transistors respectively in theswitch area 12, thefirst transistor area 14, the pre-charge andequalizer area 16, thesecond transistor area 18, and thetransistor 28 a in aswitch area 12 a defined symmetrically forma sense amplifier. In addition, the sense amplifier of the present invention is suitable for being applied in a DRAM (dynamic random access memory). -
FIG. 2 depicts an equivalent circuit diagram of the sense amplifier inFIG. 1 of the present invention. Please refer toFIG. 1 andFIG. 2 together. The P-type transistor 20, the P-type transistor 22, the N-type transistor 24, and the N-type transistor 26 constitute a latch circuit that stores data in thestorage nodes type transistor 22 and the N-type transistor 24 form an inverter, and respectively electrically connect to a voltage source Vcc and a voltage source Vss. The P-type transistor 20 and the N-type transistor 26 form another inverter, and respectively electrically connect to the voltage source Vcc and the voltage source Vss. The aforesaid inverters couple to each other to store data. - The
storage node 36 electrically connects to a source of theswitch transistor 28 a, and thestorage node 38 electrically connects to a source of theswitch transistor 28. The gates of theswitch transistor 28 a and theswitch transistor 28 are respectively coupled to a word line WL1; the drain of theswitch transistor 28 a and theswitch transistor 28 are respectively coupled to a bit line BL1 and a bit line BL2. - Furthermore, the gates of the
equalizer transistor 30, and pre-chargetransistor 32 respectively couple to a conductive line CL. A source and a drain of theequalizer transistor 30 respectively couple to the bit line BL1 and bit line BL2. A source and a drain of thepre-charge transistor 32 respectively couple to the bit line BL1 and bit line BL2. A drain of a transistor in theDRAM 40 electrically connects to the bit line BL2. A gate of the transistor in theDRAM 40 electrically connects to a word line WL2. -
FIG. 3 depicts a magnified view of a portion of the pre-charge and equalizer area shown inFIG. 1 . As shown inFIG. 1 andFIG. 3 , the pre-charge andequalizer area 16 includes thesubstrate 10. A pre-charge andequalizer area 16 is disposed on thesubstrate 10. A first direction X and a second direction Y are perpendicular to each other. Anactive area 42 is disposed on thesubstrate 10. Theactive area 42 includes afirst area 44, asecond area 46 and athird area 48. Thefirst area 44 extends toward the second direction Y, and thesecond area 46 and thethird area 48 extend from thefirst area 44 toward the first direction X. Thesecond area 46 and thethird area 48 are parallel to each other, and thefirst area 44 is perpendicular to thesecond area 46. The aforesaid term “extend” means that thefirst area 44 has a long side L1 and a wide side W1, wherein the long side L1 is greater than the wide side W1. The long side L1 is parallel to the second direction Y. Thesecond area 46 has a long side L2 and a wide side L2, and thethird area 48 has a long side L3 and a wide side W3. The long side L2 is greater than the wide side W2, and the long side L3 is greater than the wide side W3. The long side L2 and the long side L3 are parallel to the first direction X. - An insulating
element 50 is disposed in thesubstrate 10 and surrounds theactive area 42. Theactive area 42 may be formed by etching thesubstrate 10 to form numerous trenches, which are then filled with an insulating material to form the insulatingelement 50. The insulatingelement 50 defines theactive area 42 on thesubstrate 10, i.e. the material of theactive area 42 and thesubstrate 10 is the same. The insulatingelement 50 can be a shallow trench isolation formed by silicon oxide. - An
equalizer gate line 52 and apre-charge gate line 54 are disposed on thesubstrate 10. Theequalizer gate line 52 and thepre-charge gate line 54 are parallel to thefirst area 44. Theequalizer gate line 52 and thepre-charge gate line 54 respectively include a conductive gate and a gate dielectric layer. Theequalizer gate line 52 and thepre-charge gate line 54 cover thesecond area 46, the insulatingelement 50 and thethird area 48. Aconductive line 56 is disposed on thesubstrate 10 and parallel to thefirst area 44. Theconductive line 56 includes a conductive gate and a gate dielectric layer. Theconductive line 56 covers the first striped are 44 and the insulatingelement 50. Thepre-charge gate line 54 is disposed between theequalizer gate line 52 and thegate line 56. Two source/drain plugs 58/60 are disposed in thesecond area 46 and respectively at two sides of theequalizer gate line 52. Another two source/drain plugs 62/64 are disposed within thethird area 48 and at two sides of theequalizer gate line 52. Ashare plug 66 directly contacts thefirst area 44 and thegate line 56. - The
pre-charge gate line 54, the source/drain plug 60 between theequalizer gate line 52 and thepre-charge gate line 54, theshare plug 66, and part of theactive area 42 form apre-charge transistor 32. Theequalizer gate line 52, the two source/drain plugs 58/60, and part of theactive area 42 form anequalizer transistor 30. It is noteworthy that theshare plug 66 directly contacts thefirst area 44 of theactive area 44 and thegate line 56, theshare plug 66 serving as a source/drain plug of thepre-charge transistor 32 and a gate plug of thegate line 56 simultaneously. Thegate line 56 is a conductive line providing thesense amplifier 34 with a voltage of bit line pre-charge (VBLP) during a pre-charge stage. As shown inFIG. 2 , the VBLP is applied to thepre-charge transistor 32. -
FIG. 4 shows a sectional view taken along line AA′ inFIG. 3 . As shown inFIG. 3 andFIG. 4 , thegate line 56 has a long side L4 and a wide side W4. The long side L4 is greater than the wide side W4. The wide side W4 of thegate line 56 covers both the insulatingelement 50 and thefirst area 44. Furthermore, theshare plug 66 directly contacts both thefirst area 44 and thegate line 56. Aninterlayer dielectric layer 68 covers thegate line 56.FIG. 5 shows a sectional view taken along line BB′ inFIG. 3 . Please refer toFIG. 3 andFIG. 5 together. Theinterlayer dielectric layer 68 covers theequalizer gate line 52 and thepre-charge gate line 54. -
FIG. 6 shows a sectional view taken along line AA′ inFIG. 3 according to another preferred embodiment of the present invention. The difference betweenFIG. 6 andFIG. 4 is that the top surface of thegate line 56 inFIG. 6 forms a step profile. In detail, the top surface of thegate line 56 includes a firsttop surface 156 and a secondtop surface 256. The firsttop surface 156 and the secondtop surface 256 form the step profile. The firsttop surface 156 directly contacts theinterlayer dielectric layer 68. The secondtop surface 256 directly contacts theshare plug 66 and is parallel to the firsttop surface 156. The firsttop surface 156 and the secondtop surface 256 are not coplanar. Therefore, the contact area between theshare plug 66 and thegate line 56 inFIG. 6 is greater than inFIG. 4 . In this way, the resistance of theshare plug 66 can be reduced. -
FIG. 7 depicts the layout inFIG. 3 stacked with metal lines.FIG. 8 is a sectional view taken along line CC′ and line DD′ inFIG. 7 . Please refer toFIG. 7 andFIG. 8 together.Numerous metal lines 70 are disposed in the pre-charge andequalizer area 16. Eachmetal line 70 extends toward the first direction X, and crosses thefirst area 44, thesecond area 46, and the third area of theactive area 42, and crosses the insulatingelement 50. Theinterlayer dielectric layer 68 covers theequalizer gate line 52, thepre-charge gate line 54, and thegate line 56. The source/drain plugs 58/60/62/64 and theshare plug 66 penetrate theinterlayer dielectric layer 68. It is noteworthy that theshare plug 66 does not contact anymetal line 70 disposed on and contacting theinterlayer dielectric layer 68. In other words, theshare plug 66 does not electrically connect through themetal lines 70 to any plug which penetrates theinterlayer dielectric layer 68. Themetal lines 70 pass the source/drain plugs 58/60/62/64 to electrically connect to contact plugs in other regions. Because nometal line 70 passes theshare plug 66, the space above theshare plug 66 is not occupied by the metal lines 70. On the other hand,metal lines 70 pass the source/drain plugs 58/60/62/64, meaning the space above the source/drain plugs 58/60/62/64 is occupied by the metal lines 70. Therefore, the space S1 between twometal lines 70 at two sides of theshare plug 70 is greater than the space S2 between themetal line 70 directly above the source/drain plug 58 and themetal line 70 adjacent to themetal line 70 directly above the source/drain plug 58. The space S2 is also between themetal line 70 directly above the source/drain plugs 60/62/64 and themetal line 70 adjacent to themetal line 70 directly above the source/drain plugs 60/62/64. Because the space S1 is greater than the space S2, the fabricating process of themetal lines 70 can be simplified. A distance D is between the top surface of theshare plug 66 and themetal line 70 adjacent to theshare plug 66, wherein the space S1 is greater than the space S2. Therefore, the parasitic capacitance around theshare plug 66 is reduced. -
FIG. 9 shows a layout of a sense amplifier according to a second preferred embodiment of the present invention, wherein elements which are substantially the same as those in the first preferred embodiment are denoted by the same reference numerals; an accompanying explanation is therefore omitted.FIG. 10 depicts a magnified view of a portion of the pre-charge and equalizer area inFIG. 9 stacked with metal lines. - As shown in
FIG. 9 , a layout of asense amplifier 200 includes asubstrate 10. Thesubstrate 10 is divided into aswitch area 12, afirst transistor area 14, a pre-charge andequalizer area 116 and asecond transistor area 18. It is noteworthy that the layout of the pre-charge andequalizer area 116 in the second preferred embodiment is different from the layout of the pre-charge andequalizer area 16 in the first preferred embodiment. Other areas in the second preferred embodiment are the same as in the first preferred embodiment. In the second preferred embodiment,pre-charge transistors 80/82 and anequalizer transistor 84 share onecommon gate line 72, the active area is constituted by numerous “I”-shaped patterns, and there is no share plug in the pre-charge andequalizer area 116. In the first preferred embodiment, the gate line of thepre-charge transistor 32, and the gate line of theequalizer transistor 30 do not connect to each other, theactive area 42 is comb-shaped, and there is ashare plug 66. As shown inFIG. 10 , in the second preferred embodiment, the source/drain plugs 74/76 and thecommon gate line 72 constitute thepre-charge transistor 80. The source/drain plugs 76/78 and thecommon gate line 72 constitute anotherpre-charge transistor 82. The source/drain plugs 74/78 and thecommon gate line 72 constitute theequalizer transistor 84. - The different layout in the pre-charge and
equalizer area 116 in this second preferred embodiment make the density of themetal lines 70 greater than in the first preferred embodiment. In the second preferred embodiment,metal lines 70 pass the source/drain plugs 74/76/78. Agate line plug 86 is directly above thegate line 56. The gate line plug 86 electrically connects to thepre-charge transistor 80/82 through the metal lines 70. As there is no share plug in the second preferred embodiment, and there aremore metal lines 70 in the pre-charge andequalizer area 116 than in the pre-charge andequalizer area 16, the density of themetal lines 70 around thegate line plug 86 is greater than the density of themetal lines 70 at two sides of theshare plug 66. As a result, the fabricating process of patterning themetal lines 70 in the second preferred embodiment is more difficult. - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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CN201810361216.9 | 2018-04-20 |
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US5056063A (en) * | 1990-05-29 | 1991-10-08 | Texas Instruments Incorporated | Active sense amplifier with dynamic pre-charge transistor |
DE19836736C1 (en) * | 1998-08-13 | 1999-12-30 | Siemens Ag | Combination type precharging and equalising-circuit for semiconductor memory device |
JP4911838B2 (en) | 2001-07-06 | 2012-04-04 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
KR100600047B1 (en) * | 2004-05-06 | 2006-07-13 | 주식회사 하이닉스반도체 | Semiconductor memory device |
US7511982B2 (en) * | 2004-05-06 | 2009-03-31 | Sidense Corp. | High speed OTP sensing scheme |
CN100468955C (en) * | 2006-02-21 | 2009-03-11 | 立积电子股份有限公司 | Cascode and serial low-noise amplifier implemented by single-end input and differential output |
US20080042171A1 (en) * | 2006-08-18 | 2008-02-21 | Sebastian Mosler | Transistor arrangement, sense-amplifier arrangement and methods of manufacturing the same via a phase shift mask |
US20080116496A1 (en) | 2006-11-21 | 2008-05-22 | Kuo-Chyuan Tzeng | Integrating a DRAM with an SRAM having butted contacts and resulting devices |
KR101816525B1 (en) * | 2010-10-01 | 2018-02-21 | 삼성전자주식회사 | Layout Method For Differential Amplifier And Layout Using The Same |
US8531902B2 (en) * | 2011-06-30 | 2013-09-10 | Qualcomm Incorporated | Sensing circuit |
US20130009250A1 (en) * | 2011-07-06 | 2013-01-10 | Mediatek Inc. | Dummy patterns for improving width dependent device mismatch in high-k metal gate process |
US8976611B2 (en) * | 2013-03-15 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Asymmetric sensing amplifier, memory device and designing method |
CN104714708B (en) * | 2013-12-11 | 2018-12-14 | 新益先创科技股份有限公司 | control point sensing panel and design method thereof |
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