CN110379807B - 微电子器件及微电子器件制作方法 - Google Patents

微电子器件及微电子器件制作方法 Download PDF

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CN110379807B
CN110379807B CN201910702386.3A CN201910702386A CN110379807B CN 110379807 B CN110379807 B CN 110379807B CN 201910702386 A CN201910702386 A CN 201910702386A CN 110379807 B CN110379807 B CN 110379807B
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substrate
doping
epitaxial structure
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basis
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CN110379807A (zh
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蔡文必
刘成
叶念慈
林育赐
赵杰
梁玉玉
杨健
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Hunan Sanan Semiconductor Co Ltd
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Xiamen Sanan Integrated Circuit Co Ltd
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Priority to PCT/CN2020/103335 priority patent/WO2021017954A1/zh
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Abstract

本申请实施例提供一种微电子器件及微电子器件制作方法，该微电子器件包括基于衬底制作形成的至少两个相互间隔的、与衬底掺杂类型相反的掺杂阱，及基于衬底一侧制作形成的与各掺杂阱接触的外延结构。所述外延结构远离衬底一侧设置有相互级联的至少两个功率器件，其中每个功率器件与一个掺杂阱对应设置，且各功率器件的低电位端与其对应的掺杂阱连接。如此，通过在衬底中形成相互间隔的掺杂阱，且将各个功率器件的低电位端连接至对应的掺杂阱，使得衬底电压和各个功率器件的低电位端为相同电位，抑制因电子注入到外延结构中而造成功率器件性能的偏移或退化。

Description

微电子器件及微电子器件制作方法
技术领域
本申请涉及半导体制作技术领域，具体而言，涉及微电子器件及微电子器件制作方法。
背景技术
GaN电力电子器件是实现下一代的高功率密度和高效率的电力转换应用的关键技术。而GaN单芯片集成电路可以实现GaN基电路转换系统性能的最大化。目前，在集成电路中常采用半桥结构，即上、下两个功率器件级联，再连通至下方衬底。这种结构中，由于GaN器件外延结构的特殊性，上、下两个功率器件共用同一个体电势(衬底电势)，使得衬底相对于上、下两个功率器件的电应力不同，容易对功率器件的性能造成不良影响。
发明内容
为了至少克服现有技术中的上述不足，本申请实施例提供一种微电子器件及微电子器件制作方法。
第一方面，本发明实施例提供一种微电子器件，包括：
衬底；
基于所述衬底制作形成的至少两个相互间隔的掺杂阱，每个所述掺杂阱的掺杂类型与所述衬底的掺杂类型相反；
基于所述衬底一侧制作形成的外延结构，该外延结构与各所述掺杂阱接触；
基于所述外延结构远离所述衬底一侧设置的相互级联的至少两个功率器件，其中，每个所述功率器件与一个所述掺杂阱对应设置，且各所述功率器件的低电位端与其对应的掺杂阱连接。
在可选的实施方式中，所述外延结构上开设有贯穿其两侧且延伸至所述掺杂阱的通孔，所述通孔内填充有导电金属，各所述功率器件的低电位端通过所述通孔内的导电金属与其对应的掺杂阱连接。
在可选的实施方式中，所述外延结构包括：
基于所述衬底一侧制作形成的缓冲层，该缓冲层与各所述掺杂阱接触；
基于所述缓冲层远离所述衬底一侧制作形成的高阻层；
基于所述高阻层远离所述缓冲层一侧制作形成的沟道层；以及
基于所述沟道层远离所述高阻层一侧制作形成的势垒层；
其中，在相邻两个功率器件之间设置有隔离结构，该隔离结构将该相邻两个功率器件的沟道层电气隔离。
在可选的实施方式中，相邻两个所述掺杂阱之间的间隔距离大于或等于1um。
在可选的实施方式中，所述功率器件包括MOS管，所述MOS管的源极作为低电位端与其对应的掺杂阱连接。
在可选的实施方式中，所述功率器件包括二极管，所述二极管的阴极作为低电位端与其对应的掺杂阱连接。
在可选的实施方式中，所述衬底为P型衬底，所述掺杂阱为N型掺杂阱；或者，
所述衬底为N型衬底，所述掺杂阱为P型掺杂阱。
在可选的实施方式中，若所述掺杂阱为N型掺杂阱，该N型掺杂阱中掺杂有浓度为1e17cm-3-1e20cm-3的铝杂质或硼杂质；
若所述掺杂阱为P型掺杂阱，该P型掺杂阱中掺杂有浓度为1e17cm-3-1e20cm-3的磷杂质或砷杂质。
在可选的实施方式中，所述衬底为Si衬底、SOI衬底或SiC衬底中的任意一种。
第二方面，本发明实施例提供一种微电子器件制作方法，所述方法包括：
提供一衬底；
基于所述衬底制作形成至少两个相互间隔的掺杂阱，每个所述掺杂阱的掺杂类型与所述衬底的掺杂类型相反；
基于所述衬底一侧制作形成外延结构，该外延结构与各所述掺杂阱接触；
基于所述外延结构远离所述衬底一侧设置相互级联的至少两个功率器件，其中，每个所述功率器件与一个所述掺杂阱对应设置，且各所述功率器件的低电位端与其对应的掺杂阱连接。
相对于现有技术而言，本申请具有以下有益效果：
本申请实施例提供的微电子器件中，包括基于衬底制作形成的至少两个相互间隔的、与衬底掺杂类型相反的掺杂阱，及基于衬底一侧制作形成的与各掺杂阱接触的外延结构。所述外延结构远离衬底一侧设置有相互级联的至少两个功率器件，其中每个功率器件与一个掺杂阱对应设置，且各功率器件的低电位端与其对应的掺杂阱连接。如此，通过在衬底中形成相互间隔的掺杂阱，且将各个功率器件的低电位端连接至对应的掺杂阱，抑制因电子注入到外延结构中而造成功率器件性能的偏移或退化。
为使本申请的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请实施例提供的微电子器件剖面结构示意图之一。
图2为本申请实施例提供的微电子器件剖面结构示意图之二。
图3为本申请实施例提供的微电子器件剖面结构示意图之三。
图4为本申请实施例提供的级联功率器件电路连接示意图。
图5为本申请实施例提供的微电子器件制作方法的流程图。
图标：10-微电子器件；11-衬底；111-背衬底；112-埋氧化层；113-顶层硅；12-掺杂阱；13-外延结构；131-缓冲层；132-高阻层；133-沟道层；134-势垒层；135-P型半导体层；14-功率器件；15-通孔；16-隔离结构。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
宽禁带半导体材料氮化镓(GaN)相比于硅具有更高的击穿场强、更高的电子迁移率以及更低的本征载流子浓度等优点。基于GaN材料的电力电子器件具有更高的工作电压、更小的导通电阻和更高的操作频率等卓越性能，可实现下一代的高效率和高功率密度的电力转换应用。集成GaN开关器件和基于GaN材料单片集成的驱动器等，除了可以降低电源模块的重量及效率，还可以提高电源模块在复杂工作环境下的稳定性。
单片电路的稳定性除了需要考虑单颗GaN器件在开关过程中的稳定性之外，还需要以电路工作角度出发分析多颗GaN器件在不同工作状态下的稳定性。目前单片电路常采用的半桥结构中，常见的状态连接方式主要有两种。
其中一种连接方式中，对应单片集成电路的低电位端的功率器件的源极与下方的衬底连接(衬底为接地电位)，对应其高电位端的功率器件的源极浮空(未与下方衬底连接)。这种连接模式下，衬底电势相对于上、下器件产生电应力不同。另外一种连接方式是，对应单片集成电路的高电位端的功率器件的源极与下方的衬底连接(衬底为浮空电位)，而对应其低电位端的功率器件的源极接地。同样地，该连接模式中衬底电势相对于上、下器件产生的电应力不同。该类连接模式由于衬底相对于上、下管电应力不同，易导致功率器件的性能退化。
对此，如图1所示，本申请实施例提供一种微电子器件10，在衬底11中形成相互间隔的至少两个掺杂阱12，且各个掺杂阱12的掺杂类型与衬底11的掺杂类型相反。然后在衬底11一侧制作形成外延结构13之后，在外延结构13上设置级联的至少两个功率器件14(图中示出两个功率器件14)，且各个功率器件14的低电位端与对应的掺杂阱12连接。如此，在衬底11上通过掺杂阱12实现区域化电气隔离，将衬底11中各个掺杂阱12分别与各个功率器件14的低电位端连接，一定程度上抑制因电子注入到外延结构13中而造成功率器件14性能的偏移或退化。
请再次参阅图1，图1为本申请实施例提供的微电子器件10的剖面结构示意图，该微电子器件10包括衬底11、基于衬底11制作形成的至少两个相互隔离的掺杂阱12、基于衬底11一侧制作形成的与各掺杂阱12接触的外延结构13，以及基于外延结构13远离衬底11一侧设置的相互级联的至少两个功率器件14。
其中，该衬底11可以采用硅(Si)衬底、绝缘隔离硅(Silicon-On-Insulator，SOI)衬底、具有更好的PN结击穿电场的碳化硅(SiC)衬底，或者是本领域技术人员公知的任何其他适合外延生长GaN材料的衬底，本申请对此不作具体限制。
请参阅图2，在采用的衬底11为SOI衬底时，该SOI衬底包括背衬底111、基于背衬底111之上的顶层硅113，并且，在背衬底111和顶层硅113之间还包括一层埋氧化层112。其中，埋氧化层112可以基于背衬底111进行氧注入和热退火(即SIMOX方法)处理所形成。该埋氧化层112可以为顶层硅113提供更好的背面电气绝缘特性，从而可以降低对掺杂阱12的掺杂浓度及阱深的要求。
本实施例中，在衬底11内形成的至少两个相互间隔的掺杂阱12中，掺杂阱12的数量可根据实际实施时功率器件14的数量进行设定，掺杂阱12可与功率器件14一一对应。
在本实施例中，功率器件14可以为MOS管或二极管，具体可以包括增强型器件(E-mode HEMT)、耗尽型器件(D-mode HEMT)、横向场效应整流管(L-FER)、肖特基二极管(SBD)等。其中E-mode HEMT器件制作方法包含P-GaN栅型HEMT器件、P-AlGaN栅型HEMT器件、凹栅型MISHEMT器件、采用F离子注入栅的HEMT器件等。
实际实施时，各个功率器件14可以级联组合以构成多种功能电路，各个功率器件14之间可以采用在片金属线或离片电路板互联的方式进行级联。本实施例中，图1示出了功率器件14为MOS管时的微电子器件10的剖面结构示意图。
在衬底11内形成掺杂阱12时，具体地，首先可在衬底11一侧形成光刻胶层，可通过涂覆光刻胶的方式在衬底11上形成光刻胶层。其中，采用的光刻胶可以是反转胶AE5214或反转胶SPR220，涂覆的光刻胶的厚度可以大约为1微米。再使用掩膜版对衬底11上的光刻胶层进行光刻并显影，从而使衬底11的部分区域暴露出，而衬底11上暴露出的部分区域即为掺杂区域。掺杂阱12可基于该掺杂区域进行制作。基于衬底11上通过光刻工艺暴露出的掺杂区域，采用离子注入加高温激活或热扩散的方式以形成如图3中所示的掺杂阱12。
在制作形成掺杂阱12之后，可利用有机溶剂去除衬底11上的光刻胶，可采用N甲基吡咯烷酮或丙酮对光刻胶进行去除处理。再利用氧气等离子体对去除处理后的器件进行再次滤除处理，以确保光刻胶被完全去除。
本实施例中，为了避免相邻掺杂阱12之间的离子偏移，相邻两个掺杂阱12之间的间隔距离可大于或等于1um。此外，各个掺杂阱12的深度可设置为0.1um-10um。
应当理解，在半导体(例如硅)中已经历添加了受体原子(例如硼)以便于增大自由正空穴电荷载流子的数目的掺杂工艺，则该半导体可以为P型或叫P型掺杂。相反，如果半导体已经历添加了施体原子(例如磷)以便于增大自由负电子电荷载流子的数目的掺杂工艺，则该半导体可以为N型或者叫N型掺杂。
本实施例中，为了通过相互间隔的掺杂阱12以实现不同功率器件14之间的电气隔离，使得掺杂阱12与衬底11之间形成反向偏置的PN结，故而，各个掺杂阱12的掺杂类型与衬底11的掺杂类型相反。例如，在衬底11为P型衬底时，各个掺杂阱12为N型掺杂阱。而在衬底11为N型衬底时，各个掺杂阱12为P型掺杂阱。
在掺杂阱12为N型掺杂阱时，该N型掺杂阱中掺杂有浓度为1e17cm-3-1e20cm-3的铝杂质或硼杂质。在所述掺杂阱12为P型掺杂阱时，该P型掺杂阱中掺杂有浓度为1e17cm-3-1e20cm-3的磷杂质或砷杂质。
在上述基础上，在衬底11一侧还制作形成有外延结构13，该外延结构13可以采用但不限于外延生长工艺在衬底11上生长形成，例如气相沉积(MOCVD)、气相外延(HVPE)、或分子束外延(MBE)等生长方式。
请参阅图3，本实施例中，上述外延结构13包括基于衬底11一侧制作形成的缓冲层131，该缓冲层131与衬底11内的各掺杂阱12接触。基于缓冲层131的远离衬底11一侧制作形成有高阻层132，在高阻层132远离缓冲层131一侧制作形成有沟道层133，并且在沟道层133远离高阻层132一侧制作形成有势垒层134。其中，缓冲层131、高阻层132以及沟道层133可以为但不限于GaN材料层，势垒层134可以采用但不限于AlGaN、AlN或InAlN等本领域技术人员公知的可以与所述GaN(沟道层133)形成二维电子气的材料制成。
在上述基础上，在外延结构13的远离衬底11一侧设置的至少两个功率器件14中，各个功率器件14分别与下方的掺杂阱12对应。并且，各个功率器件14的低电位端与其对应的掺杂阱12连接。
本实施例中，各个功率器件14的低电位端分别与其对应的掺杂阱12连接，具体地，在外延结构13上开设有贯穿其两侧且延伸至掺杂阱12的通孔15，通孔15内填充有导电金属，可以包括，但不限于银、铜、金或铝等导电金属。各功率器件14的低电位端通过通孔15内的导电金属与其对应的掺杂阱12连接。应当理解，通孔15的数量不少于功率器件14的数量，且通孔15开设的位置对应于下方的掺杂阱12以及上方的功率器件14，从而达到通过填充的导电金属连接功率器件14及掺杂阱12的目的。
本实施例中，可通过对外延结构13进行刻蚀形成通孔15。通孔15的形状不作具体限制，可以是圆形通孔、方形通孔或者是矩形通孔等，具体不作限定，只要是能够实现贯穿外延结构13并延伸至衬底11内的掺杂阱12即可。
在进行通孔15的刻蚀时，可将对外延结构13的刻蚀截止于掺杂阱12的表面，即通孔15贯穿外延结构13即可。也可以如图3中所示，将对外延结构13刻蚀贯穿之后并延伸至掺杂阱12内，并在掺杂阱12的表面形成凹槽。本实施例中，对于通孔15的深度并不作具体限定。
在本实施例中，在功率器件14为MOS管时，外延结构13还可以包括用于制作增强型器件的P型半导体层135，该P型半导体层135可以是P-GaN层，也可采用P-AlGaN层。该P型半导体层135制作形成于势垒层134的远离沟道层133的一侧。并且，基于势垒层134上在势垒层134的相对两端制作形成有源极以及漏极，在P型半导体层135上方制作形成有栅极。MOS管的源极作为低电位端通过通孔15内的导电金属与其对应的掺杂阱12连接。
请结合参阅图3和图4，基于本实施例的层级结构设计，在级联的MOS管的个数为两个时，则对应单片集成电路的高电位(HS)端的功率器件G1的源极可通过下方掺杂阱12以与衬底11连接。同样，对应集成电路的低电位(LS)端的功率器件G2的源极可通过下方掺杂阱12以与衬底11连接。从而，抑制因沟道层133中电子被外延结构13中的缺陷俘获，而造成功率器件14性能的偏移或退化。
此外，在功率器件14为二极管时，二极管的阴极作为低电位端通过通孔15内的导电金属与其对应的掺杂阱12连接，此种情形下，与MOS管具有相同的实现原理，在此不再赘述。
进一步地，在上述外延结构13中，在相邻两个功率器件14之间设置有隔离结构16，该隔离结构16将该相邻两个功率器件14的沟道层133电气隔离。其中，该隔离结构16可以是沟槽，或者是通过离子注入方式所形成的隔离物质。此外，该隔离结构16还可将该相邻两个功率器件14的势垒层134电气隔离。
本实施例中，隔离结构16可以分别设置在相邻两个功率器件14之间的通孔15的两侧，从而将该相邻两个功率器件14的沟道层133电气隔离。也可以是设置在相邻两个功率器件14之间的通孔15的同一侧，具体不作限制，只要能够实现相邻两个功率器件14的电气隔离即可。
如此，通过在衬底11内形成相互间隔的掺杂阱12以构造PN结，实现不同功率器件14的衬底11的电势分开控制及电气隔离，可极大地提升硅基GaN单片集成电路的可靠性。
请参阅图5，本申请实施例还提供一种微电子器件制作方法，用于上述微电子器件10的制作，所应说明的是，本实施例给出的微电子器件10制作方法并不以图5以及以下所述的具体顺序为限制。应当理解，本实施例所述的微电子器件10制作方法中的部分步骤的顺序可以根据实际需要相互交换，或者其中的部分步骤也可以省略或删除，本实施例在此不做限制。
步骤S110，提供一衬底11。
步骤S120，基于所述衬底11制作形成至少两个相互间隔的掺杂阱12，每个所述掺杂阱12的掺杂类型与所述衬底11的掺杂类型相反。
步骤S130，基于所述衬底11一侧制作形成外延结构13，该外延结构13与各所述掺杂阱12接触。
步骤S140，基于所述外延结构13远离所述衬底11一侧设置相互级联的至少两个功率器件14，其中，每个所述功率器件14与一个所述掺杂阱12对应设置，且各所述功率器件14的低电位端与其对应的掺杂阱12连接。
可以理解的是，通过上述步骤S110-步骤S140中给出的工艺流程可制作得到如图1中所示的微电子器件10，其中，关于各步骤的详细描述可参照上述实施例中对微电子器件10的描述，本实施例在此不再赘述。
综上所述，本申请提供一种微电子器件10及微电子器件制作方法，包括基于衬底11制作形成的至少两个相互间隔的、与衬底11掺杂类型相反的掺杂阱12，及基于衬底11一侧制作形成的与各掺杂阱12接触的外延结构13。并且，还包括基于外延结构13远离衬底11一侧设置的相互级联的至少两个功率器件14，其中每个功率器件14与一个掺杂阱12对应设置，且各功率器件14的低电位端与其对应的掺杂阱12连接。如此，通过在衬底11中形成相互间隔的掺杂阱12，且将各个功率器件14的低电位端连接至对应的掺杂阱12，抑制因电子注入到外延结构13中而造成功率器件14性能的偏移或退化。
以上所述，仅为本申请的各种实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应所述以权利要求的保护范围为准。

Claims (6)

1.一种微电子器件，其特征在于，包括：
衬底；
基于所述衬底制作形成的至少两个相互间隔的掺杂阱，每个所述掺杂阱的掺杂类型与所述衬底的掺杂类型相反；
基于所述衬底一侧制作形成的外延结构，该外延结构与各所述掺杂阱接触，该外延结构包括基于所述衬底一侧制作形成的与各所述掺杂阱接触的缓冲层、基于所述缓冲层远离所述衬底一侧制作形成的高阻层、基于所述高阻层远离所述缓冲层一侧制作形成的沟道层、基于所述沟道层远离所述高阻层一侧制作形成的势垒层；
基于所述外延结构远离所述衬底一侧设置的相互级联的至少两个功率器件，其中，每个所述功率器件与一个所述掺杂阱对应设置，且各所述功率器件的低电位端与其对应的掺杂阱连接，以抑制所述沟道层中的电子被所述外延结构中的缺陷所俘获，且所述衬底不发生相对于上下两个功率器件电应力不同的现象；
其中，所述外延结构上开设有贯穿其两侧且延伸至所述掺杂阱的通孔，各所述功率器件的低电位端通过所述通孔与其对应的掺杂阱连接，所述通孔设置在各所述功率器件的器件有源区之外；
所述衬底为SOI衬底，所述SOI衬底包括背衬底、形成于所述背衬底之上的顶层硅以及形成于所述背衬底和所述顶层硅之间的埋氧化层，所述埋氧化层基于所述背衬底进行氧注入和热退火处理所形成，至少两个掺杂阱设置在顶层硅中；
所述微电子器件还包括：
设置在相邻两个功率器件之间的隔离结构，该隔离结构将该相邻两个功率器件的沟道层电气隔离，所述通孔设置在所述隔离结构内。
2.根据权利要求1所述的微电子器件，其特征在于，所述通孔内填充有导电金属，各所述功率器件的低电位端通过所述通孔内的导电金属与其对应的掺杂阱连接。
3.根据权利要求1所述的微电子器件，其特征在于，相邻两个所述掺杂阱之间的间隔距离大于或等于1um。
4.根据权利要求1所述的微电子器件，其特征在于，所述衬底为P型衬底，所述掺杂阱为N型掺杂阱；或者，
所述衬底为N型衬底，所述掺杂阱为P型掺杂阱。
5.根据权利要求4所述的微电子器件，其特征在于，若所述掺杂阱为N型掺杂阱，该N型掺杂阱中掺杂有浓度为1e17cm-3-1e20cm-3的铝杂质或硼杂质；
若所述掺杂阱为P型掺杂阱，该P型掺杂阱中掺杂有浓度为1e17cm-3-1e20cm-3的磷杂质或砷杂质。
6.一种微电子器件制作方法，其特征在于，所述方法包括：
提供一衬底；
基于所述衬底制作形成至少两个相互间隔的掺杂阱，每个所述掺杂阱的掺杂类型与所述衬底的掺杂类型相反；
基于所述衬底一侧制作形成外延结构，该外延结构与各所述掺杂阱接触；
基于所述外延结构远离所述衬底一侧设置相互级联的至少两个功率器件，其中，每个所述功率器件与一个所述掺杂阱对应设置，且各所述功率器件的低电位端与其对应的掺杂阱连接，以抑制所述外延结构包含的沟道层中的电子被所述外延结构中的缺陷所俘获，且所述衬底不发生相对于上下两个功率器件电应力不同的现象；
其中，所述外延结构上开设有贯穿其两侧且延伸至所述掺杂阱的通孔，各所述功率器件的低电位端通过所述通孔与其对应的掺杂阱连接，所述通孔设置在各所述功率器件的器件有源区之外；
所述衬底为SOI衬底，所述SOI衬底包括背衬底、形成于所述背衬底之上的顶层硅以及形成于所述背衬底和所述顶层硅之间的埋氧化层，所述埋氧化层基于所述背衬底进行氧注入和热退火处理所形成，至少两个掺杂阱设置在顶层硅中；
所述基于所述衬底一侧制作形成外延结构的步骤，包括：
基于所述衬底一侧制作形成与各所述掺杂阱接触的缓冲层，基于所述缓冲层远离所述衬底一侧制作形成高阻层，基于所述高阻层远离所述缓冲层一侧制作形成沟道层，基于所述沟道层远离所述高阻层一侧制作形成势垒层；
所述方法还包括：
在相邻两个功率器件之间设置隔离结构，该隔离结构将该相邻两个功率器件的沟道层电气隔离，所述通孔设置在所述隔离结构内。
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