CN110364449B - 栅氧掺氮退火温度的监控方法 - Google Patents

栅氧掺氮退火温度的监控方法 Download PDF

Info

Publication number
CN110364449B
CN110364449B CN201910670110.1A CN201910670110A CN110364449B CN 110364449 B CN110364449 B CN 110364449B CN 201910670110 A CN201910670110 A CN 201910670110A CN 110364449 B CN110364449 B CN 110364449B
Authority
CN
China
Prior art keywords
layer
gate oxide
monitoring
annealing temperature
overlay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910670110.1A
Other languages
English (en)
Other versions
CN110364449A (zh
Inventor
李中华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Original Assignee
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Integrated Circuit Manufacturing Co Ltd filed Critical Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority to CN201910670110.1A priority Critical patent/CN110364449B/zh
Publication of CN110364449A publication Critical patent/CN110364449A/zh
Priority to US16/702,924 priority patent/US10978360B2/en
Application granted granted Critical
Publication of CN110364449B publication Critical patent/CN110364449B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • H01L21/67248Temperature monitoring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54426Marks applied to semiconductor devices or parts for alignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种栅氧掺氮退火温度的监控方法,包括步骤:步骤一、在测试硅片上形成零标记层图形。步骤二、形成氮掺杂的栅氧化层,包括:氧化层生长工艺,对氧化层进行掺氮工艺,进行栅氧掺氮退火工艺。步骤三、形成套刻层图形,套刻层图形和对应的零标记层图形相套准形成监控结构。步骤四、测量各监控结构的套刻层图形和对应的零标记层图形之间的套准值,根据所测量的套准值调整栅氧掺氮退火温度。本发明能监控栅氧掺氮退火温度在二维平面上对栅氧化层的影响,并进而能调节栅氧掺氮退火温度并提高产品良率。

Description

栅氧掺氮退火温度的监控方法
技术领域
本发明涉及一种半导体集成电路制造方法,特别是涉及一种栅氧掺氮退火温度的监控方法。
背景技术
MOSFET是半导体器件电路的基本器件,MOSFET的栅极结构中需要采用栅介质层,栅介质层通常采用由SiO2材料组成栅氧化层,栅氧化层通常是对硅衬底进行氧化形成。随着半导体集成电路制造技术的不断发生,器件的特征尺寸不断等比例缩小,对于MOSFET来说,栅氧化层的厚度也会不断减小,栅氧化层的厚度减少能增加栅极电容,从而有利于提升MOSFET的驱动电流,从而提升器件的性能。
但是当半导体技术的工艺节点到达90nm以下时,栅氧化层的厚度后减少到
Figure BDA0002141425780000011
以下,过薄的栅氧化层会带来栅漏电流增加的缺陷以及栅极结构中的多晶硅栅的杂质容易穿过栅氧化层进入到硅衬底中的缺陷,故栅氧化层的厚度的降低有下限。
为了保持栅极电容不变而又不降低栅介质层的厚度,通常会采用提高栅介质层的介电系数(K)。一种方法是采用和栅氧化层不同的材料即采用高介电常数(HK)材料作为栅介质层,如采用HK材料包括氮氧化铪硅(HfSiON)等。但是HK材料的形成工艺相对复杂,成本高,开发周期长。
为此,现有一种常用的方法是,在栅氧化层中进行掺氮,栅氧化层在掺氮后SiO2中的氧会部分被N替换从而变成SiON。由于掺氮后的栅氧化层的K值会增加,故能在不降低栅氧化层的厚度的条件下提高器件的性能,从而能防止栅氧化层的厚度降低而带来的栅漏电的增加以及多晶硅栅的杂质通过栅氧化层扩散到硅衬底中。
现有掺氮栅氧化层的形成方法通常采用如下步骤:
首先、采用原位水汽生成(In-Situ Steam Generation,ISSG)对硅衬底片即硅片进行氧化形成氧化层即SiO2层。ISSG工艺通常是在氧气中通入少量的氢气作为催化剂,氧气和氢气反应后会形成水汽以及自由基氧原子,自由基氧原子会和硅反应形成SiO2。
之后、采用去耦等离子氮化(Decoupled Plasma Nitridation,DPN)工艺对所述氧化层进行掺氮工艺,即采用氮气形成的等离子体向SiO2中掺杂。
之后、进行栅氧掺氮退火即后氮化退火(Post Nitridation Anneal,PNA),PNA工艺能使DPN工艺中掺入的氮杂质稳定即使Si-N键稳定以及能修复栅氧化层中由于等离子作用而产生的损伤。
在上述三步工艺中,PNA的工艺条件最后会影响到栅氧化层中处于稳定状态的Si-N键分布,会对栅氧化层的性能有较大影响,故对PNA的工艺条件如退火温度调节很重要。但是对PNA的工艺条件的调节首先需要对PNA的工艺波动进行监控,之后才能根据监控结果进行工艺条件的调节。
现有方法中,业界对栅氧掺氮退火即PNA温度波动的监控是靠观察光片即测试硅片的Z方向上栅氧化层的厚度的变化来实现。也即在测试硅片中采用ISSG、DPN和PNA形成栅氧化层后,对栅氧化层进行厚度测量,然后根据栅氧化层的厚度的变化来对PNA温度波动进行监控,由于厚度是垂直于测试硅片的表面,故厚度为Z方向值。
但是,PNA温度波动也会在二维平面上对栅氧化层产生影响,现有技术中无法实现PNA温度波动在二维平面上对栅氧化层的影响。
发明内容
本发明所要解决的技术问题是提供一种栅氧掺氮退火温度的监控方法,能监控栅氧掺氮退火温度在二维平面上对栅氧化层的影响,并进而能调节栅氧掺氮退火温度并提高产品良率。
为解决上述技术问题,本发明提供的栅氧掺氮退火温度的监控方法包括如下步骤:
步骤一、在测试硅片上形成零标记层图形。
步骤二、在形成有所述零标记层图形的所述测试硅片表面上形成氮掺杂的栅氧化层,所述栅氧化层的形成工艺包括:氧化层生长工艺,对所述氧化层进行掺氮工艺,进行栅氧掺氮退火工艺。
步骤三、在所述栅氧化层表面上形成套刻层图形,所述套刻层图形和对应的所述零标记层图形相套准(OVL)形成监控结构,所述监控结构中所述套刻层图形和对应的所述零标记层图形之间的套准值为沿和所述测试硅片的表面平行的X方向值和Y方向值。
步骤四、测量所述测试硅片上各所述监控结构的所述套刻层图形和对应的所述零标记层图形之间的套准值,根据所测量的所述套准值调整所述栅氧掺氮退火温度。
进一步的改进是,步骤一中采用如下步骤形成所述零标记层图形:
步骤11、在所述测试硅片表面形成硬质掩模层。
步骤12、在所述硬质掩模层表面涂布零标记层光刻胶并对所述零标记层光刻胶进行曝光和显影。
步骤13、以显影后的所述零标记层光刻胶为掩模依次对所述硬质掩模层和所述测试硅片进行刻蚀形成沟槽;之后去除所述零标记层光刻胶。
步骤14、在所述沟槽中填充第一介质层,由填充于所述沟槽中的所述第一介质层组成所述零标记层图形。
进一步的改进是,步骤14中在生长所述第一介质层填充所述沟槽的同时,所述第一介质层还会延伸到所述沟槽外的所述硬质掩模层表面。
之后还包括采用以所述硬质掩模层为终点的化学机械研磨工艺对所述第一介质层进行研磨的步骤,化学机械研磨工艺后所述沟槽外的所述第一介质层被去除。
之后还包括去除所述硬质掩模层的步骤。
进一步的改进是,步骤11中所述硬质掩模层的材料为氮化硅。采用所述化学气相沉积或炉管工艺形成所述硬质掩模层;所述硬质掩模层的厚度为
Figure BDA0002141425780000031
进一步的改进是,步骤12中零标记层光刻胶的厚度为
Figure BDA0002141425780000032
进一步的改进是,步骤13中所述沟槽的深度为
Figure BDA0002141425780000033
进一步的改进是,步骤13中采用等离子刻蚀工艺对所述硬质掩模层和所述测试硅片进行刻蚀形成所述沟槽;采用湿法刻蚀工艺同时去除所述零标记层光刻胶以及所述沟槽的等离子刻蚀工艺的刻蚀残余物。
进一步的改进是,所述第一介质层的材料为氧化物。
进一步的改进是,所述第一介质层采用高密度等离子工艺或者采用高纵横比工艺生长,所述第一介质层的厚度为
Figure BDA0002141425780000034
所述第一介质层生长完成后还包括对所述第一介质层进行退火的步骤,所述第一介质层的退火采用炉管退火或快速热退火;所述第一介质层的退火的温度为1000℃。
进一步的改进是,步骤二的所述栅氧化层的形成工艺中:
采用原位水汽生成工艺进行所述氧化层生长。
采用去耦等离子氮化工艺对所述氧化层进行掺氮工艺。
进一步的改进是,步骤三中采用涂布套刻层光刻胶并对所述套刻层光刻胶进行曝光和显影形成由显影后的所述套刻层光刻胶组成的套刻层图形。
进一步的改进是,所述套刻层光刻胶的厚度为
Figure BDA0002141425780000041
进一步的改进是,所述零标记层图形的俯视面结构为条形结构,所述零标记层图形的条形结构的长度为12微米~16微米,宽度为1微米~4微米。
所述套刻层图形的俯视面结构为条形结构,所述套刻层图形的条形结构的长度为8微米~12微米,宽度为1微米~4微米。
一个所述监控结构中包括多个所述零标记层图形以及多个所述套刻层图形,多个所述零标记层图形环绕在多个所述套刻层图形的外周,多个所述套刻层图形也排列成环形结构。
进一步的改进是,一个所述监控结构中包括4个所述零标记层图形以及4个所述套刻层图形,4个所述套刻层图形排列成正方形的环形结构;4个所述零标记层图形排列成环绕在多个所述套刻层图形的外周的正方形的环形结构。
进一步的改进是,在所述测试硅片的中心区域和四周都分布有所述监控结构。
本发明为了实现对栅氧掺氮退火温度在二维平面上对栅氧化层的影响的监控,对的监控方法进行了有针对性的设置,和现有技术中直接在测试硅片上形成栅氧化层然后再测试栅氧化层的厚度来进行栅氧掺氮退火温度的监控不同,本发明方法先在测试硅片上形成零标记层图形,之后再形成掺氮的栅氧化层,之后再形成一层套刻层图形,由套刻层图形和对应的零标记层图形相套准形成监控结构,由于监控结构中的套刻层图形和对应的零标记层图形之间的套准值为沿和测试硅片的表面平行的X方向值和Y方向值,故最后对监控结构的套刻层图形和对应的零标记层图形之间的套准值进行测量就能监控栅氧掺氮退火温度在二维平面上对栅氧化层的影响,并从而能根据所测量的套准值调整栅氧掺氮退火温度,并最后能改善产品的套准精度,从而能提高产品良率。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明:
图1是本发明实施例栅氧掺氮退火温度的监控方法的流程图;
图2A-图2J是本发明实施例方法各步骤中的器件结构图。
具体实施方式
如图1所示,是本发明实施例栅氧掺氮退火温度的监控方法的流程图;如图2A至图2J所示,是本发明实施例方法各步骤中的器件结构图,本发明实施例栅氧掺氮退火温度的监控方法包括如下步骤:
步骤一、在测试硅片1上形成零标记层图形2。
本发明实施例中,采用如下步骤形成所述零标记层图形2:
步骤11、如图2A所示,在所述测试硅片1表面形成硬质掩模层101。
所述硬质掩模层101的材料为氮化硅。采用所述化学气相沉积或炉管工艺形成所述硬质掩模层101;所述硬质掩模层101的厚度为
Figure BDA0002141425780000051
步骤12、如图2A所示,在所述硬质掩模层101表面涂布零标记层光刻胶102。
如图2B所示,对所述零标记层光刻胶102进行曝光和显影,显影后所述零标记层光刻胶102的打开区域103即为所述零标记层图形2的形成区域。
所述零标记层光刻胶102的厚度为
Figure BDA0002141425780000052
步骤13、如图2C所示,以显影后的所述零标记层光刻胶102为掩模依次对所述硬质掩模层101和所述测试硅片1进行刻蚀形成沟槽104;之后去除所述零标记层光刻胶102。
所述沟槽104的深度为
Figure BDA0002141425780000053
采用等离子刻蚀工艺对所述硬质掩模层101和所述测试硅片1进行刻蚀形成所述沟槽104;采用湿法刻蚀工艺同时去除所述零标记层光刻胶102以及所述沟槽104的等离子刻蚀工艺的刻蚀残余物。
步骤14、在所述沟槽104中填充第一介质层2,由填充于所述沟槽104中的所述第一介质层2组成所述零标记层图形2。
如图2D所示,在生长所述第一介质层2填充所述沟槽104的同时,所述第一介质层2还会延伸到所述沟槽104外的所述硬质掩模层101表面。
较佳选择为,所述第一介质层2的材料为氧化物。所述第一介质层2采用高密度等离子工艺或者采用高纵横比工艺生长,所述第一介质层2的厚度为
Figure BDA0002141425780000054
所述第一介质层2生长完成后还包括对所述第一介质层2进行退火的步骤,所述第一介质层2的退火采用炉管退火或快速热退火;所述第一介质层2的退火的温度为1000℃。
如图2E所示,之后还包括采用以所述硬质掩模层101为终点的化学机械研磨工艺对所述第一介质层2进行研磨的步骤,化学机械研磨工艺后所述沟槽104外的所述第一介质层2被去除。
之后还包括去除所述硬质掩模层101的步骤。去除所述硬质掩模层101的步骤包括:先用氢氟酸对所述硬质掩模层101表面进行处理,以去除可能残留在所述硬质掩模层101表面的氧化层;之后采用磷酸去除所述硬质掩模层。
步骤二、在形成有所述零标记层图形的所述测试硅片1表面上形成氮掺杂的栅氧化层3,所述栅氧化层3的形成工艺包括:
氧化层生长工艺,本发明实施例中,采用原位水汽生成工艺进行所述氧化层生长。
对所述氧化层进行掺氮工艺,本发明实施例中,采用去耦等离子氮化工艺对所述氧化层进行掺氮工艺。
进行栅氧掺氮退火工艺。
步骤三、在所述栅氧化层3表面上形成套刻层图形4,所述套刻层图形4和对应的所述零标记层图形2相套准形成监控结构5,所述监控结构5中所述套刻层图形4和对应的所述零标记层图形2之间的套准值为沿和所述测试硅片1的表面平行的X方向值和Y方向值。
本发明实施例中,形成套刻层图形4的步骤包括:如图2H所示,涂布套刻层光刻胶105;如图2I所示,对所述套刻层光刻胶105进行曝光和显影形成由显影后的所述套刻层光刻胶105组成的套刻层图形4。
所述套刻层光刻胶105的厚度为
Figure BDA0002141425780000061
如图2J所示,所述零标记层图形2的俯视面结构为条形结构,所述零标记层图形2的条形结构的长度为12微米~16微米,宽度为1微米~4微米。
所述套刻层图形4的俯视面结构为条形结构,所述套刻层图形4的条形结构的长度为8微米~12微米,宽度为1微米~4微米。
一个所述监控结构5中包括多个所述零标记层图形2以及多个所述套刻层图形4,多个所述零标记层图形2环绕在多个所述套刻层图形4的外周,多个所述套刻层图形4也排列成环形结构。图2J中,一个所述监控结构5中包括4个所述零标记层图形2以及4个所述套刻层图形4,4个所述套刻层图形4排列成正方形的环形结构;4个所述零标记层图形2排列成环绕在多个所述套刻层图形4的外周的正方形的环形结构。
在所述测试硅片1的中心区域和四周都分布有所述监控结构5,这样能够实现对所述测试硅片1的表面各区域进行监控。
步骤四、测量所述测试硅片1上各所述监控结构5的所述套刻层图形4和对应的所述零标记层图形2之间的套准值,根据所测量的所述套准值调整所述栅氧掺氮退火温度。
本发明实施例为了实现对栅氧掺氮退火温度在二维平面上对栅氧化层3的影响的监控,对的监控方法进行了有针对性的设置,和现有技术中直接在测试硅片1上形成栅氧化层3然后再测试栅氧化层3的厚度来进行栅氧掺氮退火温度的监控不同,本发明实施例方法先在测试硅片1上形成零标记层图形2,之后再形成掺氮的栅氧化层3,之后再形成一层套刻层图形4,由套刻层图形4和对应的零标记层图形2相套准形成监控结构5,由于监控结构5中的套刻层图形4和对应的零标记层图形2之间的套准值为沿和测试硅片1的表面平行的X方向值和Y方向值,故最后对监控结构5的套刻层图形4和对应的零标记层图形2之间的套准值进行测量就能监控栅氧掺氮退火温度在二维平面上对栅氧化层3的影响,并从而能根据所测量的套准值调整栅氧掺氮退火温度,并最后能改善产品的套准精度,从而能提高产品良率。
以上通过具体实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。

Claims (13)

1.一种栅氧掺氮退火温度的监控方法,其特征在于,包括如下步骤:
步骤一、在测试硅片上形成零标记层图形;
步骤一中采用如下步骤形成所述零标记层图形:
步骤11、在所述测试硅片表面形成硬质掩模层;
步骤12、在所述硬质掩模层表面涂布零标记层光刻胶并对所述零标记层光刻胶进行曝光和显影;
步骤13、以显影后的所述零标记层光刻胶为掩模依次对所述硬质掩模层和所述测试硅片进行刻蚀形成沟槽;之后去除所述零标记层光刻胶;
步骤14、在所述沟槽中填充第一介质层,由填充于所述沟槽中的所述第一介质层组成所述零标记层图形;
步骤14中在生长所述第一介质层填充所述沟槽的同时,所述第一介质层还会延伸到所述沟槽外的所述硬质掩模层表面;
之后还包括采用以所述硬质掩模层为终点的化学机械研磨工艺对所述第一介质层进行研磨的步骤,化学机械研磨工艺后所述沟槽外的所述第一介质层被去除;
之后还包括去除所述硬质掩模层的步骤;
所述零标记层图形的顶部会突出到所述测试硅片表面之上;
步骤二、在形成有所述零标记层图形的所述测试硅片表面上形成氮掺杂的栅氧化层,所述栅氧化层的形成工艺包括:氧化层生长工艺,对所述氧化层进行掺氮工艺,进行栅氧掺氮退火工艺;
突出到所述测试硅片表面之上的所述零标记层图形的侧面会和所述栅氧化层接触,所述栅氧化层的沿和所述测试硅片平行的X方向尺寸和Y方向尺寸会对所述零标记层图形产生影响;
步骤三、在所述栅氧化层表面上形成套刻层图形,所述套刻层图形和对应的所述零标记层图形相套准形成监控结构,所述监控结构中所述套刻层图形和对应的所述零标记层图形之间的套准值为沿和所述测试硅片的表面平行的X方向值和Y方向值;
步骤四、测量所述测试硅片上各所述监控结构的所述套刻层图形和对应的所述零标记层图形之间的套准值,根据所测量的所述套准值调整所述栅氧掺氮退火温度。
2.如权利要求1所述的栅氧掺氮退火温度的监控方法,其特征在于:步骤11中所述硬质掩模层的材料为氮化硅;采用化学气相沉积或炉管工艺形成所述硬质掩模层;所述硬质掩模层的厚度为
Figure FDA0003425656840000021
3.如权利要求1所述的栅氧掺氮退火温度的监控方法,其特征在于:步骤12中零标记层光刻胶的厚度为
Figure FDA0003425656840000022
4.如权利要求1所述的栅氧掺氮退火温度的监控方法,其特征在于:步骤13中所述沟槽的深度为
Figure FDA0003425656840000023
5.如权利要求1所述的栅氧掺氮退火温度的监控方法,其特征在于:步骤13中采用等离子刻蚀工艺对所述硬质掩模层和所述测试硅片进行刻蚀形成所述沟槽;采用湿法刻蚀工艺同时去除所述零标记层光刻胶以及所述沟槽的等离子刻蚀工艺的刻蚀残余物。
6.如权利要求2所述的栅氧掺氮退火温度的监控方法,其特征在于:所述第一介质层的材料为氧化物。
7.如权利要求6所述的栅氧掺氮退火温度的监控方法,其特征在于:所述第一介质层采用高密度等离子工艺或者采用高纵横比工艺生长,所述第一介质层的厚度为
Figure FDA0003425656840000024
所述第一介质层生长完成后还包括对所述第一介质层进行退火的步骤,所述第一介质层的退火采用炉管退火或快速热退火;所述第一介质层的退火的温度为1000℃。
8.如权利要求1所述的栅氧掺氮退火温度的监控方法,其特征在于:步骤二的所述栅氧化层的形成工艺中:
采用原位水汽生成工艺进行所述氧化层生长;
采用去耦等离子氮化工艺对所述氧化层进行掺氮工艺。
9.如权利要求1所述的栅氧掺氮退火温度的监控方法,其特征在于:步骤三中采用涂布套刻层光刻胶并对所述套刻层光刻胶进行曝光和显影形成由显影后的所述套刻层光刻胶组成的套刻层图形。
10.如权利要求9所述的栅氧掺氮退火温度的监控方法,其特征在于:所述套刻层光刻胶的厚度为
Figure FDA0003425656840000025
11.如权利要求1所述的栅氧掺氮退火温度的监控方法,其特征在于:所述零标记层图形的俯视面结构为条形结构,所述零标记层图形的条形结构的长度为12微米~16微米,宽度为1微米~4微米;
所述套刻层图形的俯视面结构为条形结构,所述套刻层图形的条形结构的长度为8微米~12微米,宽度为1微米~4微米;
一个所述监控结构中包括多个所述零标记层图形以及多个所述套刻层图形,多个所述零标记层图形环绕在多个所述套刻层图形的外周,多个所述套刻层图形也排列成环形结构。
12.如权利要求11所述的栅氧掺氮退火温度的监控方法,其特征在于:一个所述监控结构中包括4个所述零标记层图形以及4个所述套刻层图形,4个所述套刻层图形排列成正方形的环形结构;4个所述零标记层图形排列成环绕在多个所述套刻层图形的外周的正方形的环形结构。
13.如权利要求1或11或12所述的栅氧掺氮退火温度的监控方法,其特征在于:在所述测试硅片的中心区域和四周都分布有所述监控结构。
CN201910670110.1A 2019-07-24 2019-07-24 栅氧掺氮退火温度的监控方法 Active CN110364449B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201910670110.1A CN110364449B (zh) 2019-07-24 2019-07-24 栅氧掺氮退火温度的监控方法
US16/702,924 US10978360B2 (en) 2019-07-24 2019-12-04 PNA temperature monitoring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910670110.1A CN110364449B (zh) 2019-07-24 2019-07-24 栅氧掺氮退火温度的监控方法

Publications (2)

Publication Number Publication Date
CN110364449A CN110364449A (zh) 2019-10-22
CN110364449B true CN110364449B (zh) 2022-06-14

Family

ID=68220814

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910670110.1A Active CN110364449B (zh) 2019-07-24 2019-07-24 栅氧掺氮退火温度的监控方法

Country Status (2)

Country Link
US (1) US10978360B2 (zh)
CN (1) CN110364449B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113013236A (zh) * 2021-02-22 2021-06-22 上海华力集成电路制造有限公司 氮掺杂栅氧化层的形成工艺的监控方法
CN113223979B (zh) * 2021-04-28 2023-08-22 上海华虹宏力半导体制造有限公司 栅氧化层工艺中的厚度补偿方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101593744A (zh) * 2008-05-29 2009-12-02 中芯国际集成电路制造(北京)有限公司 套刻对准标记及其制作方法
CN102738121A (zh) * 2011-04-08 2012-10-17 中芯国际集成电路制造(上海)有限公司 一种套刻偏差检查标记及其制作方法
CN103901729A (zh) * 2012-12-24 2014-07-02 上海华虹宏力半导体制造有限公司 改善套刻精度面内均匀性的方法
CN105223781A (zh) * 2014-06-26 2016-01-06 无锡华润上华科技有限公司 一种步进式光刻机对位监控方法
CN108089412A (zh) * 2017-11-10 2018-05-29 上海华力微电子有限公司 光刻套刻精度量测准确性的评估方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7425396B2 (en) * 2003-09-30 2008-09-16 Infineon Technologies Ag Method for reducing an overlay error and measurement mark for carrying out the same
US7192845B2 (en) * 2004-06-08 2007-03-20 Macronix International Co., Ltd. Method of reducing alignment measurement errors between device layers
US7151042B2 (en) * 2005-02-02 2006-12-19 Macronix International Co., Ltd. Method of improving flash memory performance
CN101435997B (zh) * 2007-11-15 2012-06-27 上海华虹Nec电子有限公司 光刻套刻精度的测试图形及测量方法
US8441078B2 (en) * 2010-02-23 2013-05-14 Texas Instruments Incorporated Semiconductor device including SiON gate dielectric with portions having different nitrogen concentrations
US8450221B2 (en) * 2010-08-04 2013-05-28 Texas Instruments Incorporated Method of forming MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls
CN104281020A (zh) * 2013-07-08 2015-01-14 无锡华润上华科技有限公司 一种改善光刻对位能力的方法
CN104810302B (zh) * 2014-01-23 2018-12-25 北大方正集团有限公司 一种监控晶圆的使用方法
CN104465619B (zh) * 2014-04-22 2018-09-04 上海华力微电子有限公司 一种套刻精度测量的图像结构及其套刻精度测量方法
CN105206547B (zh) * 2015-09-28 2018-05-01 上海集成电路研发中心有限公司 一种测量双重图像套刻精度的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101593744A (zh) * 2008-05-29 2009-12-02 中芯国际集成电路制造(北京)有限公司 套刻对准标记及其制作方法
CN102738121A (zh) * 2011-04-08 2012-10-17 中芯国际集成电路制造(上海)有限公司 一种套刻偏差检查标记及其制作方法
CN103901729A (zh) * 2012-12-24 2014-07-02 上海华虹宏力半导体制造有限公司 改善套刻精度面内均匀性的方法
CN105223781A (zh) * 2014-06-26 2016-01-06 无锡华润上华科技有限公司 一种步进式光刻机对位监控方法
CN108089412A (zh) * 2017-11-10 2018-05-29 上海华力微电子有限公司 光刻套刻精度量测准确性的评估方法

Also Published As

Publication number Publication date
CN110364449A (zh) 2019-10-22
US20210028072A1 (en) 2021-01-28
US10978360B2 (en) 2021-04-13

Similar Documents

Publication Publication Date Title
CN110364449B (zh) 栅氧掺氮退火温度的监控方法
JP2001332614A (ja) トレンチ型素子分離構造の製造方法
KR100740159B1 (ko) 반도체 장치의 평가방법, 반도체 장치의 제조 방법, 및 반도체 웨이퍼
TWI520266B (zh) 晶圓,形成測試結構之方法及半導體結構之製作方法
CN113013236A (zh) 氮掺杂栅氧化层的形成工艺的监控方法
US6859023B2 (en) Evaluation method for evaluating insulating film, evaluation device therefor and method for manufacturing evaluation device
KR100668509B1 (ko) 비대칭 스텝구조의 게이트를 갖는 반도체소자의 제조 방법
CN109065465B (zh) 浅沟槽隔离台阶高度稳定性测量方法
US9136127B2 (en) Method of fabricating GOI silicon wafer, GOI silicon wafer and GOI detection method
US6617258B1 (en) Method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and system for accomplishing same
JP3719670B2 (ja) 絶縁膜の評価方法、その評価装置及びその評価装置の製造方法
JP2008147461A (ja) 半導体基板の評価方法および半導体基板評価用素子
US11942359B2 (en) Reduced semiconductor wafer bow and warpage
US6329249B1 (en) Method for fabricating a semiconductor device having different gate oxide layers
KR0172047B1 (ko) 반도체 소자의 제조방법
KR100233264B1 (ko) 아날로그 반도체소자 제조방법
KR100334390B1 (ko) 이중 게이트산화막 형성방법
KR100219416B1 (ko) 반도체장치 제조방법
KR100238203B1 (ko) 열산화를 이용한 질화막의 질소 농도 측정방법
US9722045B2 (en) Buffer layer for modulating Vt across devices
US20050202680A1 (en) Method for shrinking a dimension of a gate
KR960009096B1 (ko) 반도체 소자의 필드 산화막 제조방법
CN117153687A (zh) SiC外延片、SiC器件及提高SiC器件可靠性的方法
JP5333483B2 (ja) 半導体ウェーハ、及びその製造方法
CN117711929A (zh) 一种沟槽器件终端及其栅极结构制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant