CN110349945A - 一种多芯片的封装结构及其封装方法 - Google Patents
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Abstract
本发明公开了一种多芯片的封装结构及其封装方法,属于半导体芯片封装技术领域。其扇出型芯片封装单元设置的芯片(1)为两个或两个以上,芯片(1)彼此间仅留毛细间隙(2),所述芯片(1)彼此间于再布线层(6)的上表面设置毛细封堵部件(3),毛细封堵部件(3)完全填充毛细间隙(2)的下部,所述塑封料(4)与毛细封堵部件(3)密接。本发明提供了解决芯片开裂、产品翘曲等问题的多芯片的封装结构及其封装方法,提高了产品的良率。
Description
技术领域
本发明涉及一种多芯片的封装结构及其封装方法,属于半导体封装技术领域。
背景技术
受电子产品小、轻、薄的驱动,市场对单颗芯片的功能要求越来越高,当芯片的功能不能满足客户的需求时,就需要设计公司对芯片重新设计,如此,不仅设计成本高、周期长,且需要不断优化,这与发展迅速的信息化、电子化进程显然不符。鉴于此,多芯片的封装方式应运而生。扇出型(Fan-out)晶圆封装作为新型封装技术,在应用于多芯片封装时,不仅满足了客户对产品高性能的需求,且实现了集成电路小型化的目的。但是,这种封装方式也存在一定的弊端,由于芯片平铺分布,为了达到产品小型化的目的,芯片间距需尽可能的小,而当两芯片间距足够近时,因“毛细效应”的发生,会使芯片底部的填充胶“爬升”至两芯片之间,由于底部填充胶的热膨胀系数较大,在后续工序中,受热膨胀的胶体会挤压芯片,出现芯片开裂与产品翘曲等问题,这些问题严重影响了产品的良率。
发明内容
本发明的目的在于克服现有技术中存在的不足,提供一种解决在封装过程中出现的芯片开裂与产品翘曲等问题的多芯片的封装结构及其封装方法。
本发明的目的是这样实现的:
本发明提供了一种多芯片的封装结构,其包括扇出型芯片封装单元、基板及其焊球,所述扇出型芯片封装单元设置在基板的上表面,所述焊球设置在基板的下表面,
所述扇出型芯片封装单元设置的芯片为两个或两个以上,平铺分布,且彼此紧靠,芯片彼此间仅留毛细间隙,所述毛细间隙的宽度范围在50-300微米,芯片的正面通过金属凸块Ⅰ倒装于再布线层的上表面,所述芯片彼此间于再布线层的上表面设置毛细封堵部件,毛细封堵部件完全填充毛细间隙的下部,其横向长度不小于毛细间隙的横向长度,其高度大于芯片的下表面至再布线层的上表面之间的间距,芯片与再布线层之间设置底填料Ⅰ;
还包括塑封料,所述塑封料覆盖再布线层上的所有芯片,并填充毛细间隙,所述塑封料与毛细封堵部件密接,扇出型芯片封装单元的下表面即再布线层的下表面设有金属凸块Ⅱ,扇出型芯片封装单元通过金属凸块Ⅱ与基板的上表面固连;扇出型芯片封装单元与基板之间设置底填料Ⅱ。
可选地,所述毛细封堵部件的纵截面呈⊥状。
可选地,还包括点胶道粗糙面,所述点胶道粗糙面设置于再布线层的上表面,被所述毛细封堵部件覆盖,其粗糙化图形呈点状或线状。
本发明提供了一种多芯片的封装结构的封装方法,其实施步骤如下:
步骤一、提供一载体,在载体上涂覆一层临时键合材料,并在此载体上构建下述扇出型芯片封装单元;
步骤二、在临时键合材料上设置再布线层,并在再布线层的上表面规划点胶道,所述再布线层的层数根据实际需要设置;所述点胶道设置于相邻两芯片的芯片贴装区域之间,其宽度不小于芯片之间的毛细间隙的宽度;
步骤三、点胶道粗糙化工艺,使点胶道上的再布线层最外层的绝缘层的表层形成点胶道粗糙面;
步骤四、使用点胶机,通过调试胶头的大小与控制胶量,在再布线层的点胶道上涂覆形成毛细封堵部件的原料,所述原料的高度大于芯片的上表面至再布线层6的上表面之间的间距,其初始宽度大于芯片之间的毛细间隙的宽度;
步骤五、使用自动芯片贴装机器,利用橡胶吸头将芯片从切割好的晶圆上吸取,再通过吸头的压力控制作用将芯片倒装贴装到再布线层图案层上,最后通过回流焊工艺,完成芯片与再布线层的焊接;要求芯片贴装位置控制在贴装区域+/-15um之内,贴片旋转角度需小于1.5度;设定程序后,多个芯片平铺设置,由机器控制毛细间隙的宽度范围为50微米-300微米,将进入毛细间隙的毛细封堵部件的原料的初始宽度进行挤压成型,使芯片与毛细封堵部件密接;
步骤六、所述毛细封堵部件固化塑型;
步骤七、芯片底部填充底填料Ⅰ,并进行固化烘烤;
步骤八、塑封料在高温模槽里预热后成液态,将上述封装结构倒置于模槽内,在真空负压下,塑封料通过注塑压力从毛细间隙的一端有规律地填充到毛细间隙的另一端,使毛细间隙内的空气在真空负压作用下驱赶干净,塑封料覆盖再布线层上的所有芯片,在流动过程中,塑封料与毛细封堵部件密接;
步骤九、由于临时键合材料可通过热或光作用使材料失去粘性,通过热滑动剥离、机械剥离或紫外激光剥离等技术移除载体,露出再布线层的下表面,即完成了扇出型晶圆级封装结构的封装工艺;
步骤十、在所述扇出型晶圆级封装结构的再布线层底部生长金属凸块Ⅱ;
步骤十一、将所述扇出型晶圆级封装结构切割分离成扇出型芯片封装单元;
步骤十二、将所述芯片扇出单元单体通过金属凸块Ⅱ倒装于基板上,并填充底填料Ⅱ,烘烤使底填料Ⅱ固化;
步骤十三、基板底部植焊球。
可选地,步骤三中,所述点胶道粗糙化工艺采用等离子蚀刻工艺,借助刻有镂空图案的掩模治具完成,其形成的点胶道粗糙面的表面粗糙度Ra为0.2~1.0微米。
可选地,步骤三中,所述点胶道粗糙化工艺采用激光刻蚀工艺实现,其粗糙化图形呈点状或线状,形成的点胶道粗糙面的表面粗糙度Ra为0.2~3.0微米。
可选地,步骤四中,所述毛细封堵部件的原料通过网板印刷工艺设置在再布线层的点胶道上。
可选地,步骤四中,所述毛细封堵部件的原料的主要成分为树脂和二氧化硅,其中,二氧化硅占比为50-90%,其粘度(25℃)为20-60 Pa.S.。
可选地,所述塑封料的热膨胀系数远小于底填料Ⅰ的热膨胀系数。
有益效果
本发明提供了一种多芯片的封装结构及其封装方法,其设置毛细封堵部件后,使底部填充胶不能“爬升”至两芯片中间的毛细间隙,而由塑封料填补该毛细间隙,由于塑封料的热膨胀系数较小,所以能够显著改善芯片开裂与产品翘曲等现象,提高产品的良率。
附图说明
图1为本发明一种多芯片的封装结构的示意图;
其中,
芯片1
毛细间隙2
毛细封堵部件3
塑封料4
底填料Ⅰ5
再布线层6
金属凸块Ⅱ7
底填料Ⅱ8
金属凸块Ⅰ9
基板12
焊球13。
具体实施方式
下面结合附图对本发明的具体实施方式进行详细说明。为了易于说明,可以使用空间相对术语(诸如“在…下方”、“之下”、“下部”、“在…上方”、“上部”等)以描述图中所示一个元件或部件与另一个元件或部件的关系。除图中所示的定向之外,空间相对术语还包括使用或操作中设备的不同定向。装置可以以其他方式定向(旋转90度或处于其他定向),本文所使用的空间相对描述可因此进行类似的解释。
本发明一种多芯片的封装结构,如图1所示,其包括扇出型芯片封装单元、基板12及其焊球13,其中,扇出型芯片封装单元设置在基板12的上表面,所述焊球13设置在基板12的下表面。扇出型芯片封装单元设置的芯片1为两个或两个以上,平铺分布,且彼此紧靠,芯片1彼此间形成宽度范围为50-300微米的毛细间隙2。芯片1的正面通过其下的金属凸块Ⅰ9倒装于再布线层6的上表面。金属凸块Ⅰ9的上下两端均设有焊料,其上端与芯片1的正面焊盘连接,其下端与再布线层6的上表面焊盘连接。芯片1彼此间于再布线层6的上表面设置毛细封堵部件2,其材质主要为树脂和二氧化硅,其中,二氧化硅占比为50-90%,且未固化前具有极低的流动性,毛细封堵部件2可完全填充毛细间隙2的下部,固化后,毛细封堵部件3的纵截面呈⊥状,其横向长度不小于毛细间隙2的横向长度,其高度大于芯片1的下表面至再布线层6的上表面之间的间距。为增强了毛细封堵部件3与再布线层6的结合力,可以在再布线层6的上表面设置点胶道粗糙面,其粗糙化图形呈点状或线状,但被毛细封堵部件3覆盖,不可见。
芯片1与再布线层6之间设置底填料Ⅰ5,其材质为底部填充胶,底填料Ⅰ5进一步巩固了芯片1与再布线层6之间的连接。由于毛细封堵部件2的存在,底填料Ⅰ5无法进入芯片1彼此间的毛细间隙2。塑封料4覆盖再布线金属层6上的所有芯片1,塑封料4在塑封过程中,受真空负压与注塑压力的作用向下填充毛细间隙2,从而与毛细封堵部件3密接。扇出型芯片封装单元的下表面即再布线层6的下表面设有金属凸块Ⅱ7,扇出型芯片封装单元通过金属凸块Ⅱ7与基板12的上表面固连。金属凸块Ⅱ7的上下两端均设有焊料,其上端与芯片扇出单元的下表面焊盘连接,其下端与基板12的上表面焊盘连接。底填料Ⅱ8设置于金属凸块Ⅱ7与基板12上表面之间,进一步增强芯片扇出单元与基板12的连接强度。基板12下表面设置焊球13。
本发明一种多芯片的封装结构的封装方法,其实施步骤如下:
步骤一、提供一载体,在载体上涂覆一层临时键合材料,并在临时键合材料上构建下述扇出型晶圆级封装结构。载体材质优选玻璃。
步骤二、在临时键合材料上设置再布线层6,并在再布线层6的上表面规划点胶道位置。再布线层6由至少一层绝缘介电层和至少一层再布线金属图形层构成,多层绝缘介电层和多层再布线金属图形层交叉层层交错设置,可以形成两层或两层以上的多层再布线金属图形层,再布线金属图形层彼此之间存在选择性电性连接,介电材料包裹再布线金属图形层和/或填充于相邻的再布线金属图形层之间形成绝缘介电层。再布线层6的层数根据实际需要设置,并加厚再布线层6最外层的绝缘介电层。在再布线层6的上表面,点胶道设置于相邻两芯片1的芯片贴装区域之间,其宽度不小于芯片1之间的毛细间隙2的宽度。
步骤三、点胶道粗糙化工艺。通过等离子蚀刻工艺,借助刻有镂空图案的掩模治具使点胶道上的再布线层6最外层的绝缘介电层的表层形成点胶道粗糙面,其表面粗糙度Ra为0.2~1.0微米,掩模治具上的镂空图案仅露出点胶道的上方空间;
或者通过激光刻蚀工艺,使点胶道上的再布线层6最外层的绝缘介电层的表层形成点胶道粗糙面,其表面粗糙度Ra为0.2~3.0微米。激光蚀刻形成的点胶道粗糙面的粗糙化图形可以是点状或线状。点胶道经过粗糙化工艺后,可以使后续工艺中的毛细封堵部件3的原料易于定位,也易于定型,增强了其与再布线层6的结合力。
步骤四、使用点胶机,通过调试胶头的大小与控制胶量,在再布线层6的点胶道上涂覆形成毛细封堵部件2的原料,毛细封堵部件2的原料的主要成分为树脂和二氧化硅,其粘度(25℃)为20-60 Pa.S.,其中,二氧化硅占比为50-90%,其可以降低毛细封堵部件的热膨胀性与流动性,并提高其导热性能。常温下,毛细封堵部件2的原料具有极低的流动性,要求成型的毛细封堵部件2的高度大于芯片1的上表面至再布线层6的上表面之间的间距,毛细封堵部件3的初始宽度大于芯片1之间的毛细间隙2的宽度。毛细封堵部件3的原料也可以通过网板印刷工艺在再布线层6的点胶道上设置,制作效率会更高些。
步骤五、装贴芯片1;使用自动芯片1贴装机器,利用橡胶吸头将芯片1从切割好的晶圆上吸取,再通过吸头的压力控制作用将芯片1倒装贴装到再布线层6的芯片贴装区域上,最后通过回流焊工艺,完成芯片1与再布线层6的焊接;要求芯片1贴装位置控制在芯片贴装区域+/-15um之内,贴片旋转角度需小于1.5度。设定程序后,多个芯片1平铺设置,由机器控制毛细间隙2的宽度范围为50-300微米,将进入毛细间隙2的毛细封堵部件2的初始宽度进行挤压成型,使芯片1与毛细封堵部件2密接。在芯片贴装过程中,所有芯片均按行列整齐排布,其毛细间隙2的方向一致。
步骤六、毛细封堵部件3固化塑型。毛细封堵部件3的固化方式可选光固化或热固化。
步骤七、芯片1底部填充底填料Ⅰ5,并进行烘烤固化。底填料Ⅰ5的热膨胀系数为30-50ppm/℃,由于毛细封堵部件2的阻挡,底填料Ⅰ5无法渗至芯片1之间的毛细间隙2内。
步骤八、晶圆级塑封。塑封料4在高温模槽里预热后成液态,将上述封装结构倒置于模槽内,在真空负压下,塑封料4通过注塑压力从毛细间隙2的一端有规律地填充到毛细间隙2的另一端,使毛细间隙2内的空气在真空负压作用下驱赶干净,塑封料4覆盖再布线层6上的所有芯片1,在流动过程中,塑封料4与毛细封堵部件3密接。塑封料4的热膨胀系数为5-10ppm/℃。
步骤九、由于临时键合材料可通过热或光作用使材料失去粘性,通过热滑动剥离、机械剥离或紫外激光剥离等技术移除载体,露出再布线层6的下表面,即完成了扇出型晶圆级封装结构的封装工艺。
步骤十、在扇出型晶圆级封装结构的再布线层6底部生长金属凸块Ⅱ7。
步骤十一、将扇出型晶圆级封装结构切割分离成扇出型芯片封装单元;
步骤十二、将所述扇出型芯片封装单元通过金属凸块Ⅱ7倒装于基板12上,并填充底填料Ⅱ8,烘烤使底填料Ⅱ8完全固化。
步骤十三、基板12底部植焊球13。
本发明通过设置毛细封堵部件3,底填料Ⅰ5不能“爬升”至芯片1中间的毛细间隙2,而由塑封料4填补该毛细间隙2,由于塑封料4的热膨胀系数比底填料Ⅰ5的热膨胀系数小很多(塑封料4的热膨胀系数为 5-10 ppm/℃,底填料Ⅰ5的热膨胀系数为30-50ppm/℃),所以能显著改善芯片1的开裂与扇出型芯片封装单元的翘曲等现象。
以上所述的具体实施方式,对本发明的目的、技术方案和有益效果进行了进一步地详细说明,所应理解的是,以上所述仅为本发明的具体实施方式而已,并不用于限定本发明的保护范围。凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (9)
1.一种多芯片的封装结构,其包括扇出型芯片封装单元、基板(12)及其焊球(13),所述扇出型芯片封装单元设置在基板(12)的上表面,所述焊球(13)设置在基板(12)的下表面,
其特征在于,所述扇出型芯片封装单元设置的芯片(1)为两个或两个以上,平铺分布,且彼此紧靠,芯片(1)彼此间仅留毛细间隙(2),所述毛细间隙(2)的宽度范围在50-300微米,芯片(1)的正面通过金属凸块Ⅰ(9)倒装于再布线层(6)的上表面,所述芯片(1)彼此间于再布线层(6)的上表面设置毛细封堵部件(3),毛细封堵部件(3)完全填充毛细间隙(2)的下部,其横向长度不小于毛细间隙(2)的横向长度,其高度大于芯片(1)的下表面至再布线层(6)的上表面之间的间距,芯片(1)与再布线层(6)之间设置底填料Ⅰ(5);
还包括塑封料(4),所述塑封料(4)覆盖再布线层(6)上的所有芯片(1),并填充毛细间隙(2),所述塑封料(4)与毛细封堵部件(3)密接,扇出型芯片封装单元的下表面即再布线层(6)的下表面设有金属凸块Ⅱ(7), 扇出型芯片封装单元通过金属凸块Ⅱ(7)与基板(12)的上表面固连;扇出型芯片封装单元与基板(12)之间设置底填料Ⅱ(8)。
2.根据权利要求1所述的封装结构,其特征在于,所述毛细封堵部件(3)的纵截面呈⊥状。
3.根据权利要求1所述的封装结构,其特征在于,还包括点胶道粗糙面,所述点胶道粗糙面设置于再布线层(6)的上表面,被所述毛细封堵部件(3)覆盖,其粗糙化图形呈点状或线状。
4.一种多芯片的封装结构的封装方法,其实施步骤如下:
步骤一、提供一载体,在载体上涂覆一层临时键合材料,并在此载体上构建下述扇出型芯片封装单元;
步骤二、在临时键合材料上设置再布线层(6),并在再布线层(6)的上表面规划点胶道,所述再布线层(6)的层数根据实际需要设置;所述点胶道设置于相邻两芯片(1)的芯片贴装区域之间,其宽度不小于芯片(1)之间的毛细间隙(2)的宽度;
步骤三、点胶道粗糙化工艺,使点胶道上的再布线层(6)最外层的绝缘层的表层形成点胶道粗糙面;
步骤四、使用点胶机,通过调试胶头的大小与控制胶量,在再布线层(6)的点胶道上涂覆形成毛细封堵部件(3)的原料,所述原料的高度大于芯片(1)的上表面至再布线层(6)的上表面之间的间距,其初始宽度大于芯片(1)之间的毛细间隙(2)的宽度;
步骤五、使用自动芯片(1)贴装机器,利用橡胶吸头将芯片(1)从切割好的晶圆上吸取,再通过吸头的压力控制作用将芯片(1)倒装贴装到再布线层(6)图案层上,最后通过回流焊工艺,完成芯片(1)与再布线层(6)的焊接;要求芯片(1)贴装位置控制在贴装区域+/-15um之内,贴片旋转角度需小于1.5度;设定程序后,多个芯片(1)平铺设置,由机器控制毛细间隙(2)的宽度范围为50微米-300微米,将进入毛细间隙(2)的毛细封堵部件(3)的原料的初始宽度进行挤压成型,使芯片(1)与毛细封堵部件(3)密接;
步骤六、所述毛细封堵部件(3)固化塑型;
步骤七、芯片(1)底部填充底填料Ⅰ(5),并进行固化烘烤;
步骤八、塑封料(4)在高温模槽里预热后成液态,将上述封装结构倒置于模槽内,在真空负压下,塑封料(4)通过注塑压力从毛细间隙(2)的一端有规律地填充到毛细间隙(2)的另一端,使毛细间隙(2)内的空气在真空负压作用下驱赶干净,塑封料(4)覆盖再布线层(6)上的所有芯片(1),在流动过程中,塑封料(4)与毛细封堵部件(3)密接;
步骤九、由于临时键合材料可通过热或光作用使材料失去粘性,通过热滑动剥离、机械剥离或紫外激光剥离等技术移除载体,露出再布线层(6)的下表面,即完成了扇出型晶圆级封装结构的封装工艺;
步骤十、在所述扇出型晶圆级封装结构的再布线层(6)底部生长金属凸块Ⅱ(7);
步骤十一、将所述扇出型晶圆级封装结构切割分离成扇出型芯片封装单元;
步骤十二、将所述芯片扇出单元单体通过金属凸块Ⅱ(7)倒装于基板(12)上,并填充底填料Ⅱ(8),烘烤使底填料Ⅱ(8)固化;
步骤十三、基板(12)底部植焊球(13)。
5.根据权利要求4所述的封装方法,其特征在于,步骤三中,所述点胶道粗糙化工艺采用等离子蚀刻工艺,借助刻有镂空图案的掩模治具完成,其形成的点胶道粗糙面的表面粗糙度Ra为0.2~1.0微米。
6.根据权利要求4所述的封装方法,其特征在于,步骤三中,所述点胶道粗糙化工艺采用激光刻蚀工艺实现,其粗糙化图形呈点状或线状,形成的点胶道粗糙面的表面粗糙度Ra为0.2~3.0微米。
7.根据权利要求4所述的封装方法,其特征在于,步骤四中,所述毛细封堵部件(3)的原料通过网板印刷工艺设置在再布线层(6)的点胶道上。
8.根据权利要求4所述的封装方法,其特征在于,步骤四中,所述毛细封堵部件(3)的原料的主要成分为树脂和二氧化硅,其中,二氧化硅占比为50-90%,其粘度(25℃)为20-60Pa.S.。
9.根据权利要求4所述的封装方法,其特征在于,所述塑封料(4)的热膨胀系数远小于底填料Ⅰ(5)的热膨胀系数。
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