CN110299354B - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN110299354B
CN110299354B CN201910046513.9A CN201910046513A CN110299354B CN 110299354 B CN110299354 B CN 110299354B CN 201910046513 A CN201910046513 A CN 201910046513A CN 110299354 B CN110299354 B CN 110299354B
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semiconductor
semiconductor chip
package
heat dissipation
unit
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CN110299354A (zh
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金吉洙
金容勋
金贤基
吴琼硕
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

半导体封装包括：封装基板；下半导体芯片，在封装基板上；散热构件，在下半导体芯片上，所述散热构件具有水平单元和与水平单元相连的竖直单元；第一半导体芯片堆叠和第二半导体芯片堆叠，在水平单元上；以及模制构件，其围绕所述下半导体芯片、第一半导体芯片堆叠和第二半导体芯片堆叠以及散热构件。竖直单元可以布置在第一半导体芯片堆叠和第二半导体芯片堆叠之间，并且竖直单元的上表面可以在模制构件中暴露。

Description

半导体封装
相关申请的交叉引用
2018年3月22日在韩国知识产权局递交的题为“半导体封装”的韩国专利申请No.10-2018-0033494的全部公开内容通过引用并入本文。
技术领域
实施例涉及半导体封装。
背景技术
最近，在电子产品市场中，对移动电话的需求正在迅速增加。因此，期望安装在电子产品中的电子部件是较小且较轻的。
发明内容
实施例涉及一种半导体封装，包括：封装基板；下半导体芯片，在封装基板上；散热构件，在下半导体芯片上，所述散热构件具有水平单元和与水平单元相连的竖直单元；第一半导体芯片堆叠和第二半导体芯片堆叠，在水平单元上；以及模制构件，其围绕所述下半导体芯片、第一半导体芯片堆叠和第二半导体芯片堆叠以及散热构件。竖直单元可以布置在第一半导体芯片堆叠和第二半导体芯片堆叠之间，并且竖直单元的上表面可以在模制构件中暴露。
实施例还涉及一种半导体封装，包括：封装基板；下半导体芯片，在封装基板上；散热构件，在下半导体芯片上，所述散热构件具有水平单元和与水平单元相连的竖直单元；第一半导体芯片堆叠和第二半导体芯片堆叠，布置在水平单元上；模制构件，其围绕所述下半导体芯片、第一半导体芯片堆叠和第二半导体芯片堆叠以及散热构件；以及电磁波屏蔽构件，所述电磁波屏蔽构件覆盖所述封装基板的侧表面和所述模制构件的表面。竖直单元可以布置在第一半导体芯片堆叠和第二半导体芯片堆叠之间，并且竖直单元的上表面可以暴露在模制构件中并接触所述电磁波屏蔽构件。
实施例涉及一种半导体封装，包括：封装基板；处理器芯片，在封装基板上；散热构件，在处理器芯片上，所述散热构件具有水平单元和与水平单元相连的竖直单元；第一存储器芯片堆叠和第二存储器芯片堆叠，在所述散热构件上；以及模制构件，其围绕所述处理器、第一存储器芯片堆叠和第二存储器芯片堆叠以及散热构件。竖直单元可以位于第一存储器芯片堆叠和第二存储器芯片堆叠之间，竖直单元的上表面可以暴露在模制构件中，并且另一个封装基板可以不布置在处理器芯片与第一存储器芯片堆叠和第二存储器芯片堆叠之间。
附图说明
通过参考附图详细描述示例实施例，特征对于本领域技术人员将变得显而易见，在附图中：
图1示出了根据示例实施例的半导体封装的截面图；
图2示出了半导体封装的平面图；
图3示出了散热构件的透视图；
图4示出了根据示例实施例的半导体封装的平面图；
图5示出了散热构件的透视图；
图6示出了根据示例实施例的半导体封装的平面图；
图7示出了散热构件的透视图；
图8至图10示出了根据示例实施例的半导体封装的横截面图；
图11A至图11F示出了根据示例实施例的半导体封装的制造工艺的横截面图；
图12A至图12F示出了根据示例实施例的半导体封装的制造工艺的横截面图；以及
图13示出了根据示例实施例的半导体封装的配置的示意性框图。
具体实施方式
图1示出了根据示例实施例的半导体封装10的截面图。图2示出了半导体封装10的平面图。图3示出了散热构件MS的透视图。
参考图1至图3，在示例实施例中，半导体封装10可以包括封装基板100、安装在封装基板100上的下半导体芯片200、布置在下半导体芯片200上的散热构件MS、布置在散热构件MS上的第一半导体芯片堆叠300和第二半导体芯片堆叠400以及模制构件500。
封装基板100可以包括主体101、主体101的上表面上的上基板焊盘103以及主体101的下表面下方的下基板焊盘105。封装基板100可以具有基板连接通孔，用于将内部布线和上基板焊盘103电连接至下基板焊盘105。上基板焊盘103和下基板焊盘105中的一部分可以是接地焊盘104。
封装基板100可以是例如印刷电路板(PCB)等。
封装基板100可以由酚醛树脂、环氧树脂和聚酰亚胺中的一种或多种形成。封装基板100可以包括例如FR4、四官能环氧树脂、聚苯醚、环氧/聚苯氧化物、双马来酰亚胺三嗪、聚醯胺短纤席材，氰酸酯，聚酰亚胺和液晶聚合物中的一种或多种。上基板焊盘103、下基板焊盘105、内部布线线路、基板连接通孔可以由例如铜(Cu)、镍(Ni)、铝(Al)或铍(Be)中的一种或多种(例如，铍铜)形成。
外部连接端子110可以形成在封装基板100的下基板焊盘105上。外部连接端子110可以包括例如焊球、导电凸块、导电膏、球状栅格阵列(BGA)、触点栅格阵列(LGA)、插针栅格阵列(PGA)或上述材料的组合。在示例实施例中，可以省略外部连接端子110。
根据本示例实施例的半导体封装10可以是系统级封装。在这种情况下，可以在下半导体芯片200与第一半导体芯片堆叠300和第二半导体芯片堆叠400之间没有布置除了封装基板100之外的其他封装基板。因此，半导体封装10可以仅包括封装基板100。
下半导体芯片200可以是处理器芯片。下半导体芯片200可以由例如微处理器、图形处理器、信号处理器、网络处理器、芯片组、音频编解码器、视频编解码器、应用处理器、片上系统等实现。微处理器可以包括例如单核或多核。
下半导体芯片200可以具有有源表面和面向半导体基板201中的有源表面的非有源表面。下半导体芯片200的有源表面可以面向封装基板100的上表面。可以在下半导体芯片200的有源表面上形成多个有源/无源元件和下半导体芯片焊盘203。内部连接端子210可以形成在封装基板100和下半导体芯片200的有源表面之间。内部连接端子210可以包括焊球、导电凸块、导电膏或上述材料的组合。下半导体芯片焊盘203和上基板焊盘103可以分别接触内部连接端子210。下半导体芯片200可以通过内部连接端子210电连接至封装基板100。
散热构件MS可以包括水平单元MH和竖直单元MV。水平单元MH的水平宽度可以大于其竖直高度，并且竖直单元MV的竖直高度可以大于其水平宽度。水平单元MH可以布置在下半导体芯片200与第一半导体芯片堆叠300和第二半导体芯片堆叠400之间。竖直单元MV可以布置在第一半导体芯片堆叠300和第二半导体芯片堆叠400之间。竖直单元MV的竖直高度可以大于第一半导体芯片堆叠300和第二半导体芯片堆叠400。在散热构件MS中，水平单元MH和竖直单元MV可以彼此集成在一起。
散热构件MS可以由导电材料形成。散热构件MS可以是包括例如Cu、Al、钛(Ti)、钽(Ta)、钨(W)、镍(Ni)的金属；或上述金属的组合；包括金属的金属膏；或包括金属的金属带。
散热构件MS可以将下半导体芯片200产生的热量散发到外部。水平单元MH可以将下半导体芯片200产生的热量传递到竖直单元MV。
由下半导体芯片200产生的热量可以通过散热构件MS散发到半导体封装10的外部。为此，竖直单元MV的上表面可以通过模制构件500暴露。因此，模制构件500可以不覆盖竖直单元MV的上表面。散热构件MS可以防止下半导体芯片200产生的热量被传递到第一半导体芯片堆叠300和第二半导体芯片堆叠400。
第一半导体芯片堆叠300可以包括多个存储器芯片，例如，第一存储器芯片310和第二存储器芯片320，并且第二半导体芯片堆叠400可以包括多个存储器芯片，例如，第三存储器芯片410和第四存储器芯片420。
第一半导体芯片堆叠300可以包括安装在散热构件MS的水平单元MH的左边的第一半导体芯片310和第二半导体芯片320。第二半导体芯片320可以竖直堆叠在第一半导体芯片310上。第一半导体芯片310可以通过第一接合线315电连接至封装基板100，并且第二半导体芯片320可以通过第二接合线325电连接至封装基板100。
第二半导体芯片堆叠400可以包括安装在散热构件MS的水平单元MH的右边的第三半导体芯片410和第四半导体芯片420。第四半导体芯片420可以竖直堆叠在第三半导体芯片410上。第三半导体芯片410可以通过第三接合线415电连接至封装基板100，并且第四半导体芯片420可以通过第四接合线425电连接至封装基板100。
在其他实现方式中，半导体封装10中可以包括更多或更少的半导体芯片堆叠。
第一至第四半导体芯片310、320、410和420可以是易失性存储器芯片和/或非易失性存储器芯片。易失性存储器芯片可以包括例如动态随机存取存储器(DRAM)、静态RAM(SRAM)、晶闸管RAM(TRAM)、零电容器RAM(ZRAM)和双晶体管RAM(TTRAM)。非易失性存储器芯片可以包括例如闪存、磁RAM(MRAM)、自旋转移扭矩MRAM(STT-MRAM)、铁电RAM(FRAM)、相变RAM(PRAM)、电阻RAM(PRAM)、纳米管RRAM、聚合物RAM、纳米浮栅存储器、全息存储器、分子电子存储器和绝缘体电阻变化存储器。
构成第一至第四半导体芯片310、320、410和420的各存储器芯片可以包括：半导体基板311、321、411和421，具有彼此相对的有源表面和非有源表面；存储器件，形成在半导体基板311、321、411和421的有源表面上；以及第一至第四接合焊盘313、323、413和423，形成在半导体基板311、321、411和421的有源表面上并电连接到第一至第四接合线315、325、415和425。第一至第四半导体芯片310、320、410和420可以均具有相同的结构。
在多个分离的半导体芯片集成为一个封装的系统级封装中，第一至第四半导体芯片310、320、410和420的数量可以根据半导体封装10的目的而变化。在其他实现方式中，半导体封装10中可以包括更多或更少的半导体芯片。
第一至第四半导体芯片310、320、410和420可以通过第一至第四粘附构件317、327、417和427粘附到散热构件MS的水平单元MH上，第一半导体芯片310和第二半导体芯片320可以彼此粘附，并且第三半导体芯片410和第四半导体芯片420可以彼此粘附并且可以堆叠。
第一至第四粘附构件317、327、417和427可以是管芯附着膜。管芯附着膜可以具有例如无机粘合剂或聚合物粘合剂。聚合物粘合剂可以被分为热固性树脂和热塑性树脂。在热成型为单体之后，热固性树脂可以具有三维交联结构，并且即使热固性树脂被再加热也不会软化。热塑性树脂可以通过加热而具有可塑性，并且可以具有线性聚合物结构。热固性树脂和热塑性树脂可以彼此混合并且可以产生混合树脂。
形成第一至第四粘附构件317、327、417和427的材料的导热率可以小于形成散热构件MS的材料的导热率。直接粘附到散热构件MS的水平单元MH上的第一粘附构件317和第三粘附构件417可以由导热率小于第二粘附构件327和第四粘附构件427的导热率的材料形成，以便帮助防止热量从散热构件MS传递到第一半导体芯片310和第三半导体芯片410。
第一半导体芯片堆叠300的至少一部分可以布置在下半导体芯片200上以与下半导体芯片200重叠。另外，第二半导体芯片堆叠400的至少一部分可以布置在下半导体芯片200上，以在与第一半导体芯片堆叠300不同的部分中与下半导体芯片200重叠。因此，在半导体封装10的平面结构中，下半导体芯片200的平面面积可以大于第一半导体芯片堆叠300的平面面积，并且下半导体芯片200的平面面积可以大于第二半导体芯片堆叠400的平面面积。下半导体芯片200的平面面积可以等于水平单元MH的平面面积。
第一至第四接合线315、325、415和425可以将第一至第四半导体芯片310、320、410和420电连接至封装基板100。第一至第四接合线315、325、415和425可以将第一至第四半导体芯片310、320、410和420的第一至第四接合焊盘313、323、413和423分别连接至封装基板100的上基板焊盘103。在附图中，为方便起见，仅示出了一些接合线。
另外，接地接合线MG可以将散热构件MS电连接至第一至第四半导体芯片310、320、410和420的第一至第四接合焊盘313、323、413和423中的一个。第一至第四半导体芯片310、320、410和420可以通过第一至第四接合线315、325、415和425电连接至封装基板100。因此，接地接合线MG可以将散热构件MS电连接至封装基板100的接地焊盘104。散热构件MS可以由如上所述的导电材料形成。在这种情况下，如果散热构件MS没有接地，则可能发生浮置现象。因此，半导体封装10可以包括接地接合线MG，以便帮助防止浮置现象。
第一至第四接合线315、325、415和425以及接地接合线MG可以包括金(Au)、银(Ag)、Cu和Al中的至少一种。在示例实施例中，第一至第四接合线315、325、415和425以及接地接合线MG可以通过热压连接和超声波连接或通过组合热压连接和超声波连接获得的热超声连接中的一种方法相连。
在示例实施例中，配置第一半导体芯片堆叠300和第二半导体芯片堆叠400的第一至第四半导体芯片310、320、410和420可以被对准为在Y方向上移位并且越过。第一至第四半导体芯片310、320、410和420可以竖直对准。第一至第四接合线315、325、415和425中的一些可以形成为穿过第二粘附构件327和第四粘附构件427中的一个的内部。
在示例实施例中，水平单元MH在平行于X方向上的第一宽度MHX可以小于在Y方向上的第二宽度MHY，其中所述X方向平行于形成第一至第四接合线315、325、415和425的方向，且所述Y方向垂直于形成第一至第四接合线315、325、415和425的方向。因此，可以设计散热构件MS，使得第一至第四接合线315、325、415和425的长度最小化，同时使水平单元MH的平面面积最大化。
模制构件500可以包围下半导体芯片200、第一半导体芯片堆叠300和第二半导体芯片堆叠400以及散热构件MS，并且可以保护下半导体芯片200、第一半导体芯片堆叠300和第二半导体芯片堆叠400以及散热构件MS免受外部环境的干扰。
可以通过注入工艺将模制树脂注入到封装基板100上，并且可以通过硬化工艺形成半导体封装10的外观，从而获得模制构件500。半导体封装10的外观可以是通过在使用压力机的加压工艺中对模制树脂施加压力来形成的。考虑到诸如模制树脂的粘度的物理性质，可以设定诸如模制树脂注入和加压之间的延迟时间、注入的模制树脂的量和加压温度/压力之类的工艺条件。
在示例实施例中，模制树脂可以包括环氧基模制树脂或聚酰亚胺基模制树脂。模制构件500可以由例如环氧模制化合物(EMC)或高K环氧模制化合物形成。形成模制构件500的材料的导热率可以小于形成散热构件MS的材料的导热率。
模制构件500可以保护下半导体芯片200以及第一半导体芯片堆叠300和第二半导体芯片堆叠400免受例如污染和冲击的外部影响。模制构件500的厚度可以形成为包围所有下半导体芯片200以及第一半导体芯片堆叠300和第二半导体芯片堆叠400。模制构件500可以完全覆盖封装基板100。因此，模制构件500的宽度可以等于半导体封装10的宽度。模制构件500可以将散热构件MS的竖直单元MV的上表面暴露到外部。因此，模制构件500可以不覆盖竖直单元MV的上表面。
对便携式设备的需求正在迅速增长。因此，期望安装在电子产品中的电子部件是较小且较轻的。为了使电子部件小而轻，安装在电子部件中的半导体封装可以在处理高容量数据的同时具有减小的封装体积。期望的是安装在半导体封装中的半导体芯片是高密度集成的和单独封装的。因此，为了高效地将半导体芯片布置在半导体封装的有限结构中，可以应用系统级封装。然而，通常，由于许多操作可以产生大量的热量。如果不控制热量的产生，则可能影响存储器芯片的性能。
在根据本示例实施例的半导体封装10中，散热构件MS可以布置成直接接触下半导体芯片200，在实现中，下半导体芯片200是比第一至第四半导体芯片310、320、410和420产生更多热量的芯片。因此，半导体芯片可以被高效地布置在半导体封装10的有限空间结构中，同时提供改善的散热和高密度集成。
图4示出了根据示例实施例的半导体封装20的平面图。图5示出了散热构件MS的透视图。
参考图4和图5，半导体封装20可以包括封装基板100、安装在封装基板100上的下半导体芯片、布置在下半导体芯片上的散热构件MS、布置在散热构件MS上的第一半导体芯片堆叠300和第二半导体芯片堆叠400以及模制构件。
构成半导体封装20的各个元件和形成元件的材料可以与图1至图3中描述的元件和材料相同或相似。因此，以下描述将主要针对不同之处进行。半导体封装20被示出为具有平面结构，使得未示出下半导体芯片，并且省略模制构件，以描述半导体封装20的内部结构。
在半导体封装20中，将如下描述第一半导体芯片堆叠300和第二半导体芯片堆叠400的相对位置以及封装基板100上的散热构件MS的竖直单元MV。可以布置第一半导体芯片堆叠300和第二半导体芯片堆叠400，使得其部分重叠。竖直单元MV可以包括多个结构MV1、MV2和MV3，并且可以与第一半导体芯片堆叠300和第二半导体芯片堆叠400分离。多个结构MV1、MV2和MV3可以在不同位置形成为具有不同大小。多个结构MV1、MV2和MV3的所有竖直高度可以彼此相等。
与半导体封装10不同，接地接合线MG可以直接将散热构件MS电连接至封装基板100的接地焊盘104，而不穿过第一至第四半导体芯片310、320、410和420。
图6示出了根据示例实施例的半导体封装30的平面图。图7示出了散热构件MS的透视图。
参考图6和图7，半导体封装30可以包括封装基板100、安装在封装基板100上的下半导体芯片、布置在下半导体芯片上的散热构件MS、布置在散热构件MS上的第一至第四半导体芯片310、320、410和420以及模制构件。
构成半导体封装30的各个元件和形成元件的材料可以与图1至图3中描述的元件和材料相同或相似。因此，将主要描述不同之处。半导体封装30被示出为具有平面结构，使得未示出下半导体芯片，并且省略模制构件，以描述半导体封装30的内部结构。
在半导体封装30中，将如下描述第一至第四半导体芯片310、320、410和420以及封装基板100上的散热构件MS的竖直单元MV的相对位置。所有第一至第四半导体芯片310、320、410和420可以彼此分离，以便彼此不重叠。竖直单元MV可以分隔第一至第四半导体芯片310、320、410和420，并且可以与第一至第四半导体芯片310、320、410和420分离。竖直单元MV可以形成为使得在X和Y方向上延伸的结构在水平单元MH的中心相会。
图8至图10示出了根据示例实施例的半导体封装的横截面图。
参考图8，半导体封装40可以包括封装基板100、安装在封装基板100上的下半导体芯片200、布置在下半导体芯片200上的散热构件MS、布置在散热构件MS上的第一半导体芯片堆叠300和第二半导体芯片堆叠400、模制构件500和电磁波屏蔽构件600。
构成半导体封装40的各个元件和形成元件的材料可以与图1至图3中描述的元件和材料相同或相似。因此，将主要描述不同之处。
当半导体封装40安装在包括主板的电子设备中时，可以发射由半导体封装40产生的电磁波，并且电磁干扰(EMI)可能影响安装在电子设备中的其他电子部件。因此，可能在安装有半导体封装40的电子设备中产生诸如电磁波噪声或错误操作之类的干扰，这可能影响产品的可靠性。电磁波屏蔽构件600可以帮助防止在半导体封装40的操作过程中产生的电磁波影响外部。
为了增加电磁波屏蔽效果，电磁波屏蔽构件600可以电连接至接地焊盘104。
散热构件MS可以电连接至电磁波屏蔽构件600，并且电磁波屏蔽构件600可以电连接至封装基板100的接地焊盘104。因此，可以在半导体封装40中省略接地接合线MG。
电磁波屏蔽构件600可以包括导电材料。例如，导电材料可以包括金属。电磁波屏蔽构件600可以形成为金属薄膜。在这种情况下，金属薄膜可以通过薄膜形成工艺形成，例如，喷涂工艺、电镀工艺、无电镀覆工艺或溅射工艺。
参考图9，半导体封装50可以包括封装基板100、安装在封装基板100上的下半导体芯片200、布置在下半导体芯片200上的散热构件MS、布置在散热构件MS上的第一半导体芯片堆叠300和第二半导体芯片堆叠400和模制构件500。
构成半导体封装50的各个元件和形成元件的材料可以与图1至图3中描述的元件和材料相同或相似。因此，将主要描述不同之处。
第一半导体芯片堆叠300可以包括安装在散热构件MS的水平单元MH的左边的第一半导体芯片310、第二半导体芯片320和第五半导体芯片330。第二半导体芯片320可以竖直堆叠在第一半导体芯片310上，并且第五半导体芯片330可以竖直堆叠在第二半导体芯片320上。第一半导体芯片310、第二半导体芯片320和第五半导体芯片330可以分别通过第一接合线315，通过第二接合线325以及通过第五接合线335电连接至封装基板100。
第二半导体芯片堆叠400可以包括安装在散热构件MS的水平单元MH的右边的第三半导体芯片410、第四半导体芯片420和第六半导体芯片430。第四半导体芯片420可以竖直堆叠在第三半导体芯片410上。第六半导体芯片430可以竖直堆叠在第四半导体芯片420上。第三半导体芯片410、第四半导体芯片420和第六半导体芯片430可以分别通过第三接合线415，通过第四接合线425以及通过第六接合线435电连接至封装基板100。
下半导体芯片200的X方向上的宽度200X可以大于水平单元MH的X方向上的宽度MHX。因此，散热构件MS可以不形成在下半导体芯片200的一部分中。因此，下半导体芯片200的平面面积可以大于水平单元MH的平面面积。
参考图10，半导体封装60可以包括封装基板100、安装在封装基板100上的下半导体芯片200、布置在下半导体芯片200上的散热构件MS、布置在散热构件MS上的第一半导体芯片堆叠300和第二半导体芯片堆叠400、模制构件500和电磁波屏蔽构件600。
构成半导体封装60的各个元件和形成元件的材料可以与图9中描述的元件和材料相同或相似。因此，将主要描述不同之处。
电磁波屏蔽构件600可以帮助防止在半导体封装60的操作过程中产生的电磁波影响外部。为了增加电磁波屏蔽效果，电磁波屏蔽构件600可以电连接至接地焊盘104。
散热构件MS可以电连接至电磁波屏蔽构件600，并且电磁波屏蔽构件600可以电连接至封装基板100的接地焊盘104。因此，可以在半导体封装60中省略接地接合线MG。
下半导体芯片200的X方向上的宽度200X可以小于水平单元MH的X方向上的宽度MHX。因此，在散热构件MS中，可以存在不接触下半导体芯片200的区域。因此，下半导体芯片200的平面面积可以小于水平单元MH的平面面积。
图11A至图11F示出了根据示例实施例的半导体封装的制造工艺中的各阶段的横截面图。
参考图11A，下半导体芯片200可以安装在安装封装基板100的区域上。
内部连接端子210可以布置在封装基板100和下半导体芯片200之间。内部连接端子210可以包括焊球、导电凸块、导电膏或上述材料的组合。下半导体芯片200可以通过内部连接端子210电连接至封装基板100。
参考图11B，散热构件MS可以布置在下半导体芯片200上，以便接触下半导体芯片200。
散热构件MS可以包括水平单元MH和竖直单元MV。散热构件MS可以是一体的。散热构件MS可以由导电材料形成的。可以分开地制造散热构件MS和下半导体芯片200。因此，散热构件MS可以被预先一体地制造并且可以布置在下半导体芯片200上。
参考图11C，第一半导体芯片310和第三半导体芯片410可以布置在散热构件MS上，并且第一半导体芯片310和第三半导体芯片410以及封装基板100可以通过使用第一接合线315和第三接合线415电连接。
直接粘附到散热构件MS的水平单元MH上的第一粘附构件317和第三粘附构件417可以包括具有低导热率的材料，以便帮助防止热量从散热构件MS传递到第一半导体芯片310和第三半导体芯片410。
参考图11D，第二半导体芯片320和第四半导体芯片420可以布置在第一半导体芯片310和第三半导体芯片410上，并且第二半导体芯片320和第四半导体芯片420以及封装基板100可以通过使用第二接合线325和第四接合线425电连接。
第二半导体芯片320和第四半导体芯片420可以在Y方向上移位一段距离，并且可以堆叠在第一半导体芯片310和第三半导体芯片410上，使得形成在第二半导体芯片320和第四半导体芯片420下方的半导体芯片的上表面的一部分中的第一接合焊盘313和第三接合焊盘413被暴露。
在多个分离的元件集成为一个封装的系统级封装中，半导体芯片的数量可以根据半导体封装的目的而变化。因此，可以堆叠更多或更少的半导体芯片。
接地接合线可以通过散热构件MS和第一至第四半导体芯片310、320、410和420之一电连接至封装基板100的接地焊盘。
当将第一至第四半导体芯片310、320、410和420堆叠为阶梯时，可以形成再分布层。在第一至第四接合焊盘313、323、413和423位于第一至第四半导体芯片310、320、410和420的部分中的情况下，当第一至第四半导体芯片310、320、410和420被堆叠时，半导体封装可以是复杂的，并且第一至第四接合线315、325、415和425的长度可能增加，使得特性劣化。因此，可以通过形成重新布线来改变第一至第四接合焊盘313、323、413和423的位置。
参考图11E，可以形成覆盖下半导体芯片200以及第一半导体芯片堆叠300和第二半导体芯片堆叠400并且暴露散热构件MS的竖直单元MV的上表面的模制构件500。
在一般的半导体封装中，可以形成模制构件以覆盖布置在封装基板的上表面上的所有元件。根据示例实施例，模制构件500形成为暴露热发射构件MS的竖直单元MV的上表面，这可以如上所述地改善散热性质。
在执行上述工艺之后，可以通过在封装基板100中形成外部连接端子110(参考图1)来制造半导体封装10。
参考图11F，模制构件500可以被电磁波屏蔽构件600覆盖，并且电磁波屏蔽构件600可以电连接至封装基板100的接地焊盘104。
电磁波屏蔽构件600可以覆盖模制构件500的上表面、模制构件500的侧表面、散热构件MS的竖直单元MV的上表面以及封装基板100的侧表面。散热构件MS可以直接接触电磁波屏蔽构件600，并且电磁波屏蔽构件600可以直接接触封装基板100的接地焊盘104。
电磁波屏蔽构件600可以是金属薄膜的形式。在这种情况下，金属薄膜可以通过薄膜形成工艺形成，例如，喷涂工艺、电镀工艺、无电镀覆工艺或溅射工艺。
在执行上述工艺之后，可以通过在封装基板100上形成外部连接端子110(参考图4)来制造半导体封装40。
图12A至图12F示出了根据示例实施例的半导体封装的制造工艺中的各阶段的横截面图。
参考12A，备用水平单元MHW可以形成在备用下半导体芯片200W的非有源表面上。
备用水平单元MHW可以包括诸如金属或合金的导电材料，例如，Cu、Al、Ni、Pt、Ag、Au或上述金属的组合。备用水平单元MHW可以通过薄膜形成工艺形成，例如，喷涂工艺、电镀工艺、无电镀覆工艺、溅射工艺或金属带粘附工艺。
备用下半导体芯片200W和备用水平单元MHW可以在划线道SL中切割并且可以在物理上彼此分离，使得形成下半导体芯片200(参考图12B)(其中形成水平单元MH(参考图12B))。
参考图12B，形成有水平单元MH的下半导体芯片200可以安装在封装基板100上。
内部连接端子210可以布置在封装基板100和形成有水平单元MH的下半导体芯片200之间。内部连接端子210可以包括焊球、导电凸块、导电膏或上述材料的组合。形成有水平MH的下半导体芯片200可以通过内部连接端子210电连接至封装基板100。
参考图12C，第一半导体芯片堆叠300和第二半导体芯片堆叠400可以布置在水平单元MH上。
可以直接粘附到水平单元MH上的第一粘附构件317和第三粘附构件417可以包括具有低导热率的材料，以帮助防止热量从散热构件MS传递到第一半导体芯片310和第三半导体芯片410。
第二半导体芯片320和第四半导体芯片420可以在与封装基板100水平的方向上移位一段距离，并且可以堆叠在第一半导体芯片310和第三半导体芯片410上，使得第一接合焊盘313和第三接合焊盘413(形成在第二半导体芯片320和第四半导体芯片420下方的半导体芯片的上表面的一部分中)被暴露。
接地接合线可以通过散热构件MS和第一至第四半导体芯片310、320、410和420之一电连接至封装基板100的接地焊盘。
参考图12D，模制构件500可以形成为覆盖下半导体芯片200以及第一半导体芯片堆叠300和第二半导体芯片堆叠400。
与上述制造工艺不同，可以不形成竖直单元MV(参考图12F)。因此，模制构件500可以覆盖布置在封装基板100的上表面上的所有元件。
参考图12E，可以在模制构件500中形成暴露水平单元MH的一部分的模制开口500H。
可以通过去除模制构件500的一部分来形成模制开口500H。模制开口500H可以通过例如钻孔工艺形成。当没有水平单元MH时，下半导体芯片200可能被钻孔损坏。模制开口500H的最下表面的水平面可以高于下半导体芯片200的最上表面。水平单元MH可以形成在下半导体芯片200上。因此，可以避免对下半导体芯片200的损坏。
参考图12F，竖直单元MV可以形成在模制开口500H中，并且热发射构件MS可以形成为接触水平单元MH。
在示例实施例中，诸如金属和粘合剂聚合物的导电材料可以填充在模制开口500H中。竖直单元MV和水平单元MH可以由相同的材料形成。竖直单元MV可以连接到水平单元MH，并且可以形成散热构件MS。因此，散热构件MS可以不是一体的。
在执行上述工艺之后，可以通过在封装基板100上形成外部连接端子110(参考图1)来制造半导体封装10。
图13示出了根据示例实施例的半导体封装的配置的示意性框图。
参考图13，半导体封装1000可以包括微处理单元(MPU)1010、存储器1020、接口1030、图形处理单元(GPU)1040、功能块1050以及用于连接功能块1050的系统总线1060。半导体封装1000可以包括MPU 1010和GPU 1040两者，或者仅包括MPU 1010和GPU 1040中的一个。
MPU 1010可以包括核心和L2高速缓存。例如，MPU 1010可以包括多核。多核中的各个核可以具有相同的性能或不同的性能。多核中的各个核可以同时激活或者可以在不同的时间点激活。
存储器1020可以通过微处理单元1010的控制来存储由功能块1050处理的结果。接口1030可以向外部设备发送信息或信号且从外部设备接收信息或信号。GPU 1040可以执行图形功能。例如，GPU 1040可以执行视频编解码器或者可以处理三维(3D)图形。功能块1050可以执行各种功能。例如，当半导体封装1000是移动设备中的无线接入点(AP)时，一些功能块1050可以执行通信功能。半导体封装1000可以包括根据图1至图10中描述的本示例实施例的半导体封装10、20、30、40、50和60中的一个。
通过总结和回顾，为了使电子部件小而轻，可以形成被安装在电子部件中的半导体封装，以用减小的封装体积处理大容量数据。安装在半导体封装中的半导体芯片被期望是高度集成的且单个封装的。因此，为了高效地将半导体芯片布置在半导体封装的有限结构中，应用系统级封装。
如上所述，实施例涉及一种包括处理器芯片和存储器芯片的系统级封装。实施例可以提供能够在半导体封装的有限结构中高效地布置半导体芯片的同时改善散热性质和高密度集成的半导体封装。
本文已经公开了示例实施例，并且尽管采用了特定的术语，但是这些术语被使用并且将仅被解释为一般的和描述性的意义，而不是为了限制的目的。在一些情况下，在提交本申请时对于本领域普通技术人员将是显而易见的是，除非另外具体指出，否则结合特定实施例描述的特征、特性和/或元件可以单独使用或者与结合其它实施例描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离如所附权利要求中阐述的本发明的精神和范围的前提下，可以进行形式和细节上的各种改变。

Claims (20)

1.一种半导体封装，包括：
封装基板；
下半导体芯片，在所述封装基板上；
散热构件，在所述下半导体芯片上，所述散热构件具有水平单元和与所述水平单元相连的竖直单元；
第一半导体芯片堆叠和第二半导体芯片堆叠，在所述水平单元上；以及
模制构件，所述模制构件包围所述下半导体芯片、所述第一半导体芯片堆叠和所述第二半导体芯片堆叠以及所述散热构件，其中：
所述竖直单元布置在所述第一半导体芯片堆叠和所述第二半导体芯片堆叠之间，
所述竖直单元的上表面暴露在所述模制构件中，以及
所述第一半导体芯片堆叠和所述第二半导体芯片堆叠通过具有低导热率的粘附构件直接粘附到所述水平单元。
2.根据权利要求1所述的半导体封装，其中：
所述第一半导体芯片堆叠包括多个第一半导体芯片，
所述第二半导体芯片堆叠包括多个第二半导体芯片，
所述多个第一半导体芯片和所述多个第二半导体芯片通过接合线与所述封装基板电连接，以及
所述下半导体芯片通过接合凸块与所述封装基板电连接。
3.根据权利要求2所述的半导体封装，其中所述多个第一半导体芯片和所述多个第二半导体芯片中的最下面的半导体芯片通过所述粘附构件粘附到所述水平单元。
4.根据权利要求2所述的半导体封装，其中：
所述封装基板包括接地焊盘，以及
所述散热构件通过所述多个第一半导体芯片和所述多个第二半导体芯片之一与所述接地焊盘电连接，或者
所述散热构件与所述接地焊盘直接电连接。
5.根据权利要求2所述的半导体封装，其中，所述水平单元沿形成所述接合线的方向的第一宽度小于所述水平单元沿垂直于形成所述接合线的所述方向的方向的第二宽度。
6.根据权利要求1所述的半导体封装，其中，所述水平单元直接粘附到所述下半导体芯片。
7.根据权利要求1所述的半导体封装，其中，所述第一半导体芯片堆叠和所述第二半导体芯片堆叠彼此不重叠。
8.根据权利要求7所述的半导体封装，其中，所述竖直单元形成为一个结构，并且与所述第一半导体芯片堆叠和所述第二半导体芯片堆叠分离。
9.根据权利要求1所述的半导体封装，其中，所述第一半导体芯片堆叠和所述第二半导体芯片堆叠至少部分地彼此重叠。
10.根据权利要求9所述的半导体封装，其中，所述竖直单元由多个结构形成，并且与所述第一半导体芯片堆叠和所述第二半导体芯片堆叠分离。
11.一种半导体封装，包括：
封装基板；
下半导体芯片，在所述封装基板上；
散热构件，在所述下半导体芯片上，所述散热构件具有水平单元和与所述水平单元相连的竖直单元；
第一半导体芯片堆叠和第二半导体芯片堆叠，布置在所述水平单元上；
模制构件，所述模制构件包围所述下半导体芯片、所述第一半导体芯片堆叠和所述第二半导体芯片堆叠以及所述散热构件；以及
电磁波屏蔽构件，所述电磁波屏蔽构件覆盖所述封装基板的侧表面和所述模制构件的表面，其中：
所述竖直单元布置在所述第一半导体芯片堆叠和所述第二半导体芯片堆叠之间，
所述竖直单元的上表面暴露在所述模制构件中并接触所述电磁波屏蔽构件，以及
所述第一半导体芯片堆叠和所述第二半导体芯片堆叠通过具有低导热率的粘附构件直接粘附到所述水平单元。
12.根据权利要求11所述的半导体封装，其中：
所述封装基板包括接地焊盘，以及
所述电磁波屏蔽构件与所述接地焊盘电连接。
13.根据权利要求11所述的半导体封装，其中所述水平单元的平面面积大于下半导体芯片的平面面积。
14.根据权利要求11所述的半导体封装，其中：
所述第一半导体芯片堆叠由多个第一半导体芯片形成，
所述第二半导体芯片堆叠由多个第二半导体芯片形成，
所述多个第一半导体芯片和所述多个第二半导体芯片通过接合线与所述封装基板相连，以及
所述下半导体芯片通过接合凸块与所述封装基板相连。
15.根据权利要求14所述的半导体封装，其中：
所述多个第一半导体芯片和所述多个第二半导体芯片包括存储器芯片，以及
所述下半导体芯片包括处理器芯片。
16.一种半导体封装，包括：
封装基板；
处理器芯片，在所述封装基板上；
散热构件，在所述处理器芯片上，所述散热构件具有水平单元和与所述水平单元相连的竖直单元；
第一存储器芯片堆叠和第二存储器芯片堆叠，在所述散热构件上；以及
模制构件，所述模制构件包围所述处理器芯片、所述第一存储器芯片堆叠和所述第二存储器芯片堆叠以及所述散热构件，其中：
所述竖直单元位于所述第一存储器芯片堆叠和所述第二存储器芯片堆叠之间，
所述竖直单元的上表面暴露在所述模制构件中，
在所述处理器芯片与所述第一存储器芯片堆叠和第二存储器芯片堆叠之间未布置其他封装基板，以及
所述第一存储器芯片堆叠和所述第二存储器芯片堆叠通过具有低导热率的粘附构件直接粘附到所述水平单元。
17.根据权利要求16所述的半导体封装，其中，形成所述散热构件的材料的导热率大于形成所述模制构件的材料的导热率。
18.根据权利要求17所述的半导体封装，其中：
所述模制构件包括环氧树脂模制化合物，以及
所述散热构件由金属、金属膏、金属带或导电材料形成。
19.根据权利要求17所述的半导体封装，其中，所述第一存储器芯片堆叠和所述第二存储器芯片堆叠的相应最下面的存储器芯片通过所述粘附构件粘附到所述水平单元，所述粘附构件的导热率低于所述散热构件的导热率。
20.根据权利要求16所述的半导体封装，其中：
所述水平单元接触所述处理器芯片，以及
所述竖直单元与所述第一存储器芯片堆叠和所述第二存储器芯片堆叠分离。
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