CN110289305A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN110289305A
CN110289305A CN201810749458.5A CN201810749458A CN110289305A CN 110289305 A CN110289305 A CN 110289305A CN 201810749458 A CN201810749458 A CN 201810749458A CN 110289305 A CN110289305 A CN 110289305A
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semiconductor regions
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CN110289305B (zh
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白石达也
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Toshiba Corp
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Abstract

一种半导体装置，具备第1导电型的第1半导体区域和第3半导体区域、第2导电型的第2半导体区域、第1～3电极、第1层以及第2层。第1半导体区域具有在第1方向上排列的第1区域以及第2区域。第1电极设置在第1区域之上。第2半导体区域设置在第2区域之上。第3半导体区域设置在第2半导体区域的一部分之上。第2电极设置在第3半导体区域之上，在第1方向上与第1电极分离。第3电极设置在第2半导体区域的其他的一部分以及第1半导体区域的一部分之上，与第1电极以及第2电极分离。第1层设置在第3电极之上，包含从由钛、镍以及钒构成的组中选择的至少一个。第2层设置在第1层之上，包含从由氮以及氧构成的组中选择的至少一个和硅。

Description

半导体装置
关联申请的交叉引用
本申请以日本专利申请2018－50468号(申请日：2018年3月19日)为基础申请享受优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式一般涉及半导体装置。
背景技术
有包括肖特基势垒二极管的半导体装置。该半导体装置的特性的变动优选较小。
发明内容
实施方式提供能够抑制特性的变动的半导体装置。
根据一个实施方式，半导体装置具备第1导电型的第1半导体区域、第1电极、第2导电型的第2半导体区域、第1导电型的第3半导体区域、第2电极、第3电极、第1层以及第2层。上述第1半导体区域具有在第1方向上排列的第1区域以及第2区域。上述第1电极设置在上述第1区域之上。上述第2半导体区域设置在上述第2区域之上。上述第3半导体区域设置在上述第2半导体区域的一部分之上。上述第2电极设置在上述第3半导体区域之上，在上述第1方向上与上述第1电极分离。上述第3电极设置在上述第2半导体区域的其他的一部分以及上述第1半导体区域的一部分之上，与上述第1电极以及上述第2电极分离。上述第1层设置在上述第3电极之上，包含从由钛、镍以及钒构成的组中选择的至少一个。上述第2层设置在上述第1层之上，包含从由氮以及氧构成的组中选择的至少一个和硅。
附图说明
图1是第1实施方式的半导体装置的截面图。
图2是表示第1实施方式的半导体装置的等价电路的电气电路图。
图3是第2实施方式的半导体装置的截面图。
具体实施方式
以下，参照附图对本发明的各实施方式进行说明。
附图是示意性的或概念性的图，各部分的厚度与宽度的关系、部分间的大小的比率等并不一定与现实的相同。在表示相同部分的情况下，也有根据附图将彼此尺寸、比率不同地表示的情况。
本申请说明书和各图中，对于与说明过的要素相同的要素，赋予相同的符号并适当省略详细的说明。
以下的说明以及附图中，n+、n、n－以及p的标记表示各导电型中的杂质浓度的相对高低。即，带有“+”的标记表示与没有带“+”以及”－”的任何一个的标记相比杂质浓度相对高，带有“－”的标记表示与没有带“+”以及”－”的任何一个的标记相比杂质浓度相对低。在各个区域中包含有p型杂质和n型杂质这两者的情况下，这些标记表示这些杂质相互补偿后的实际的杂质浓度的相对高低。
关于以下说明的各实施方式，也可以使各半导体区域的p型和n型反转来实施各实施方式。
(第1实施方式)
图1是第1实施方式的半导体装置的截面图。
如图1所示，第1实施方式的半导体装置100具有n－型(第1导电型)半导体区域1(第1半导体区域)、p型(第2导电型)基极区域2(第2半导体区域)、n型发射极区域3(第3半导体区域)、n+型集电极区域4(第4半导体区域)、集电极电极11(第1电极)、发射极电极12(第2电极)、基极电极13(第3电极)、第1层21以及第2层22。
n－型半导体区域1具有第1区域1a以及第2区域1b。这里，将从第1区域1a朝向第2区域1b的方向设为X方向(第1方向)。将与X方向垂直的方向设为Z方向，将与X方向及Z方向垂直的方向设为Y方向。为了便于说明，在附图中将上方称为“上”，将其相反方向称为“下”，但这些方向与重力方向无关。
第1区域1a和第2区域1b在X方向上并排。n+型集电极区域4设置在第1区域1a之上。集电极电极11设置在n+型集电极区域4之上，与n+型集电极区域4电连接。例如，集电极电极11的X方向上的长度比n+型集电极区域4的X方向上的长度长。集电极电极11设置在n+型集电极区域4之上以及n－型半导体区域1的一部分之上。
p型基极区域2设置在第2区域1b之上。n型发射极区域3设置在p型基极区域2的一部分之上。发射极电极12设置在n型发射极区域3之上，与n型发射极区域3电连接。发射极电极12在X方向上与集电极电极11分离。例如，发射极电极12的X方向上的长度比n型发射极区域3的X方向上的长度短。
基极电极13设置在p型基极区域2的其他的一部分之上以及n－型半导体区域1的一部分之上，与这些半导体区域电连接。基极电极13与集电极电极11以及发射极电极12分离。基极电极13例如位于集电极电极11与发射极电极12之间。
n－型半导体区域1、p型基极区域2、n型发射极区域3、以及n+型集电极区域4例如包含有硅作为主成分。或者，n－型半导体区域1、p型基极区域2、n型发射极区域3，以及n+型集电极区域4也可以包含碳化硅、砷化镓或氮化镓作为主成分。
集电极电极11、发射极电极12以及基极电极13包含从由铝、钴以及钨构成的组中选择的至少一个。
第1层21设置在基极电极13之上。第1层21除了基极电极13之上以外，还可以在基极电极13的周围设置在n－型半导体区域1之上以及p型基极区域2之上。第1层21包含从由钛、镍以及钒构成的组中选择的至少一个。
第2层22设置在第1层21之上。第2层22包含硅和从由氮以及氧构成的组中选择的至少一个。例如，第2层22是包含氮化硅的绝缘层。
在第2层22之上也可以设有绝缘层23。绝缘层23包含硅和从由氮以及氧构成的组中选择的至少一个。例如，绝缘层23包含氧化硅。绝缘层23的厚度比第2层22的厚度大。
如图1所示，在集电极电极11以及发射极电极12之上也可以分别设有层21a(第3层)以及层21b(第4层)。第1层21、层21a、以及层21b在X方向上相互分离。层21a以及21b与第1层21同样，包含从由钛、镍、以及钒构成的组中选择的至少一个。例如，第2层22以及绝缘层23在第1层21、层21a以及层21b之上连续地设置。
在绝缘层23之上例如设有用于将半导体装置100封固的绝缘性的树脂层28。树脂层28例如包含环氧树脂或聚酰亚胺等。
图2是表示第1实施方式的半导体装置的等价电路的电气电路图。
如图2所示，半导体装置100中，由n－型半导体区域1(n+型集电极区域4)、p型基极区域2以及n型发射极区域3构成双极晶体管BJT。进而，半导体装置100中，n－型半导体区域1以及基极电极13进行肖特基接合，由此构成肖特基势垒二极管SBD。该肖特基势垒二极管SBD的正向是从基极电极13向集电极电极11流过电流的方向。
说明第1实施方式的效果。
第1实施方式的半导体装置100中，在n－型半导体区域1与基极电极13之间构成肖特基势垒二极管SBD。即，如图2所示，肖特基势垒二极管SBD连接在集电极电极11与基极电极13之间。由此，能够将向基极电极13流入的电流(基极电流)保持为规定值，使双极晶体管BJT的输出更加稳定。另一方面，肖特基势垒二极管SBD的特性(例如正向电压)依赖于n－型半导体区域1与基极电极13之间的界面的状态。例如，水分等杂质从树脂层28或半导体装置100的外部向界面移动，如果界面的状态变化，则肖特基势垒二极管SBD的特性也变动。其结果，半导体装置100的特性变动。
为了抑制杂质在n－型半导体区域1与基极电极13之间的界面移动，在基极电极13之上设置阻挡性高的包含硅的绝缘层(第2层22)是有效的。
另一方面，第2层22有时包含氢。在第2层22包含氢的情况下，随着时间的经过或在半导体装置100的制造过程中，氢有可能在n－型半导体区域1与基极电极13之间的界面移动。氢使肖特基势垒二极管SBD的特性变动。
因此，半导体装置100中，在基极电极13与第2层22之间设有第1层21，该第1层21包含从由钛、镍以及钒构成的组中选择的至少一个。这些元素容易吸收氢。更具体地讲，这些元素比基极电极13中包含的铝、钴或钨等更容易吸收氢。通过设置第1层21，第2层22中包含的氢难以到达n－型半导体区域1与基极电极13之间的界面。能够抑制肖特基势垒二极管SBD的特性的变动。
根据本实施方式，能够抑制半导体装置100的特性的变动，能够提高半导体装置100的可靠性。
第1层21优选的是，在基极电极13的周围设置在n－型半导体区域1之上以及p型基极区域2之上。根据该结构，能够抑制水分或氢向基极电极13的周围的n－型半导体区域1或p型基极区域2的表面移动。能够抑制氢沿着这些表面向n－型半导体区域1与基极电极13的界面移动。因此，能够进一步提高半导体装置100的可靠性。
(第2实施方式)
图3是表示第2实施方式的半导体装置的截面图。
第2实施方式的半导体装置200如图3所示，具有n－型半导体区域31(第1半导体区域)、n+型阴极区域32(第2半导体区域)、p型保护环区域33、阳极电极41(第1电极)、阴极电极42(第2电极)、第1层21以及第2层22。
n+型阴极区域32设置在阴极电极42之上，与阴极电极42电连接。n－型半导体区域31设置在n+型阴极区域32之上。p型保护环区域33在n－型半导体区域31的一部分的周围以环状设置。
阳极电极41设置在n－型半导体区域31之上以及p型保护环区域33之上，与n－型半导体区域31电连接。阳极电极41与n－型半导体区域31进行肖特基接合。
第1层21设置在阳极电极41之上、p型保护环区域33之上以及n－型半导体区域31的外周上。第2层22设置在第1层21之上。绝缘层23设置在第2层22之上。在绝缘层23之上例如设有树脂层28。
n－型半导体区域31、n+型阴极区域32以及p型保护环区域33例如包含硅作为主成分。或者，n－型半导体区域31、n+型阴极区域32以及p型保护环区域33也可以包含碳化硅、砷化镓或者氮化镓作为主成分。
阳极电极41以及阴极电极42包含从由铝、钴以及钨构成的组中选择的至少一个。
在本实施方式中，也在阳极电极41之上设有第1层21以及第2层22。由此，能够抑制由水分以及氢引起的肖特基势垒二极管(即半导体装置200)的随时间经过的特性变动。由此，能够提高半导体装置200的可靠性。
进而，半导体装置200中，第1层21以及第2层22除了设置在阳极电极41之上以外，还设置在n－型半导体区域31之上。因此，能够进一步提高半导体装置200的可靠性。
关于以上说明的各实施方式中的各半导体区域之间的杂质浓度的相对高低，例如能够利用SCM(扫描型静电电容显微镜)来确认。各半导体区域中的载流子浓度能够视为与在各半导体区域中活性化的杂质浓度相等。因而，关于各半导体区域之间的载流子浓度的相对高低，也能够利用SCM来确认。
关于各半导体区域中的杂质浓度，例如能够通过SIMS(二次离子质谱分析法)来测定。
以上，例示了本发明的几个实施方式，但这些实施方式是作为例子提示的，并没有要限定发明的范围。这些新的实施方式能够以其他多种形态实施，并且在不脱离发明的主旨的范围内能够进行各种省略、替换、变更等。这些实施方式及其变形例包含于发明的范围及主旨，并且包含于权利要求所记载的发明及其等同的范围。此外，上述的各实施方式能够相互组合来实施。

Claims (10)

1.一种半导体装置，其中，具备：
第1导电型的第1半导体区域，具有在第1方向上排列的第1区域以及第2区域；
第1电极，设置在上述第1区域之上；
第2导电型的第2半导体区域，设置在上述第2区域之上；
第1导电型的第3半导体区域，设置在上述第2半导体区域的一部分之上；
第2电极，设置在上述第3半导体区域之上，上述第2电极在上述第1方向上与上述第1电极分离；
第3电极，设置在上述第2半导体区域的其他的一部分以及上述第1半导体区域的一部分之上，上述第3电极与上述第1电极以及上述第2电极分离；
第1层，设置在上述第3电极之上，上述第1层包含从由钛、镍以及钒构成的组中选择的至少一个；以及
第2层，设置在上述第1层之上，上述第2层包含从由氮以及氧构成的组中选择的至少一个和硅。
2.如权利要求1所述的半导体装置，其中，
上述第1层以及上述第2层还设置在上述第1半导体区域之上以及上述第2半导体区域之上。
3.如权利要求1所述的半导体装置，其中，
还具备设置在上述第1电极之上的第3层；
上述第3层包含从由钛、镍以及钒构成的组中选择的至少一个。
4.如权利要求1所述的半导体装置，其中，
还具备设置在上述第2电极之上的第4层；
上述第4层包含从由钛、镍以及钒构成的组中选择的至少一个。
5.如权利要求1所述的半导体装置，其中，
还具备设置在上述第1区域之上的第1导电型的第4半导体区域；
上述第4半导体区域中的第1导电型的杂质浓度比上述第1半导体区域中的第1导电型的杂质浓度高；
上述第1电极设置在上述第4半导体区域之上。
6.如权利要求5所述的半导体装置，其中，
上述第1半导体区域、上述第2半导体区域、上述第3半导体区域以及上述第4半导体区域包含硅；
上述第3电极包含从由铝、钴以及钨构成的组中选择的至少一个。
7.如权利要求1所述的半导体装置，其中，
上述第1半导体区域与上述第3电极形成肖特基结。
8.一种半导体装置，其中，具备：
第1半导体区域；
第1电极，设置在上述第1半导体区域的一部分之上，上述第1电极包含从由铝、钴以及钨构成的组中选择的至少一个；
第1层，设置在上述第1半导体区域的其他的一部分之上以及上述第1电极之上，上述第1层包含从由钛、镍以及钒构成的组中选择的至少一个；以及
第2层，设置在上述第1层之上，上述第2层包含从由氮以及氧构成的组中选择的至少一个和硅。
9.如权利要求8所述的半导体装置，其中，
还具备：
第1导电型的第2半导体区域，设置在上述第1半导体区域之下；以及
第2电极，设置在上述第2半导体区域之下；
上述第1半导体区域是第1导电型；
上述第2半导体区域中的第1导电型的杂质浓度比上述第1半导体区域中的第1导电型的杂质浓度高。
10.如权利要求8所述的半导体装置，其中，
上述第1半导体区域和上述第1电极形成肖特基结。
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