CN104541373A - 用于使用工程化衬底的氮化镓电子器件的方法和系统 - Google Patents

用于使用工程化衬底的氮化镓电子器件的方法和系统 Download PDF

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Publication number
CN104541373A
CN104541373A CN201380042559.4A CN201380042559A CN104541373A CN 104541373 A CN104541373 A CN 104541373A CN 201380042559 A CN201380042559 A CN 201380042559A CN 104541373 A CN104541373 A CN 104541373A
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iii
family nitride
layer
coupled
gan
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CN104541373B (zh
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聂辉
唐纳德·R·迪斯尼
伊舍克·C·克孜勒亚尔勒
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Avoji Abc Co ltd
New Era Power System Co ltd
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A Woji Co Ltd
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Abstract

一种用于制造电子器件的方法，所述方法包括提供包括第III族氮化物籽层的工程化衬底，形成耦接至所述第III族氮化物籽层的GaN基功能层，形成电耦接至所述GaN基功能层的至少一部分的第一电极结构。该方法还包括在所述GaN基功能层的与工程化衬底相反一侧结合载体衬底，以及移除所述工程化衬底结构的至少一部分。该方法进一步包括形成电耦接至所述GaN基功能层的至少另一部分的第二电极结构以及移除所述载体衬底。

Description

用于使用工程化衬底的氮化镓电子器件的方法和系统
背景技术
功率电子产品广泛地应用于各种应用中。功率电子器件常用于电路中以改变电能的形式，例如，从交流到直流，从一个电压水平至另一电压水平，或以其他的方式。这样的器件可在宽范围的功率水平内运行，从移动设备中的毫瓦级至高压电力传输系统中的数百兆瓦。尽管功率电子产品取得了进步，但本领域仍对改进的电子系统和其运行方法存在需求。
发明内容
本发明主要涉及电子器件。更具体地，本发明涉及使用工程化衬底(engineered substrate)制造器件以提供器件性能参数的改善。该方法和技术可应用于各种化合物半导体系统中，包括垂直结型场效应晶体管(JFET)、电接触结构、二极管结构等。
根据本发明的实施方案，提供一种制造电子器件的方法。该方法包括提供包括第III族氮化物籽层的工程化衬底结构，形成耦接至第III族氮化物籽层的GaN基功能层，以及形成电耦接至GaN基功能层的至少一部分的第一电极结构。该方法还包括在该GaN基功能层的与工程化衬底结构相反一侧结合载体衬底，以及移除该工程化衬底结构的至少一部分。该方法进一步包括形成电耦接至GaN基功能层的至少另一部分的第二电极结构以及移除该载体衬底。
根据本发明另一实施方案，提供垂直第III族氮化物电子器件。该器件包括第一电接触结构，和耦接至第一电接触结构的第一导电类型的第III族氮化物外延层。该器件还包括耦接至第III族氮化物外延层的第III族氮化物外延结构和耦接至一层或更多层的第III族氮化物外延结构的第二电接触结构。
根据本发明的替代方案，提供垂直第III族氮化物JFET。该垂直第III族氮化物JFET包括器件衬底，耦接至器件衬底的界面层，耦接至界面层的第一电极结构。垂直第III族氮化物JFET还包括连接至第一电极结构的第III族氮化物外延层，外延耦接至第III族氮化物外延层的第III族氮化物漂移层，外延耦接至第III族氮化物漂移层的第III族氮化物沟道区。垂直第III族氮化物JFET进一步包括外延耦接至第III族氮化物沟道区的第III族氮化物源极区；以及相邻第III族氮化物沟道区设置的一个或更多个栅极区。
相比传统技术，通过本发明的方法实现很多益处。例如，本发明实施方案在制造高功率垂直GaN基器件(例如垂直EFTs)时采用工程化衬底。工程化衬底的使用导致在一些实施方案中成本降低。此外，一些实施方案的特征在于减少的衬底减薄和/或移除步骤。对于一些垂直器件，特别是高性能GaN基器件，衬底电阻是可观的并且会影响器件性能。为了降低与衬底相关的电阻，在初步加工后，可以减薄/移除衬底的部分或全部。本发明的实施方案采用具有预定的GaN基外延层的工程化衬底，所述GaN基外延层在移除处理衬底和接合层之后提供期望的器件特性。结合下文和附图更加具体地描述本发明的这些和其他实施方案，及其许多优势和特征。
附图说明
图1是示出根据本发明实施方案的工程化衬底的简化截面图；
图2是示出在根据本发明实施方案的工程化衬底上的外延生长的简化截面图；
图3是示出根据本发明实施方案的电极形成的简化截面图；
图4是示出根据本发明实施方案的载体晶片结合的简化截面图；
图5是示出根据本发明实施方案的处理晶片减薄的简化截面图；
图6是示出根据本发明实施方案的层的移除和电极形成的简化截面图；
图7是示出根据本发明实施方案的衬底结合的简化截面图；
图8是示出根据本发明实施方案的载体晶片的移除的简化截面图；
图9A是示出根据本发明实施方案的GaN肖特基二极管结构的简化示意图；
图9B是示出根据本发明实施方案的GaN p-n二极管结构的简化示意图；
图10是示出根据本发明实施方案的三端子GaN FET结构的简化示意图；
图11是示出根据本发明实施方案的三端子GaN双级结构的简化示意图；
图12是示出根据本发明实施方案的器件接合的简化示意图；以及
图13是示出根据本发明实施方案的电子器件的制造方法的简化流程图。
具体实施方式
本发明实施方案涉及电子器件。更具体地，本发明涉及使用工程化衬底制造器件以使得器件性能参数得到提高。该方法和技术可应用于各种化合物半导体系统中，包括垂直结型场效应晶体管(JFETs)、电接触结构、二极管结构等。
GaN基电子器件和光电器件正经历快速发展。与GaN、相关合金和异质结构相关联的期望的性能包括对可见和紫外光发射的高带隙能量，优越的传输性能(例如，高电子迁移率和饱和速度)、高击穿场以及高热导率。根据本发明的实施方案，使用在工程化衬底上形成的GaN籽层上的氮化镓(GaN)外延来制造使用传统技术不可能制造的垂直GaN基半导体器件。例如，传统生长GaN的方法包括使用异质衬底例如碳化硅(SiC)。由于GaN层和异质衬底之间在热膨胀系数和晶格常数上的差异，这会限制生长在异质衬底上的可用的GaN层的厚度。在GaN和异质衬底之间界面处的高缺陷密度进一步使得制造垂直器件(包括功率电子器件例如JFETs和其他场效应晶体管)的尝试复杂化。
另一方面，这里描述的本发明实施方案中使用GaN籽层上的同质外延GaN层来提供比传统技术和器件优越的性能。例如，对于给定的背景掺杂水平N，电子迁移率μ更高。这提供了低电阻率ρ，因为电阻率反比于电子迁移率，如式(1)所示：
ρ = 1 qμN - - - ( 1 )
其中q为元电荷。
另一个由在GaN籽层上的同质外延GaN层提供的优越性能是雪崩击穿的高临界电场。相比具有较小临界电场的材料，高临界电场使得在较小的长度L上能够支持更大的电压。电流流过较小的长度以及低电阻率得到相比其他材料更低的电阻R，因为电阻可由下式决定：
R = ρL A - - - ( 2 )
其中A是沟道或电流路径的横截面积。
一般来说，在设备关断状态下支持高电压所需要的设备的物理尺寸，和在导通状态下使电流通过具有低电阻的同一设备的能力之间存在折衷。在很多情况，在使折衷最小化而性能最大化方面，GaN比其他材料更加优选。此外，相比生长在失配衬底上的GaN层，生长在工程化衬底上的GaN籽层上的GaN层具有低的缺陷密度。该低缺陷密度会带来优越的热导率、更少的陷阱相关(trap-related)的影响，如动态导通电阻，以及更好的可靠性。
在垂直器件结构中，预期的是垂直JFET。按照掺杂水平、物理尺寸、导电类型(例如，n型或p型材料)、以及其他因素，垂直JFET可被设计为具有常断或常通的功能。常断垂直JFET由于其具有在没有电压施加到栅极时能够阻止电流流动的能力而特别有用，除了其他之外，其还可以作为功率应用中使用的垂直JEFTs的安全装置(safety feature)。
可以以各种方式制造常断垂直JFET。例如，由p+栅极可在每一侧上拦截从源极到漏极的n型电流。通过足够低的背景掺杂，以及p+栅极中由于高空穴浓度带来的高正电荷，在零偏压下沟道可能耗尽载流子或被夹断。当施加正向电压至栅极时，沟道能够被重新打开以接通器件。因此，在本发明实施方案中，由于电流通过栅极区(gated region)在源极和漏极之间垂直流动，垂直JFET指的是垂直结型场效应晶体管。
除了支持高电压、低电阻JFET应用的能力外，这里描述的GaN垂直JFETs可在其他方面不同于传统垂直JFET。例如，可采用用于制造垂直JFET的其他半导体(例如SiC)改变制造模式。此外，GaN外延层的使用可允许非均匀的掺杂剂浓度(其作为在垂直JFET不同层内的厚度的函数)，这能够使器件的性能最优化。
图1为示出根据本发明实施方案的工程化衬底10的简化截面图。如图1所示，工程化衬底10包括处理衬底100、接合层101、以及GaN基籽层102。在一个实施方案中，接合层101为氧化物层，但是，如下更全面的描述，这并非本发明实施方案所必须的。
处理衬底100在处理和加工操作中提供机械刚度以支承上覆层，并且可由单一材料制成或者由层状结构、合金结构中之一或其组合的材料组合制成。作为一个例子，处理衬底可包括金属材料、陶瓷材料、半导体材料或其结合。如对于本领域技术人员而言明显的是，工程化衬底10与硅基应用中使用的绝缘体上硅的衬底具有一些共同的特征。在一些实施方案中，在工程化衬底10的制造过程中GaN籽层102被外延剥离。在另外的实施方案中，GaN籽层为接合至接合层101、之后使用层转移工艺从衬底分离的GaN衬底的一部分。本领域技术人员能够认识到许多变化方案、修改方案和替代方案。
如本文所述，工程化衬底10可应用在制造高功率GaN基电子器件中，其使得相比传统技术成本降低，减少涉及减薄和移除GaN基衬底材料的步骤等。
图2为示出根据本发明实施方案的工程化衬底上外延生长的简化截面图。如图2所示，例如，使用金属有机化学气相沉积(MOCVD)工艺，在GaN籽层102上形成缓冲层201(例如，n+GaN缓冲层)。在例示的实施方案中，由于籽层可为高电阻的，缓冲层为重掺杂的n型以形成高导电的N+层。例如，层201可用硅或氧掺杂达到1×1017cm-3至1×1020cm-3范围内的掺杂浓度，并具有0.1μm至10μm范围内的厚度。然后在缓冲层201上形成了形成垂直电子器件的元件的漂移层301(例如n型GaN漂移层)。其他功能层401随后形成在漂移层301上，并且旨在表示适合于特定应用的各种各样的功能层。
在一些实施方案中，在制造之后，缓冲层201将作为n型接触层，漂移层301将提供适合于例如垂直JFET的器件功能。漂移层301的性能可根据需要的功能而改变。例如，为支持高电压，层301可以为具有足够厚度的相对低掺杂的材料。在一些实施方案中，层301的掺杂浓度基本上低于层201的掺杂浓度。例如，层301可具有n-导电类型、具有1×1014cm-3至1×1018cm-3的掺杂浓度。此外，掺杂浓度可以是均一的，也可以是变化的，例如，作为漂移区厚度的函数。层301的厚度可根据目标的额定电压在4μm至100μm的范围内。在一些实施例中，层301可包括两个或更多个子层，其可具有不同的物理特性(例如掺杂浓度、掺杂均一性等)。
参照图1和图2，GaN籽层102可为基本未掺杂的、补偿掺杂的(即具有基本上相等浓度的n型和p型掺杂，使得净掺杂浓度小)，或具有净n型掺杂或净p型掺杂。此外，虽然在附图1和2中示出了GaN籽层，但本发明实施方案不限于GaN籽层。其它第III-V族材料，特别是第III族氮化物材料，包含在本发明的范围内，并且其不仅可以替代所示出的GaN籽层，还可替代本发明描述的其他GaN基的层和结构。作为实例，二元第III-V族(例如，第III族氮化物)材料，三元第III-V族(例如，第III族氮化物)材料例如InGaN和AlGaN，四元第III族氮化物材料例如AlInGaN，这些材料的掺杂变体等，包括在本发明的范围内。
图3是示出根据本发明实施方案的电极形成的简化截面图。顶电极501电连接至一个或更多个其他可用的功能层401，并且实际设计与集成将取决于具体器件设计和由具体器件提供的功能。作为一个实例，顶电极501可以由一层或更多层的包括各种金属的电导体形成，以将顶电极501电耦接至电路(未示出)。
图4为示出根据本发明实施方案的载体晶片结合的简化截面图。参照图4，牺牲接合层601结合至顶电极501和其他可用功能层401的一部分，并为载体晶片701接合至材料结构提供机械支承。如下面更加具体描述的，载体晶片701使随后待使用的加工能够移除处理晶片和其他合适的层。本领域技术人员可认识到许多变化方案，修改方案和替代方案。
在一个实施方案中，用于形成牺牲接合层601的材料包括蜡、氧化物材料、有机带、适用于接合载体晶片701的其他有机或金属材料，或其组合等。典型地，牺牲接合层601是在后续加工中易于移除并提供化学侵蚀耐受性的相当软的材料。通常，牺牲接合层601将根据用于载体晶片的具体材料来选择以提供与载体晶片的良好匹配。因此，牺牲接合层601提供粘附和化学耐受性两者。
用于形成载体晶片701的材料可包括刚性衬底例如蓝宝石、碳化硅、硅等，或可包括较柔性的材料例如聚酰亚胺、塑料或带。因此，虽然载体晶片示出为晶片，但实施方案不限于晶片/衬底且本发明应在更宽的背景中来理解。载体晶片701将提供足够的刚度以在加工操作中保持外延层的完整性。
图5是示出根据本发明实施方案的处理晶片减薄的简化截面图。参照图5，图4所示的结构被反转过来，载体晶片701在底部而处理衬底100在顶部。此外，图5示出了使用例如减薄、研磨或其他移除工艺部分移除处理衬底。虽然图5中未示出，使用减薄或其他移除工艺移除接合层101和GaN基籽层102以露出GaN缓冲层201。因此，在一些实施方案中，已为GaN缓冲层提供外延生长表面的籽层，一旦完成籽层的目的(例如，提供高质量(例如单晶)的外延生长表面)即被移除。
处理衬底在高移除率的工艺中被抛光、研磨、或铣削，然后化学刻蚀、物理刻蚀、或利用化学刻蚀和物理刻蚀的组合刻蚀(例如，湿法刻蚀、CAIBE、使用ICP、RIE等的干法刻蚀)。然后使用相似的刻蚀工艺来移除接合层101和籽层102来露出缓冲层201。根据特定的材料，可使用化学刻蚀、抛光、干法刻蚀等的组合。由于GaN对大多数湿法刻蚀具有耐受性，可使用选择性刻蚀移除接合层101，该层可包括氧化物、氮化物、或其他合适的材料，其在化学刻蚀中以对下层GaN基籽层102具有选择性的方式被移除。因此，在一些实施方案中可使用抛光和化学刻蚀的组合移除处理衬底100和接合层101(例如，接合氧化物)以由此露出GaN籽层102。GaN籽层可随后使用适于移除GaN基材料的干法刻蚀(例如ICP)移除，且GaN缓冲层201可足够厚以允许过度刻蚀情况下的加工余量。根据掺杂类型及籽层102的结构，也可使用湿法刻蚀来移除籽层102而基本不刻蚀缓冲层201。本领域技术人员可认识到许多变化方案、修改方案和替代方案。
图6是示出根据本发明实施方案的层的移除和电极形成的简化截面图。对比图5和图6，如上所述已经移除了接合层和籽层102以露出缓冲层201，并且已沉积底电极801以提供与n+GaN缓冲层201的电接触。在一些实施方案中，在移除籽层后，缓冲层201提供了对GaN晶体结构的氮表面的接近。因为利用低温金属沉积工艺氮表面能够形成良好的欧姆接触，底电极801的形成可以为低温工艺。在一些实施方案中，底电极801可在室温下沉积而不需要沉积后的退火。各种技术可被用来形成接触，包括金属蒸镀、溅射、镀覆、及其组合等。参考图6，应注意到采用形成底电极801的低温工艺，使得能够使用牺牲接合层601的材料，这些材料在使用高温金属化工艺来形成底电极801的情况下不一定能够使用。有关电极和金属化的更多的说明提供在2012年7月18日提交的题为“具有可焊接的背金属的GaN功率器件(GaN Power Device with SolderableBack Metal)”的美国专利申请第13/552,365号中，其全部公开内容通过引用并入本文用于所有目的。
图7是示出了根据本发明实施方案的衬底结合的简化截面图。如图7所示，器件衬底1001(由于以下描述的性能也被称为导电导热衬底(electrical and thermal substrate))利用接合界面层901结合至底电极801。导电导热衬底1001为使用外延层制造的器件提供导电性以及导热性以从有源器件导出热量。作为实例，导电导热衬底1001可以包括各种材料，包括钼、铜、钨、类似的金属、金属合金，其组合等。如下所述，导电导热衬底1001还在移除载体晶片701后为外延器件层提供机械支承。可使用接合界面层，结合或补充以钎焊、烧结或其他合适工艺，将导电导热衬底结合至图示的结构。
作为使用导电导热衬底的替代方案，可将底电极801形成(例如镀覆)为足够的厚度以为外延层提供机械支承。例如，底电极801可以包括铜、镍、铝、类似的金属或数种金属的合金。在一个实施方案中，层801可包括由化学和/或电化学镀覆工艺形成的25μm至100μm厚的铜层。在一些实施方案中，顶电极501的厚度和组成可与底电极801相似，以平衡由这些电极和GaN器件层的热膨胀系数(TCE)的失配导致的机械应力。因此，根据特定的实施方式，可使用导电导热衬底，然而在其他实施方案中，使用替代技术来提供期望的机械、电学、热学性能特点。
图8是示出了根据本发明实施方案的载体晶片的移除的简化截面图。如图8所示，载体晶片已与牺牲接合层一起被剥离或移除，以露出顶电极和部分其他合适的功能层。在牺牲接合层包含蜡的实施方案中，可使用有机溶剂移除该层。如上所述，虽然图8中示出了导电导热衬底，但其不是本发明必须的，可使用一层或更多层的镀覆，包括底电极801的额外镀覆来为器件层提供机械支承。在特定的实施方案中，镀覆至少一层顶电极或底电极至足够厚度以提供机械支承，例如顶电极为25μm的铜，底电极为25μm的铜。在这个特定实施方案中，可利用顶电极501和底电极801的应力平衡以使外延器件层处于压应力中。
在制造工艺过程中利用工程化衬底使得器件结构基本上无衬底材料，因为传统器件为特征的GaN衬底已被GaN缓冲层201所取代，其相比传统衬底可以非常薄。例如，块体GaN晶片根据晶片直径可具有300μm至500μm的起始厚度。由于衬底对于电流流动和热流动是串联的，其显著增加了电阻和热阻。在传统的对块体衬底上的垂直功率器件的加工中，优选减薄衬底来降低热阻和电阻。但是，最终衬底的最小厚度受到处理和机械应力问题的限制。在目前技术的垂直功率器件中，最终衬底的厚度可在50μm至150μm的范围内。根据本文所述的实施方案，最终“衬底”的等效厚度与N+GaN缓冲层301的厚度相同，其可在1μm至10μm的范围内。因此，本发明提供垂直GaN功率器件，其相比于在块体GaN衬底上制造的垂直GaN功率器件具有低得多的电阻和热阻。
图9A为示出根据本发明实施方案的GaN肖特基二极管结构的简化示意图。图9A示出的GaN肖特基二极管结构为双端子GaN基器件的实例，其采用了使用本文所述的工程化衬底工艺制造的外延结构。有关肖特基二极管结构的另外的描述提供在2011年9月2日提交的美国专利申请第13/225,345号，和2011年11月4日提交的美国专利申请第13/289,219号中，其全部公开内容通过引用并入本文用于所有目的。如图9A所示，肖特基接触形成为顶电极，其提供对于轻掺杂的n型GaN基漂移层的肖特基势垒。
通过使用工程化衬底来制造图9A所示的器件，和本文所述的其他器件，在底电极和肖特基接触之间仅存在外延材料。如关于本文所述的其他器件的讨论，本发明的实施方案利用了工程化衬底来移除通常存在于传统器件中的衬底材料。因此，如图9A所示的器件中，缓冲层和漂移层两者均为使用籽层生长的外延层，随着籽层随后被移除，导致在接触之间的层中仅存在外延材料。由于器件结构没有衬底材料，材料性能由外延生长工艺限定，其为器件设计和制造提供更多的控制。
衬底材料的移除使得能够制造比传统器件更薄的器件结构，例如，缓冲层厚度(即，从底电极至第III族氮化物漂移层测得的距离)小于5μm，小于4μm，小于3μm，小于2μm，小于1μm，小于0.5μm，小于0.1μm等，其适合于在原始籽层与漂移层之间仅有缓冲层的结构。此外，因为包括缓冲层和漂移层的第III族氮化物外延层为硅掺杂的n型层，而不是用于n型GaN衬底的传统掺杂剂的氧掺杂的层，所以本发明实施方案与传统器件形成对比。因此图示的器件中使用的缓冲层的特征在于氧浓度低于5×1017cm-3(例如，低于2×1017cm-3)，其为与GaN衬底关联的氧浓度。此外，缓冲层的硅浓度可大于1×1018cm-3。因此，由于不存在衬底材料，使用工程化衬底制造的器件提供低电阻、低热阻等。
图9B为示出根据本发明实施方案的GaN p-n二极管结构的简化示意图。图9B示出的GaN p-n结二极管结构为双端子GaN基器件的另一实例，其采用了本文所述的使用了工程化衬底工艺制造的外延结构。有关p-n结二极管结构的另外的描述提供在2011年9月2日提交的美国专利申请第13/225,345号，和2011年11月4日提交的美国专利申请第13/289,219号中，其全部公开内容通过引用并入本文用于所有目的。如图9B所示，p型欧姆接触形成为顶电极，提供对于p型GaN基层的欧姆接触，该层与轻掺杂的n型GaN基漂移层形成p-n结。
除了肖特基二极管和p-n结二极管器件，合并的PIN、肖特基(MPS)二极管结构可使用本文所述的工程化衬底制造。有关MPS二极管的另外的描述提供在2011年11月18日提交的美国专利申请第13/300,028号中，其全部公开内容通过引用并入本文用于所有目的。
图10为示出根据本发明实施方案的三端子GaN FET结构的简化示意图。图10示出的三端子器件为垂直结型场效应晶体管(JFET)，其可以使用2011年8月4日提交的美国专利申请第13/198,655号中具体讨论的技术来制造，其全部公开内容通过引用并入本文用于所有目的。如图10所述，所述垂直JFET包括轻掺杂的n型GaN基漂移层1050和轻掺杂的GaN基沟道区1051。栅极材料1060(例如p型GaN基层)通过施加电压至金属1061而被施加偏压，其形成与p型栅极材料的欧姆接触。源极区1052通过施加电压至源极金属1053而被施加偏压，其形成与重掺杂n型源极区的欧姆接触。由于图10所示的结构在制造过程中采用了工程化衬底，因为底电极连接至重掺杂的n型GaN缓冲层和漂移层1050，所以与GaN衬底关联的电压降减小。
图11是示出了根据本发明实施方案的三端子GaN双极结构的简化示意图。参照图11，功能层包括设置于轻掺杂n型漂移层1150和重掺杂发射极结构之间的重掺杂p型基底1151，该轻掺杂n-型漂移层1150连接至底电极801(集电极)，该重掺杂发射极结构包括n型AlxGa1-xN层1160、n型GaN层1161以及接触n型GaN层1161的欧姆金属接触1162(发射极)。进入基底1151、利用接触p-GaN层的欧姆接触1152偏置的电流被放大以产生集电极和发射极电流。虽然图11中示出了NPN BJT，但这不是本发明必须的，也可采用PNP设计。选择BJT的各层的厚度和掺杂来提供适用于特定设计的预定器件特性。本领域技术人员可认识到许多变化方案，修改方案和替代方案。
图12为示出根据本发明实施方案的器件接合的简化示意图。图12呈现出使用图8中所示的导电导热衬底的替代设计。如图12所示，示出了GaN缓冲层201、GaN漂移层301、其他可应用的功能层401以及顶电极(#1和#2)且可将其与图3中的层相对比。在图12所示的实施方案中制造多个顶电极1201和1202。然后使用接合物(bond)1210将该结构倒装接合至衬底1220。因此，可在功能层形成之后使用倒装接合将该结构接合至衬底1220。然后在底电极1230形成之前将处理衬底100和接合层与籽层一起移除。
在使用三端子器件的一些实施方案中，衬底1220可包括连接至接合区域以为第一顶电极1201和第二顶电极1202提供单独电路的导线轨迹(wire trace)和/或绝缘互连。一个实施方案是使用直接接合铜(DBC)的设计。顶电极可使用如上所述的镀覆形成。因此，使用图12所示的设计，通过衬底可提供与衬底的电接触和移除器件热量的热传导两者。
图13为示出根据本发明的实施方案电子器件制造方法的简化流程图。方法1300包括提供包括第III族氮化物籽层的工程化衬底结构(1310)，以及形成耦接至第III族氮化物籽层的GaN基功能层。在一个实施方案中，第III族氮化物籽层包括GaN材料，例如在层转移工艺中移除的GaN衬底的一部分，例如n型GaN基材料。在一些实施方案中，该方法包括外延生长耦接至第III族氮化物籽层的第III族氮化物缓冲层，和耦接至第III族氮化物缓冲层的第III族氮化物漂移层。在这些实施方案中，该方法可额外包括外延生长GaN基功能层以形成GaN基功能层。
该方法还包括形成电耦接至GaN基功能层的至少一部分的第一电极结构(1314)以及在GaN基功能层的与工程化衬底结构相反一侧结合载体衬底(1316)。
将载体晶片结合至GaN基功能层可包括形成耦接至GaN基功能层中之一的至少一部分的电极结构，形成耦接至该GaN基功能层中之一的另一部分以及该电极结构至少一部分的牺牲接合层，以及将载体衬底接合至牺牲接合层。
该方法还包括移除工程化衬底结构的至少一部分(1318)以及形成电耦接至GaN基功能层的至少另一部分的第二电极结构(1320)。此外，该方法包括移除载体衬底(1322)。在具体的实施方案中，移除载体衬底包括移除如上所述的牺牲接合层。如本文描述的，工程化衬底可包括耦接至第III族氮化物籽层的接合层和处理晶片。在这个实施方案中，移除工程化衬底结构的至少一部分可以包括机械移除处理晶片，化学刻蚀接合层，以及物理刻蚀第III族氮化物籽层。因此，本实施方案提供了基本没有衬底材料的结构，而是使用外延生长材料来形成器件层。
在一些实施方案中，该方法还可包括在移除载体衬底前将器件衬底结合至第二电极，然而在另外一些实施方案中，镀覆第二衬底至一定厚度使得不使用器件衬底，而使第二电极的结构在制造和包装工艺过程中为其他层提供足够的机械支承。
应当理解图13中所示的具体步骤提供了根据本发明实施方案的制造电子器件的具体方法。也可根据变化方案实施其他的步骤顺序。例如，本发明的替代方案可按不同顺序实施上面列出的步骤。此外，图13中所示的单独步骤可包括多个子步骤，其可按适合于该独立步骤的多种顺序实施。另外，根据具体的应用可增加或删减额外的步骤。本领域技术人员可认识到许多变化方案、修改方案和替代方案。
还应理解本文所述的实施方案和实施例仅用于示例性的目的并且其可提示本领域技术人员进行各种调整和变换，上述调整和变换均包含在本发明的范围和精神内并包含在权利要求的保护范围里。

Claims (24)

1.一种用于制造电子器件的方法，所述方法包括：
提供包括第III族氮化物籽层的工程化衬底结构；
形成耦接至所述第III族氮化物籽层的GaN基功能层；
形成电耦接至所述GaN基功能层的至少一部分的第一电极结构；
在所述GaN基功能层的与所述工程化衬底结构相反一侧结合载体衬底；
移除所述工程化衬底结构的至少一部分；
形成电耦接至所述GaN基功能层的至少另一部分的第二电极结构；以及
移除所述载体衬底。
2.根据权利要求1所述的方法，还包括在移除所述载体衬底之前将器件衬底结合至所述第二电极。
3.根据权利要求1所述的方法，其中所述第III族氮化物籽层包括GaN材料。
4.根据权利要求1所述的方法，其中所述第III族氮化物籽层包括n型GaN基材料。
5.根据权利要求1所述的方法，还包括外延生长耦接至所述第III族氮化物籽层的第III族氮化物缓冲层和耦接至所述第III族氮化物缓冲层的第III族氮化物漂移层。
6.根据权利要求5所述的方法，其中形成GaN基功能层包括外延生长所述GaN基功能层。
7.根据权利要求1所述的方法，其中将所述载体晶片结合至所述GaN基功能层包括：
形成耦接至所述GaN基功能层中一层的至少一部分的电极结构；
形成耦接至所述GaN基功能层中的所述一层的另一部分和所述电极结构的至少一部分的牺牲接合层；以及
将所述载体晶片接合至所述牺牲接合层。
8.根据权利要求7所述的方法，其中移除所述载体衬底包括移除所述牺牲接合层。
9.根据权利要求1所述的方法，其中所述工程化衬底包括耦接至所述第III族氮化物籽层的接合层和处理晶片，并且其中移除所述工程化衬底结构的至少一部分包括机械移除所述处理晶片，化学刻蚀所述接合层以及物理刻蚀所述第III族氮化物籽层。
10.一种垂直第III族氮化物电子器件，包括：
第一电接触结构；
耦接至所述第一电接触结构的第一导电类型的第III族氮化物外延层；
耦接至所述第III族氮化物外延层的第III族氮化物外延结构；以及
耦接至所述第III族氮化物外延结构的一层或更多层的第二电接触结构。
11.根据权利要求10所述的垂直第III族氮化物电子器件，其中所述第III族氮化物外延层包括n型GaN层。
12.根据权利要求10所述的垂直第III族氮化物电子器件，其中所述第一导电类型包括n型。
13.根据权利要求10所述的垂直第III族氮化物电子器件，其中所述第III族氮化物外延结构包括n型GaN层以及一个或更多个另外的GaN层。
14.根据权利要求10所述的垂直第III族氮化物电子器件，其中所述第III族氮化物外延层和所述第III族氮化物外延结构的厚度为约1μm至约100μm。
15.根据权利要求10所述的垂直第III族氮化物电子器件，还包括支承所述第一电接触结构的器件衬底。
16.一种垂直第III族氮化物JFET，包括：
器件衬底；
耦接至所述器件衬底的界面层；
耦接至所述界面层的第一电极结构；
连接至所述第一电极结构的第III族氮化物外延层；
外延耦接至所述第III族氮化物外延层的第III族氮化物漂移层；
外延耦接至所述第III族氮化物漂移层的第III族氮化物沟道区；
外延耦接至所述第III族氮化物沟道区的第III族氮化物源极区；以及
相邻所述第III族氮化物沟道区设置的一个或更多个栅极区。
17.根据权利要求16所述的垂直第III族氮化物JFET，还包括耦接至所述第III族氮化物源极区的源电极结构。
18.根据权利要求16所述的垂直第III族氮化物JFET，还包括耦接至所述一个或更多个栅极区的一个或更多个栅电极结构。
19.根据权利要求16所述的垂直第III族氮化物JFET，其中所述界面层的厚度为约0.1μm至约1μm。
20.根据权利要求16所述的垂直第III族氮化物JFET，其中所述第III族氮化物漂移层的厚度为约1μm至约100μm。
21.根据权利要求16所述的垂直第III族氮化物JFET，其中从所述第一电极结构至所述第III族氮化物漂移层的测得的距离小于10μm。
22.根据权利要求16所述的垂直第III族氮化物JFET，其中所述第III族氮化物外延层和所述第III族氮化物漂移层为硅掺杂的n型层。
23.根据权利要求22所述的垂直第III族氮化物JFET，其中所述第III族氮化物外延层和所述第III族氮化物漂移层的特征在于氧浓度小于2×1018cm-3。
24.根据权利要求22所述的垂直第III族氮化物JFET，其中所述第III族氮化物外延层的特征在于硅浓度大于1×1018cm-3。
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