CN104241260B - 具有高电子迁移率晶体管和单片集成半导体二极管的高压级联二极管 - Google Patents

具有高电子迁移率晶体管和单片集成半导体二极管的高压级联二极管 Download PDF

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CN104241260B
CN104241260B CN201410266969.3A CN201410266969A CN104241260B CN 104241260 B CN104241260 B CN 104241260B CN 201410266969 A CN201410266969 A CN 201410266969A CN 104241260 B CN104241260 B CN 104241260B
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CN104241260A (zh
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G·普雷科托
C·奥斯特梅尔
O·哈伯莱恩
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Infineon Technologies Austria AG
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Abstract

本发明提供了包括HEMT和Si肖特基二极管的、具有超过300V的击穿电压的级联二极管的一个实施例。HEMT包括栅极、漏极、源极和二维电子气沟道区，该二维电子气沟道区连接源极和漏极并且由栅极控制。HEMT具有超过300V的击穿电压。Si肖特基二极管与HEMT单片集成。Si肖特基二极管包括连接至HEMT的源极的阴极、以及连接至HEMT的栅极的阳极。Si肖特基二极管具有低于300V的击穿电压和低于或等于0.4V的正向电压。Si肖特基二极管的阳极形成级联二极管的阳极，HEMT的漏极形成级联二极管的阴极。

Description

具有高电子迁移率晶体管和单片集成半导体二极管的高压级 联二极管
技术领域
本申请涉及高压二极管，并且更具体地涉及由与HEMT级联在相同裸片上的低压硅基二极管形成的高压二极管。
背景技术
最高性能的Si功率二极管是Si肖特基二极管。与其他类型的Si功率二极管相比，Si肖特基二极管具有低的反向恢复时间，并且也具有最低的正向电压降(0.4V至0.3V)。虽然与其他二极管技术相比Si肖特基二极管具有低正向损耗和可以忽略不计的切换损耗的优势，但是硅的窄带隙制约了其在最大电压为约200V的使用。已经通过将低压Si肖特基二极管与高压AlGaN/GaN HEMT(高电子迁移率晶体管)级联，而实现了具有明显高于200V的击穿电压的功率二极管。这类级联二极管具有Si肖特基二极管的低阈值电压优势以及GaN的高电流密度优势。
级联二极管的功能由使电位在反方向上增加直到高压HEMT夹断(在这种情况下HEMT为常开器件)的Si肖特基二极管提供。在在Si肖特基二极管的阴极侧上不出现该最小偏差的情况下，高电压HEMT导通。因此，级联二极管的整体切换速度可以受益于高压HEMT和快速Si肖特基二极管。然而，传统的级联二极管将低压Si肖特基二极管和高压HEMT实施在两个分离的裸片(芯片)上，一个裸片包括高压GaN HEMT并且另一裸片包括低压Si肖特基二极管。两个裸片经由包括位于裸片之间的键合或夹式连接的共同的封装组合在一起。封装中的这些连接导致降低整个级联电路的动态行为的不希望的寄生电感和电容。
发明内容
根据级联二极管的一个实施例，级联驱动器包括半导体二极管、III族氮化物半导体本体、以及具有栅极、漏极、源极和连接源极和漏极的沟道的HEMT。HEMT的沟道由栅极控制，并且由在III族氮化物半导体本体的具有不同带隙的两种材料之间的结形成。半导体二极管与HEMT单片集成。半导体二极管具有连接至HEMT的源极的阴极以及连接至HEMT的栅极的阳极。半导体二极管的阳极形成级联二极管的阳极，HEMT的漏极形成级联二极管的阴极。
根据具有超过300V的击穿电压的级联二极管的一个实施例，级联驱动器包括HEMT，该HEMT包括栅极、漏极、源极和二维电子气沟道区，该二维电子气沟道区连接源极和漏极并且由栅极控制。HEMT具有超过300V的击穿电压。级联驱动器还包括与HEMT单片集成的Si肖特基二极管，Si肖特基二极管包括连接至HEMT的源极的阴极、以及连接至HEMT的栅极的阳极。Si肖特基二极管具有低于300V的击穿电压和低于或等于0.4V的正向电压。Si肖特基二极管的阳极形成级联二极管的阳极，而HEMT的漏极形成级联二极管的阴极。
根据制造级联二极管的方法的一个实施例，该方法包括：在III族氮化物半导体本体中形成HEMT，该HEMT具有栅极、漏极、源极和连接源极和漏极的沟道，该沟道由栅极控制并且由在III族氮化物半导体本体的具有不同带隙的两种材料之间的结形成；将半导体二极管与HEMT单片集成，该半导体二极管具有连接至HEMT的源极的阴极以及连接至HEMT的栅极的阳极；将级联二极管的阳极端子连接至半导体二极管的阳极；并且将级联二极管的阴极端子连接至HEMT的漏极。
本领域的技术人员基于阅读以下详细说明并且查看了附图，将看出额外的特征和优点。
附图说明
附图中的部件不一定按比例绘制，而是将重点放在说明本发明的原理上。此外，在附图中，相似的附图标记表示对应的部件。在附图中：
图1图示了包括与HEMT单片集成在相同裸片上的半导体肖特基二极管的级联二极管的示意图。
图2图示了包括与HEMT单片集成在相同裸片上的纵向Si肖特基二极管的级联二极管的一个实施例的部分截面图。
图3图示了包括与HEMT单片集成在相同裸片上的纵向Si肖特基二极管的级联二极管的另一实施例的部分截面图。
图4图示了包括与HEMT单片集成在相同裸片上的纵向Si肖特基二极管的级联二极管的又一实施例的部分截面图。
图5图示了包括与HEMT单片集成在相同裸片上的纵向Si肖特基二极管的级联二极管的再一实施例的部分截面图。
图6图示了包括与HEMT单片集成在相同裸片上的纵向Si肖特基二极管的级联二极管的还一实施例的部分截面图。
图7图示了包括与HEMT单片集成在相同裸片上的纵向Si p-n结二极管的级联二极管的一个实施例的部分截面图。
图8图示了包括与HEMT单片集成在相同裸片上的纵向Si p-n结二极管的级联二极管的另一实施例的部分截面图。
图9图示了包括与HEMT单片集成在相同裸片上的横向半导体二极管的级联二极管的一个实施例的部分截面图。
图10图示了包括与HEMT单片集成在相同裸片上的横向半导体二极管的级联二极管的另一实施例的部分截面图。
具体实施方式
图1图示了级联二极管100的示意图。如图1中的虚线框所指示，级联二极管100包括HEMT以及与HEMT单片集成在相同裸片上的半导体二极管(D)。半导体二极管的阴极(C)连接至HEMT 的源极(S)，半导体二极管的阳极(A)连接至HEMT的栅极(G)。半导体二极管的阳极形成级联二极管100的阳极(“阳极”)，HEMT的漏极(D)形成级联二极管100的阴极(“阴极”)。这类单片集成构造产生了具有半导体二极管的低阈值电压优势以及HEMT的高电流密度和高击穿电压优势的级联二极管100，同时消除了会降低级联二极管100的动态行为的不希望的寄生封装电感和电容。
一般说来，可以利用任意合适的III族氮化物技术(诸如GaN)来实现HEMT。可以利用相同或不同的半导体技术(如HEMT)来形成半导体二极管。例如在具有AlGaN势垒区和GaN缓冲区的HEMT的情况下，半导体二极管可以是GaN二极管或MIS(金属绝缘体半导体)栅控二极管。在MIS栅控二极管的情况下，MIS栅控二极管基于常断型HEMT设计(例如，执行栅极凹陷以得到常断条件)。然而，MIS栅控二极管的栅极电连接至二极管的源极，该源极形成阳极。这样，当MIS栅控二极管的源极(阳极)和漏极(阴极)之间的反向电压超过二极管的阈值电压时，MIS栅控二极管传导电流。MIS栅控二极管的阈值电压可以小于HEMT的阈值电压。当漏极的电位相对于源极而言为小负电压时，沟道在反方向上在MIS栅控二极管的栅极电极下打开。在III-V半导体中，MIS栅控二极管的绝缘体可以为氮化物而非氧化物。
备选地，半导体二极管可以为硅基二极管，诸如Si肖特基二极管或Si p-n结二极管。在另一实施例中，半导体二极管可以为SiC肖特基二极管。Si和SiC技术可以容易地与III族氮化物技术(诸如GaN)集成，以形成包括与HEMT单片集成在相同裸片上的半导体二极管的级联二极管100，如下文详细描述的。
术语HEMT通常也称作HFET(异质结场效应晶体管)、MODFET(调制掺杂FET)和MESFET(金属半导体场效应晶体管)。术语HEMT、HFET、MESFET和MODFET在本文中可以交换地使用，指具有在两种不同带隙材料之间的结(即，异质结)作为沟道的任意基于III族氮化物的化合物半导体晶体管。例如，GaN可以与AlGaN 或InGaN结合以形成沟道。化合物半导体器件可以具有AlInN/AlN/GaN势垒层、间隔层、缓冲层结构。
具体地针对GaN技术，极化电荷和应变效应的存在导致二维载流子气的实现，该二维载流子气是由很高的载流子密度和载流子迁移率表征的二维电子或空穴反型层。这类二维载流子气(诸如2DEG(二维电子气)或2DHG(二维空穴气))在例如GaN合金势垒区和GaN缓冲区之间的界面附近形成HEMT的导电沟道区。可以在GaN缓冲区和GaN合金势垒区之间设置的薄(例如1-2nm)AlN层，以使合金散射最小化并且增强2DEG迁移率。广义上讲，本文所描述的HEMT可以由任意二元、三元或四元III族化合物半导体材料形成，其中能带不连续性主导器件构思。
图2图示了包括高压级联二极管100的裸片的一个实施例的部分截面图。该裸片包括布置在III族氮化物半导体本体200中的HEMT。HEMT具有栅极(“栅极”)、源极(“源极”)和漏极(“漏极”)。HEMT的栅极、源极和漏极区可以包括在GaN基III族氮化物材料中产生n型掺杂的硅基区等掺杂区、金属区，或掺杂区和金属区的组合。HEMT的栅极、源极和漏极区的形成在半导体技术领域中是众所周知的，并且因此对此不作进一步解释。
根据本实施例，在具有(111)晶向的Si衬底202上布置III族氮化物半导体本体200。在Si衬底202上形成一个或多个过渡层204(诸如AlN)。在一个或多个过渡层204上形成缓冲区206(诸如GaN)；在缓冲区206上形成势垒区208(诸如GaN合金(如AlGaN或InGaN))；并且在势垒区208上形成钝化层210(比如SiN)。势垒区和缓冲区206、208包括具有不同带隙的III族氮化物半导体本体200的材料，并且因而引起了HEMT的根据材料类型为2DEG或2DHG的沟道212，如本文之前所解释的。沟道212将HEMT的源极和漏极连接，并且由栅极控制。在本实施例中，HEMT常开，即必须向栅极施加负栅极电压以便在栅极下断开沟道212并且断开HEMT。通常，出于制造器件之目的，在Si衬底202上可以形成任 意二元、三元或四元III族氮化物化合物半导体层204、206、208。在生长衬底(诸如，Si衬底202)上形成这类III族化合物半导体层204、206、208在半导体技术领域是众所周知的，并且因此对此不作进一步解释。
级联二极管裸片进一步包括与HEMT单片集成在相同裸片上的半导体二极管。在本实施例中，半导体二极管是利用不同于HEMT的半导体技术形成的。具体而言，Si衬底202为n型掺杂，并且金属化结构214布置在Si衬底202的背离III族氮化物半导体本体200的一侧203上。根据本实施例，半导体二极管为Si肖特基二极管。由n型掺杂Si衬底202形成Si肖特基二极管的阴极，由布置在Si衬底202的背侧203上的金属化结构214形成Si肖特基二极管的阳极。如此，背侧金属化结构214形成肖特基接触。
导电欧姆塞(“欧姆塞”)216延伸穿过III族氮化物半导体200，并且将HEMT的源极连接至Si衬底202。塞216可以由金属或多晶硅制成，并且通过蚀刻出穿过III族氮化物半导体200到达Si衬底202的开口并且填充该开口来形成。塞216可以具有绝缘侧壁215，以使塞216的导电部分与相邻的半导体材料200隔离。塞216完成在HEMT的源极和半导体二极管的阴极之间的级联连接。
备选地，可以使用SiC衬底而非Si衬底202，并且半导体二极管则可以为SiC肖特基二极管而非Si肖特基二极管。在又一实施例中，半导体二极管可以为GaN二极管或MIS栅控二极管，与HEMT形成在相同III族氮化物半导体本体200中。在以上每种情况下，半导体二极管的阳极都形成高压级联二极管的阳极，并且HEMT的漏极都形成高压级联二极管的阴极，如图1所示。
可以通过在斜切的Si(100)或Si(110)衬底而非Si(111)衬底上通过分子束外延和金属有机气相外延形成III族氮化物半导体本体200，来形成级联二极管的裸片。备选地，预生长的GaN外延层可以通过去除原来的衬底，并且随后例如经由Au/In/Au键合层、PdIn3和AuGe中间层、或SiO2中间层而与Si(100)衬底键合，而 转移到Si(100)衬底上。在又一实施例中，可以通过衬底键合和回蚀刻工艺而形成包括Si(100)和GaN的衬底。通常，这类技术及其他技术均可以用于实现与HEMT单片集成在相同裸片上的半导体二极管，以形成高压级联二极管。
在GaN二极管与HEMT单片集成以在相同裸片上实现图1中的级联二极管的情况下，半导体二极管的正向电压约为1V至0.8V。在MIS栅控二极管与HEMT单片集成以在相同裸片上实现图1中的级联二极管的情况下，半导体二极管的正向电压可以低于0.8V。可以通过利用其中每个都具有约0.7V至0.6V的正向电压的Si p-n结二极管或SiC肖特基，而提高级联二极管的性能。可以通过利用具有约0.4V或更低的正向电压的Si肖基特二极管，而更进一步提高级联二极管的性能。Si肖基特二极管具有低于300V的击穿电压，例如通常为200V或更低。相反地，与半导体二极管单片集成的HEMT具有超过300V的击穿电压。例如，在如图2所示的横向GaN HEMT的情况下，横向HEMT可以具有约600V甚至更高的击穿电压。可以使用纵向或准纵向HEMT，但是由于漂移区域更薄而具有更低的击穿电压。
图3图示了图2所示裸片的部分截面图，其中HEMT的栅极通过键合接线、带或夹220连接至引线框架218。引线框架218具有用于完成至半导体二极管的阳极(即，背侧金属化结构214)的电连接的导电通路，形成了如图1所示的级联二极管连接。
图4图示了图2所示裸片的部分截面图，其中HEMT的栅极经由导电塞222连接至半导体二极管的阳极(即，背侧金属化结构214)。塞222延伸穿过III族氮化物半导体本体200和Si衬底202到达背侧金属化结构214，并且经由布置在裸片正侧201上的金属层或夹224将HEMT的栅极连接至半导体二极管的阳极。导电塞222具有用于将塞222与相邻的半导体材料200、202隔离的绝缘侧壁226。
图5图示了具有高压级联二极管的裸片的另一实施例的部分截 面图。图5所示实施例与图2所示实施例相似，然而图5中，在Si衬底202的与背侧金属化结构214相邻的第一区228中Si衬底202的n型掺杂的浓度较低，而在Si衬底202的由第一(更轻掺杂)区228与背侧金属化结构214间隔开的第二区230中Si衬底202的n型掺杂的浓度较高。例如，Si衬底202的较高掺杂区230可以具有1017至1020cm-3的掺杂浓度，而Si衬底202的较轻掺杂区228可以具有1014至1016cm-3的掺杂浓度。可以通过背侧外延工艺在较高掺杂区230上形成较轻掺杂区228。通常，这类构造导致在背侧金属化结构214和Si衬底202之间的更优的肖基特界面。
图6图示了具有高压级联二极管的裸片的另一实施例的部分截面图。图6所示实施例与图2所示实施例相似，然而，Si衬底202为p型而不是n型。在这类p型衬底202的情况下，肖基特接触位于HEMT源极侧，以便级联二极管如图1所图示发挥作用。因此，可以利用与p型Si衬底202连接的金属塞(“肖特基BD塞”)216来建立肖基特接触。根据本实施例，背侧金属化结构214是欧姆的，从而Si肖基特二极管的阴极由金属塞216形成，而二极管的阳极由p型掺杂Si衬底202形成。
图7图示了具有高压级联二极管的裸片的又一实施例的部分截面图。图7所示实施例与图6所示实施例相似，然而将HEMT的源极连接至p型Si衬底202的塞(“n型多晶硅塞”)216包括n掺杂多晶硅。根据本实施例，半导体二极管为Si p-n结二极管。Si p-n结二极管的阴极由n掺杂多晶硅塞216形成，而Si p-n结二极管的阳极由p型掺杂Si衬底202形成。多晶硅基p-n结的受限的反向耗尽需要足够高的阈值(Vth)电压(即，Vth<0)，以维持级联功能。备选地，p-n结可以实施在晶片背侧203处，而非部分地在塞216中。
图8图示了具有高压级联二极管的裸片的另一实施例的部分截面图。图8所示实施例与图7所示实施例相似，然而Si p-n结二极管完全形成在将HEMT的源极连接至p型Si衬底202的塞216中。根据本实施例，塞216包括与HEMT的源极接触的n掺杂多晶硅区 (“n型多晶硅”)232以及通过n掺杂多晶硅区232与HEMT的源极间隔开的p掺杂多晶硅区(“p型多晶硅”)234。Si p-n结二极管的阴极由塞216的n掺杂多晶硅区232形成，而Si p-n结二极管的阳极由塞216的p型掺杂多晶硅区234形成。
本文前述的级联二极管实施例利用了与HEMT单片集成在相同裸片上的纵向半导体。备选地，可以将横向半导体二极管与HEMT单片集成在相同裸片上。例如，可以利用多晶硅沉积至源极金属电极和栅极金属电极之上或旁边，而实现横向二极管的集成。可以在形成源极金属电极或栅极金属电极之前或之后沉积多晶硅。如果在形成源极电极和栅极电极之前沉积多晶硅，那么多晶硅可以通过肖基特接触连接至HEMT源极，并且通过欧姆接触与HEMT栅极接触。
图9图示了与HEMT单片集成在相同裸片上以形成图1所示高压级联二极管的横向半导体二极管的一个实施例的部分截面图。横向半导体二极管布置在III族氮化物半导体本体200的具有HEMT的栅极的一侧上。横向半导体二极管包括：布置在III族氮化物半导体本体200的正侧201上的重度n掺杂(n++)多晶硅区300、与重度n掺杂多晶硅区300相邻的轻度n掺杂(n-)多晶硅区302、位于重度n掺杂多晶硅区300上的欧姆接触304、以及位于轻度n掺杂多晶硅区302上的肖基特接触306。重度n掺杂多晶硅区和轻度n掺杂多晶硅区300、302可以通过标准的沉积、掩膜处理和掺杂工艺形成，并且因此不再对此作进一步解释。HEMT的源极经由夹、键合线、带或其他类型的电连接器308连接至欧姆接触，而HEMT的栅极经由另一夹、键合线、带或其他类型的电连接器310连接至肖基特接触306，以完成图1所示的级联连接。在图9中，将生成的级联二极管的阳极和阴极分别标上“阳极”和“阴极”。
图10图示了与HEMT单片集成在相同裸片上以形成图1所示高压级联二极管的横向半导体二极管的另一实施例的部分截面图。横向半导体二极管包括：布置在III族氮化物半导体本体200的正侧201上的重度p掺杂(p++)多晶硅区312、与重度p掺杂多晶硅区312 相邻的轻度p掺杂多晶硅区314、位于重度p掺杂多晶硅区312上的欧姆接触316、以及位于轻度p掺杂多晶硅区314上的肖基特接触318。重度p型掺杂多晶硅区和轻度p型掺杂多晶硅区312、314可以通过标准的沉积、掩膜和掺杂工艺形成，并且因此不再对此作进一步解释。HEMT的源极经由夹、键合线、带或其他类型的电连接器320连接至肖特基接触318，而HEMT的栅极经由另一夹、键合线、带或其他类型的电连接器322连接至欧姆接触316，以完成图1所示的级联连接。在图9中，将生成的级联二极管的阳极和阴极分别标上“阳极”和“阴极”。
空间相关术语，比如“下”、“下方”、“之上”、“上”等，出于方便说明之目的，用于解释一个元件相对于第二元件的位置。该术语旨在涵盖器件的除了附图所示方向之外的不同方向。进一步地，诸如“第一”、“第二”之类的术语还可以用于说明各种元件、区和部段等，并且亦非旨在构成限制。贯穿本说明，类似的术语表示类似的元件。
如本文所使用的，“具有”、“包含”、“包括”等术语为开放式术语，其表明存在所表述的元件或特征，但不排除存在其他的元件或特征。除非本文另有明确说明，否则冠词“一”、“一个”和“该”旨在包括单数形式和复数形式。
考虑到上述变化和应用的范围，应理解本发明不受以上说明的限制，也不受附图的限制。而是本发明仅受所附权利要求书及其法律等同的限制。

Claims (20)

1.一种级联二极管，包括：
III族氮化物半导体本体；
具有栅极、漏极、源极以及连接所述源极和所述漏极的沟道的HEMT，所述沟道由所述栅极控制并且由在所述III族氮化物半导体本体的具有不同带隙的两种材料之间的结形成；以及
与所述HEMT单片集成的半导体二极管，所述半导体二极管具有连接至所述HEMT的所述源极的阴极以及连接至所述HEMT的所述栅极的阳极，
其中，所述半导体二极管的所述阳极形成所述级联二极管的阳极，而所述HEMT的所述漏极形成所述级联二极管的阴极。
2.根据权利要求1所述的级联二极管，其中，所述半导体二极管为Si肖特基二极管或SiC肖特基二极管。
3.根据权利要求1所述的级联二极管，其中，所述半导体二极管为Si p-n结二极管。
4.根据权利要求1所述的级联二极管，其中，所述HEMT为GaN HEMT，而所述半导体二极管为GaN二极管或MIS栅控二极管。
5.根据权利要求1所述的级联二极管，进一步包括：
Si衬底，所述III族氮化物半导体本体布置于所述Si衬底上；以及
导电塞，延伸穿过所述III族氮化物半导体本体并且将所述HEMT的所述源极连接至所述Si衬底。
6.根据权利要求5所述的级联二极管，进一步包括布置在所述Si衬底的背离所述III族氮化物半导体本体的一侧上的金属化结构，其中，所述Si衬底为n型掺杂的，所述半导体二极管的所述阴极由所述n型掺杂的Si衬底形成，而所述半导体二极管的所述阳极由布置在所述Si衬底上的所述金属化结构形成。
7.根据权利要求6所述的级联二极管，其中，所述Si衬底的n型掺杂的浓度在所述Si衬底的与所述金属化结构相邻的第一区中较低，而在所述Si衬底的通过所述第一区与所述金属化结构间隔开的第二区中较高。
8.根据权利要求5所述的级联二极管，其中，所述Si衬底为p型掺杂的，所述塞为金属塞，所述半导体二极管的所述阴极由所述金属塞形成，而所述半导体二极管的所述阳极由所述p型掺杂的Si衬底形成。
9.根据权利要求5所述的级联二极管，其中，所述Si衬底为p型掺杂的，所述塞包括n掺杂多晶硅，所述半导体二极管的所述阴极由所述n掺杂多晶硅的塞形成，而所述半导体二极管的所述阳极由所述p型掺杂的Si衬底形成。
10.根据权利要求5所述的级联二极管，其中，所述塞包括与所述HEMT的所述源极接触的n掺杂多晶硅区、以及通过所述n掺杂多晶硅区与所述HEMT的所述源极间隔开的p掺杂多晶硅区，所述半导体二极管的所述阴极由所述塞的所述n掺杂多晶硅区形成，而所述半导体二极管的所述阳极由所述塞的所述p掺杂多晶硅区形成。
11.根据权利要求1所述的级联二极管，其中，所述半导体二极管布置在所述III族氮化物半导体本体上，并且包括：
布置在所述III族氮化物半导体本体的具有所述HEMT的所述栅极的一侧上的重度n掺杂多晶硅区；
与所述重度n掺杂多晶硅区相邻的轻度n掺杂多晶硅区；
在所述重度n掺杂多晶硅区上的欧姆接触；以及
在所述轻度n掺杂多晶硅区上的肖特基接触，
其中，所述HEMT的所述源极连接至所述欧姆接触，而所述HEMT的所述栅极连接至所述肖特基接触。
12.根据权利要求1所述的级联二极管，其中，所述半导体二极管布置在所述III族氮化物半导体本体上，并且包括：
布置在所述III族氮化物半导体本体的具有所述HEMT的所述栅极的一侧上的重度p掺杂多晶硅区；
与所述重度p掺杂多晶硅区相邻的轻度p掺杂多晶硅区；
在所述重度p掺杂多晶硅区上的欧姆接触；以及
在所述轻度p掺杂多晶硅区上的肖特基接触，
其中，所述HEMT的所述源极连接至所述肖特基接触，而所述HEMT的所述栅极连接至所述欧姆接触。
13.根据权利要求1所述的级联二极管，进一步包括延伸穿过所述III族氮化物半导体本体以将所述HEMT的所述栅极连接至所述半导体二极管的所述阳极的导电塞，所述导电塞具有绝缘侧壁。
14.一种具有超过300V的击穿电压的级联二极管，包括：
包括栅极、漏极、源极和二维电子气沟道区的HEMT，所述二维电子气沟道区连接所述源极和所述漏极并且由所述栅极控制，所述HEMT具有超过300V的击穿电压；以及
与所述HEMT单片集成的Si肖特基二极管，所述Si肖特基二极管包括连接至所述HEMT的所述源极的阴极以及连接至所述HEMT的所述栅极的阳极，所述Si肖特基二极管具有低于300V的击穿电压和低于或等于0.4V的正向电压，
其中，所述Si肖特基二极管的所述阳极形成所述级联二极管的阳极，而所述HEMT的所述漏极形成所述级联二极管的阴极。
15.根据权利要求14所述的级联二极管，进一步包括：
Si衬底，所述HEMT布置于所述Si衬底上；以及
导电塞，将所述HEMT的所述源极连接至所述Si衬底。
16.根据权利要求15所述的级联二极管，进一步包括布置在所述Si衬底的背离所述HEMT的所述栅极的一侧上的金属化结构，其中，所述Si衬底为n型掺杂的，所述Si肖特基二极管的所述阴极由所述n型掺杂的Si衬底形成，而所述Si肖特基二极管的所述阳极由布置在所述Si衬底上的所述金属化结构形成。
17.根据权利要求15所述的级联二极管，其中，所述Si衬底为p型掺杂的，所述塞为金属塞，所述Si肖特基二极管的所述阴极由所述金属塞形成，而所述Si肖特基二极管的所述阳极由所述p型掺杂Si衬底形成。
18.根据权利要求14所述的级联二极管，其中，所述Si肖特基二极管布置在III族氮化物半导体本体的具有所述HEMT的所述栅极的一侧上，并且所述Si肖特基二极管包括：
布置在所述III族氮化物半导体本体的具有所述HEMT的所述栅极的一侧上的重度n掺杂多晶硅区；
与所述重度n掺杂多晶硅区相邻的轻度n掺杂多晶硅区；
在所述重度n掺杂多晶硅区上的欧姆接触；以及
在所述轻度n掺杂多晶硅区上的肖特基接触，
其中，所述HEMT的所述源极连接至所述欧姆接触，而所述HEMT的所述栅极连接至所述肖特基接触。
19.根据权利要求14所述的级联二极管，其中，所述Si肖特基二极管布置在III族氮化物半导体本体的具有所述HEMT的所述栅极的一侧上，并且所述Si肖特基二极管包括：
布置在所述III族氮化物半导体本体的具有所述HEMT的所述栅极的一侧上的重度p掺杂多晶硅区；
与所述重度p掺杂多晶硅区相邻的轻度p掺杂多晶硅区；
在所述重度p掺杂多晶硅区上的欧姆接触；以及
在所述轻度p掺杂多晶硅区上的肖特基接触，
其中，所述HEMT的所述源极连接至所述肖特基接触，而所述HEMT的所述栅极连接至所述欧姆接触。
20.一种制造级联二极管的方法，所述方法包括：
在III族氮化物半导体本体中形成HEMT，所述HEMT具有栅极、漏极、源极以及连接所述源极和所述漏极的沟道，所述沟道由所述栅极控制并且由在所述III族氮化物半导体本体的具有不同带隙的两种材料之间的结形成；
将半导体二极管与所述HEMT单片集成，所述半导体二极管具有连接至所述HEMT的所述源极的阴极以及连接至所述HEMT的所述栅极的阳极；
将所述级联二极管的阳极端子连接至所述半导体二极管的所述阳极；以及
将所述级联二极管的阴极端子连接至所述HEMT的所述漏极。
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