CN110277406B - 半导体存储装置 - Google Patents
半导体存储装置 Download PDFInfo
- Publication number
- CN110277406B CN110277406B CN201810886808.2A CN201810886808A CN110277406B CN 110277406 B CN110277406 B CN 110277406B CN 201810886808 A CN201810886808 A CN 201810886808A CN 110277406 B CN110277406 B CN 110277406B
- Authority
- CN
- China
- Prior art keywords
- portions
- film
- memory device
- contour
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 230000007423 decrease Effects 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7889—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018-048447 | 2018-03-15 | ||
JP2018048447A JP7123585B2 (ja) | 2018-03-15 | 2018-03-15 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110277406A CN110277406A (zh) | 2019-09-24 |
CN110277406B true CN110277406B (zh) | 2023-09-05 |
Family
ID=67904147
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810886808.2A Active CN110277406B (zh) | 2018-03-15 | 2018-08-06 | 半导体存储装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10651186B2 (zh) |
JP (1) | JP7123585B2 (zh) |
CN (1) | CN110277406B (zh) |
TW (1) | TWI676239B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102647618B1 (ko) * | 2019-04-30 | 2024-03-13 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 굴곡된 후면 워드 라인을 갖는 삼차원 메모리 디바이스 |
WO2020220269A1 (en) | 2019-04-30 | 2020-11-05 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional memory device having bent backside word lines |
JP2021145014A (ja) * | 2020-03-11 | 2021-09-24 | キオクシア株式会社 | 半導体記憶装置 |
JP2022036723A (ja) * | 2020-08-24 | 2022-03-08 | キオクシア株式会社 | 半導体記憶装置 |
JP2023041280A (ja) | 2021-09-13 | 2023-03-24 | キオクシア株式会社 | 記憶装置 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105097818A (zh) * | 2014-05-21 | 2015-11-25 | 旺宏电子股份有限公司 | 存储器装置及其制造方法和操作方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101603731B1 (ko) | 2009-09-29 | 2016-03-16 | 삼성전자주식회사 | 버티칼 낸드 전하 트랩 플래시 메모리 디바이스 및 제조방법 |
JP6084246B2 (ja) * | 2014-05-21 | 2017-02-22 | マクロニクス インターナショナル カンパニー リミテッド | 3d独立二重ゲートフラッシュメモリ |
US10103155B2 (en) * | 2016-03-09 | 2018-10-16 | Toshiba Memory Corporation | Semiconductor memory device |
KR101940374B1 (ko) * | 2016-05-19 | 2019-04-11 | 연세대학교 산학협력단 | 3 차원 비휘발성 메모리 소자 및 이의 제조 방법 |
-
2018
- 2018-03-15 JP JP2018048447A patent/JP7123585B2/ja active Active
- 2018-08-06 CN CN201810886808.2A patent/CN110277406B/zh active Active
- 2018-08-06 TW TW107127262A patent/TWI676239B/zh active
- 2018-09-05 US US16/122,492 patent/US10651186B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105097818A (zh) * | 2014-05-21 | 2015-11-25 | 旺宏电子股份有限公司 | 存储器装置及其制造方法和操作方法 |
Also Published As
Publication number | Publication date |
---|---|
TW201939676A (zh) | 2019-10-01 |
CN110277406A (zh) | 2019-09-24 |
US10651186B2 (en) | 2020-05-12 |
JP7123585B2 (ja) | 2022-08-23 |
TWI676239B (zh) | 2019-11-01 |
JP2019161118A (ja) | 2019-09-19 |
US20190287983A1 (en) | 2019-09-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110277406B (zh) | 半导体存储装置 | |
US9153705B2 (en) | Vertical memory devices and methods of manufacturing the same | |
TWI389305B (zh) | 非揮發性半導體儲存元件及其製造方法 | |
TWI385792B (zh) | 非揮發性半導體儲存裝置及其製造方法 | |
US9130038B2 (en) | Three-dimensional semiconductor memory device, memory system including the same, method of manufacturing the same and method of operating the same | |
CN110277395B (zh) | 存储装置 | |
CN110931488B (zh) | 半导体存储器 | |
US10636803B2 (en) | Semiconductor memory device with floating gates having a curved lateral surface | |
US20110012188A1 (en) | Semiconductor memory device | |
US20120235220A1 (en) | Semiconductor device | |
CN112117278B (zh) | 半导体存储装置及其制造方法 | |
US20160322378A1 (en) | Semiconductor memory device and method of manufacturing the same | |
US20160322377A1 (en) | Semiconductor memory device | |
JP4504403B2 (ja) | 半導体記憶装置 | |
JP2013201185A (ja) | 不揮発性半導体記憶装置およびその製造方法 | |
JP2020035977A (ja) | 半導体記憶装置 | |
CN111989776B (zh) | 半导体存储装置 | |
US8207572B2 (en) | Nonvolatile semiconductor memory device | |
US9761605B1 (en) | Semiconductor memory device | |
TWI751631B (zh) | 半導體裝置 | |
JP2019169517A (ja) | 半導体記憶装置 | |
CN113380808B (zh) | 半导体存储装置 | |
JP2022147746A (ja) | 半導体記憶装置 | |
TWI787833B (zh) | 半導體記憶裝置及其製造方法 | |
TWI821718B (zh) | 半導體記憶裝置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: Tokyo Applicant after: TOSHIBA MEMORY Corp. Address before: Tokyo Applicant before: Pangea Co.,Ltd. Address after: Tokyo Applicant after: Kaixia Co.,Ltd. Address before: Tokyo Applicant before: TOSHIBA MEMORY Corp. |
|
CB02 | Change of applicant information | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20220129 Address after: Tokyo Applicant after: Pangea Co.,Ltd. Address before: Tokyo Applicant before: TOSHIBA MEMORY Corp. |
|
TA01 | Transfer of patent application right | ||
GR01 | Patent grant | ||
GR01 | Patent grant |