CN110246772A - 半导体装置及半导体装置的制造方法 - Google Patents
半导体装置及半导体装置的制造方法 Download PDFInfo
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- CN110246772A CN110246772A CN201910529230.XA CN201910529230A CN110246772A CN 110246772 A CN110246772 A CN 110246772A CN 201910529230 A CN201910529230 A CN 201910529230A CN 110246772 A CN110246772 A CN 110246772A
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Abstract
本发明提供一种半导体装置及半导体装置的制造方法,本发明的半导体装置为通过键合线(7)将半导体芯片(1)和电路图案(4)电连接的模块结构的半导体装置,在半导体芯片(1)的正面电极的表面形成有正面金属膜,在该正面金属膜通过引线键合而接合有键合线(7)。就半导体芯片(1)而言,在Si基板或SiC基板的正面具有正面电极,在背面具有背面电极。正面金属膜为厚度在例如3μm以上且7μm以下的Ni膜或Ni合金膜。键合线(7)为通过将引线键合前的结晶粒度控制在例如1μm以上且20μm以下的范围内,从而提高了再结晶温度且使强度得到了提高的Al线。由此,能够提供实现了大电流导通和高温动作的高可靠性的半导体装置。
Description
本申请是申请人于2015年9月1日提交的申请号为201480011844.4(国际申请号PCT/JP2014/061458),原申请发明名称为“半导体装置”的发明专利申请的分案申请,通过引用将其全部内容结合到本申请。
技术领域
本发明涉及一种半导体装置及半导体装置的制造方法。
背景技术
在用于通用逆变器、风力发电、太阳能发电和电气化铁路等的模块结构的半导体装置中,在现有技术中,公知有通过铝(Al)线等的引线键合而将半导体元件的正面电极和电路图案进行电连接(键合)的构成的模块结构的半导体装置。该模块结构的半导体装置的正面电极例如为Al电极和/或铜(Cu)电极,电路图案由例如Cu等导体构成。
此外,还提出了下述构成的模块结构的半导体装置:在Al电极的表面上形成镀镍(Ni)膜,镀Ni膜和镀金(Au)膜的层叠膜,或镀Ni膜、镀钯(Pd)膜和镀Au膜的层叠膜,并在该镀膜上引线键合Al线的构成,或代替Al线的引线键合而将引线框架焊接于镀膜的构成。对现有的模块结构的半导体装置的结构进行说明。
图14是示出现有的模块结构的半导体装置的结构的剖视图。图15是示意性地示出图14的半导体元件的结构的剖视图。如图14、图15所示,现有的模块结构的半导体装置具备半导体芯片(半导体元件)101、绝缘基板102、Cu基底106和Al线107。就绝缘基板102而言,在绝缘层103的正面侧设置有由Cu构成的电路图案104,在绝缘层103的背面侧设置有背面铜箔105。
就半导体芯片101而言,在半导体基板111的正面具有由Al或Cu构成的正面电极112,在半导体基板111的背面具有背面电极113。半导体芯片101的背面电极113通过焊料接合层101a与电路图案104接合。半导体芯片101的正面电极112通过Al线107等的引线键合而与电路图案104电连接。
Al线107是利用超声波振动进行接合的,通过使对Al线107的线径(直径)施加的热量、超声波振动、压力等的条件最佳化,从而不产生连接不良而形成良好的接合。现有的Al线107的线径为300μm~400μm程度。正面电极112与Al线107的接合条件根据正面电极112所使用的金属种类和/或正面电极112的厚度而变化。Cu基底106的正面通过焊料接合层(未图示)与背面铜箔105接合。
作为这样的模块结构的半导体装置而提出有镀Ni膜的表面光泽度为1.6以上或镀Ni膜的表面粗糙度为0.2μm以下,并且镀Ni膜的厚度为2μm以上的装置,上述镀Ni膜是作为进行Al线键合的对象的电极,并被施加于由黄铜板和/或Cu板构成的电极母材(例如,参照下述专利文献1)。在下述专利文献1中,公开了镀Ni膜的特性中的表面光泽度、表面粗糙度和镀膜厚度对Al线键合的强度带来很大的影响的技术内容。
此外,作为另一半导体装置而提出了具备在Al电极膜的表面成膜的金属保护膜和通过热压接或超声波振动而与Al电极膜借由金属保护膜电连接的Al线的装置,其中,金属保护膜为利用非电解镀膜法而得到的厚度为5μm以下的镀Ni膜,并且镀Ni膜的厚度为Al电极膜的厚度以下(例如,参照下述专利文献2)。在下述专利文献2中,公开了通过在Al电极膜的表面形成有镀Ni膜,从而能够焊料接合Al电极膜和Al线的技术内容。
现有技术文献
专利文献
专利文献1:日本特开2004-87772号公报
专利文献2:日本特开2009-76703号公报
发明内容
技术问题
然而,近年来,随着使用用途的扩大,对大电流化、高温动作、高可靠性的要求不断提高,产生了如下问题。例如,虽然通过Al线的加粗(例如500μm左右)和/或应用导电率比Al线高的Cu线而能够实现大电流化,但是由于键合线的强度变大,所以在向正面电极的表面进行引线键合时应力作用于半导体芯片,从而导致半导体芯片损坏。
这样的问题可以通过在正面电极的表面形成Ni膜而提高电极部的强度来解决。但是,由于Ni膜与键合线的接合为异种金属之间的接合,所以在现有的用于接合同种金属彼此(Al电极和Al线,或Cu电极和Cu线)的引线键合条件下,具有容易在Ni膜与键合线的接合界面产生接合不良(未接合部),从而无法良好地接合Ni膜与键合线的问题。
容易在Ni膜与键合线的接合界面产生接合不良的原因是因为作为Ni膜的材料的Ni与作为键合线的材料的Al和Cu具有不同的材料特性。由于Ni比Al或Cu硬且难以延展,所以作用于Ni膜的应力难以分散,在引线键合时容易在Ni膜上产生裂纹。因此,键合线的线径(直径)、Ni膜的厚度、Ni膜与键合线的接合条件变得非常重要,但是关于他们的详细研究结果却没有被公开。
此外,在现有的Al线中,通过引线键合使得与正面电极的接合界面附近的晶体结构比引线键合前精细化,Al线的接合界面附近的强度提高。但是,Al线的接合界面附近的晶体结构会根据由引线键合后的制造工序而产生的热过程和/或由半导体元件的通电发热而引起的高温(例如175℃左右)动作而粗大化并软化。由此,裂纹(破裂)变得容易向Al线的内部延伸。
发明人对将Al线引线键合于正面电极表面的半导体装置进行通电循环试验的结果表明,裂纹随着通电循环的反复循环次数的增加而向Al线的内部延伸,最终Al线断裂剥离而导致元件损坏。因此,期望通过提高针对动作中的发热和反复放热(通电循环)的热负荷的耐受量(以下,称为通电循环耐受量(寿命))而开发出实现了大电流导通和高温动作的高可靠性的半导体装置。
本发明为了解决上述现有技术的问题点,其目的在于提供一种实现了大电流导通和高温动作的高可靠性的半导体装置。
技术方案
为了解决上述课题,实现本发明的目的,本发明的半导体装置具有如下特征。在半导体元件的表面设置有导电部。在前述导电部的表面设置有厚度为3μm以上且7μm以下的金属膜。在前述金属膜通过利用了超声波振动的引线键合而接合有线径为500μm以上的键合线。
此外,本发明的半导体装置在上述发明中的特征在于,前述半导体元件具备:半导体基板,选自硅基板和碳化硅基板;和前述导电部,设置于前述半导体基板的表面,且以铝为主要成分。
此外,本发明的半导体装置在上述发明中的特征在于,前述金属膜以镍为主要成分。
此外,本发明的半导体装置在上述发明中的特征在于,前述金属膜为含有磷和硼中的至少一种的镍合金膜。
根据上述发明,通过利用了超声波振动的引线键合而将键合线接合于在正面电极的表面形成的正面金属膜,由此能够提高正面金属膜与键合线的接合强度和接合率。由此,能够确保正面金属膜与键合线的良好的接合状态,而能够防止键合线剥离。因此,即使将键合线的线径加粗到500μm以上而提高键合线的导电性,也能够提高半导体装置的寿命。
技术效果
根据本发明的半导体装置,具有能够实现大电流化和高温动作,并且能够提高可靠性的效果。
附图说明
图1是示出实施方式的半导体装置的结构的剖视图。
图2是示意性地示出图1的半导体元件的结构的剖视图。
图3是示出实施方式的半导体装置的制造方法的概要的流程图。
图4是示出镀镍膜的厚度与镀膜处理时间之间的关系的特性图。
图5是示出实施例1的半导体装置在引线键合后的半导体芯片特性的图表。
图6是示出比较例1的半导体装置在引线键合后的半导体芯片特性的图表。
图7是示出实施例2的半导体装置的正面金属膜与键合线的接合强度的特性图。
图8是示出实施例2的半导体装置的正面金属膜与键合线的接合率的特性图。
图9是示意性地示出实施例2的半导体装置在测定抗剪强度后的状态的俯视图。
图10是示出正面金属膜与键合线的接合率的计算方法的说明图。
图11是示意性地示出实施例2的半导体装置在接合后的状态的剖视图。
图12是示出实施例1的半导体装置的通电循环耐受量的特性图。
图13是示出实施例1的半导体装置的通电循环耐受量的特性图。
图14是示出现有的模块结构的半导体装置的结构的剖视图。
图15是示意性地示出图14的半导体元件的结构的剖视图。
符号说明
1:半导体芯片
2:绝缘基板
3:绝缘层
4:电路图案
5:背面铜箔
6:Cu基底
7:键合线
8:焊料接合层
11:半导体基板
12:正面电极
13:背面电极
14:正面金属膜
具体实施方式
以下,参照附图详细说明本发明的半导体装置的优选实施方式。应予说明,在以下的实施方式的说明以及附图中,对同样的构成标记相同的符号,并省略重复的说明。
(实施方式)
对实施方式的半导体装置的结构进行说明。图1是示出实施方式的半导体装置的结构的剖视图。图2是示意性地示出图1的半导体元件的结构的剖视图。如图1、图2所示,实施方式的半导体装置为具备半导体芯片(半导体元件)1、陶瓷绝缘基板(DCB基板)等的绝缘基板2、铜(Cu)基底6和键合线7的模块结构的半导体装置。就绝缘基板2而言,在绝缘层3的正面侧设置有例如由Cu等构成的电路图案4,在绝缘层3的背面侧设置有背面铜箔5。
就半导体芯片1而言,在半导体基板(例如硅(Si)基板或碳化硅(SiC)基板)11的正面具有正面电极(导电部)12,在半导体基板11的背面具有背面电极13。半导体芯片1的背面电极13通过焊料接合层8与电路图案4接合。Cu基底6的正面通过焊料接合层(未图示)与背面铜箔5接合。虽然未图示,但就半导体装置而言,Cu基底6的背面通过导热材料(thermalcompound)与散热体接合而使用。此外,在Cu基底6的边缘粘接有设置了外部端子的树脂外壳。
半导体芯片1的正面电极(以下,仅称为正面电极)12为例如以铝(Al)为主要成分的Al电极或Al合金电极。在正面电极12的表面通过例如非电解镀膜处理、电解镀膜处理、溅射和气相沉积等而形成有正面金属膜14。正面金属膜14为例如镍(Ni)膜、以Ni为主要成分的Ni合金膜(例如至少包含磷(P)和硼(B)中的任意一种的Ni合金膜)和/或Cu膜,其硬度比正面电极12高。正面金属膜14的硬度为例如Hv400~Hv900,比正面电极12和键合线7的硬度高。在作为正面金属膜14而形成了通过例如非电解镀Ni处理而形成的镀Ni膜的情况下,正面金属膜14的光泽度为例如1.4左右。
正面金属膜14的厚度可以为例如3.0μm以上,优选为例如4.5μm以上。其理由如下。通过使正面金属膜14的厚度为例如3.0μm以上而发挥如下效果。由于能够提高正面电极12的强度,所以即使在使用以铝(Al)为主要成分,线径为450μm~550μm,典型地约为500μm以上的键合线7的情况下,也能够缓和在引线键合时作用于半导体芯片1的应力,从而降低导致半导体芯片1损坏的频率。此外,能够提高金属种类不同的正面金属膜14与键合线7的接合强度和接合率,从而能够防止在正面金属膜14与键合线7的接合界面产生接合不良(未接合部),而使正面金属膜14与键合线7良好地接合。
进一步地,通过将正面金属膜14的厚度设置为例如4.5μm以上,能够使导致半导体芯片1损坏的频率减小,并使正面金属膜14与键合线7的接合强度和接合率与同种金属之间(例如Al电极与Al线)的接合相同程度地提高。因此,能够使正面金属膜14与键合线7进一步良好地接合。通过将正面金属膜14的厚度设置为例如5.0μm左右,能够不导致半导体芯片1损坏(导致半导体芯片1损坏的频率=0%),并且在正面金属膜14与键合线7的接合界面不产生未接合部(接合率≒100%)。这样,正面金属膜14的厚度可以为3.0μm以上且7.0μm以下的范围,优选为4.5μm以上且7.0μm以下的范围。虽然正面金属膜14的厚度越厚越能够降低导致半导体芯片1损坏的频率,但如果过厚则半导体芯片1产生翘曲,考虑生产量(throughput)和经济性等可设置为正面电极12的厚度以下。优选地,正面电极12的厚度为3.0μm以上且10.0μm以下。
导致半导体芯片1损坏的频率为导致损坏的半导体芯片(不合格品)的个数N1相对于在生产线制造的半导体芯片的总数N0的比例(=N1/N0)。正面金属膜14与键合线7的接合率为正面金属膜14与键合线7的接合面积S1相对于正面金属膜14与键合线7对置的部分的面积S0的比例(=S1/S0)。即,接合率=100%是指在正面金属膜14与键合线7的接合界面未产生接合不良的状态(没有未接合部)。关于正面金属膜14与键合线7的接合率的详细说明将在后面描述。
在正面金属膜14,通过利用例如热量、超声波振动和压力(接合负载)的引线键合而接合有键合线7的一端。键合线7的另一端通过引线键合而接合于电路图案4。即,经由键合线7将正面电极12与电路图案4电连接。对于键合线7的引线键合条件将在后面描述。键合线7可以为以Al为主要成分,并通过将线径(直径)加粗为例如500μm以上来提高导电性的Al线。通过加粗键合线7能够实现大电流导通,并且由于能够降低通电时键合线7的发热温度而能够实现高温动作。具体说来,键合线7可以为通过含有预定量的例如铁(Fe)来提高强度的铝合金线。铝合金线为例如由含有0.2重量%~2.0重量%的范围的Fe,和剩余部分为纯度99.99%以上的铝(Al)构成的键合线。应予说明,键合线7的线径如果超过600μm,则需要增大引线键合的输出,加厚正面金属膜14,因此,优选为450μm~550μm的范围。
此外,键合线7可以为通过将引线键合前的结晶粒度控制在例如1μm以上且20μm以下的范围内来提高再结晶温度并使强度得到了提高的高强度键合线。通过控制键合线7的结晶粒度,从而能够将键合线7的再结晶温度提高到例如175℃以上。键合线7的与被接合部件(正面金属膜14和电路图案4)的接合界面附近的晶粒通过引线键合而成为比引线键合前更微细的颗粒状,该结晶粒度在例如1μm以上且15μm以下的范围内。在键合线7的从与被接合部件的接合界面分离的部分(键合线7的接合界面附近以外),维持引线键合前的结晶粒度。通过使刚进行引线键合之后的键合线7的接合界面附近的结晶粒度在上述范围内,从而能够提高键合线7的与被接合部件的接合界面附近的接合强度。键合线7的接合界面附近是指根据例如由引线键合后的制造工序而产生的热过程和/或由半导体元件的通电发热引起的高温动作的热量而容易产生裂纹的部分。
以下,以通过非电解镀Ni处理在作为正面电极12的Al电极的表面作为正面金属膜14而形成镀Ni膜的情况为例对正面金属膜14的成膜(形成)方法进行说明。图3是示出实施方式的半导体装置的制造方法的概要的流程图。图4是示出镀镍膜的厚度与镀膜处理时间之间的关系的特性图。由于Al电极与Ni膜密合性差,所以通常作为非电解镀膜处理的预处理而进行锌酸盐处理,以提高镀Ni膜相对于Al电极的密合性。具体说来,首先,在正面电极12的表面进行脱脂处理,去除附着在表面的油脂性的污渍和/或异物以使其洁净(步骤S1)。在步骤S1,可以改善后续工序的例如蚀刻液等对正面电极12的表面的润湿性。然后,使用酸性溶液进行蚀刻处理(步骤S2)。由此,正面电极12的表面的自然氧化膜被去除。
然后,使用硝酸(HNO3)溶液进行酸洗(去污处理),去除由蚀刻处理产生的附着物(污物:smut)。然后,进行第一锌酸盐处理,将正面电极12的表面的Al置换为锌(Zn),而在正面电极12的表面生成具有所期望的结晶粒度的Zn膜(步骤S3)。然后,使用硝酸溶液去除形成于正面电极12的表面的Zn膜(步骤S4)。然后,通过进行第二锌酸盐处理,从而再次在正面电极12的表面生成Zn膜(步骤S5)。之后,进行非电解镀Ni处理,将Zn膜置换为Ni,通过在正面电极12的表面持续析出Ni来形成镀Ni膜(步骤S6)。由此,在正面电极12的表面作为正面金属膜14而形成镀Ni膜。如图4所示,发明人确认镀Ni膜的厚度与镀膜处理时间成比例地变厚。
以下,对键合线7的引线键合条件进行说明。图5是示出实施例1的半导体装置在引线键合后的半导体芯片特性的图表。图6是示出比较例1的半导体装置在引线键合后的半导体芯片特性的图表。根据不同的引线键合条件制造多个涉及实施方式的半导体装置(以下,称为实施例1),并将确认了是否导致半导体芯片1损坏的结果示于图5。作为比较,根据与实施例1同样的引线键合条件制造多个将键合线7接合于正面电极12的半导体装置(以下,称为比较例1),并将确认了是否导致半导体芯片1损坏的结果示于图6。
按下述方法在实施例1和比较例1中都制作引线键合条件不同的共计九个试样:将引线键合时的接合负载设置为1300cN、1400cN和1500cN,并针对每个接合负载制作将引线键合的超声波输出设置为18V、20V和22V的三个试样。就被接合部件而言,在实施例1中是指正面金属膜14,在比较例1中是指正面电极12。图5、图6中,针对每个试样,在半导体装置为正常的情况下用○符号表示,在导致半导体芯片损坏的情况下用×符号表示。“正常”是指半导体装置满足作为产品的预定的动作基准的情况。导致半导体芯片损坏的情况是指在栅极-发射极间产生漏电流Iges,半导体装置不满足作为产品的预定的动作基准的情况。
实施例1的各试样中共用的构成如下。通过例如溅射在直径6英寸的Si晶片的正面作为正面电极12而形成厚度为5.0μm的Al电极,切割该Si晶片,以使芯片尺寸成为10mm×10mm,并将切割得到的芯片作为实施例1的半导体芯片1。根据上述的正面金属膜14的成膜方法通过非电解镀Ni处理,在半导体芯片1的正面电极12的表面形成了厚度为5.0μm的镀Ni膜来作为正面金属膜14。然后,针对每个试样在不同的上述引线键合条件下,将线径为500μm的键合线7引线键合于正面金属膜14。作为键合线7使用将引线键合前的结晶粒度控制在1μm以上且20μm以下的范围内而提高强度,并且通过添加Fe(铁)而提高了强度的铝合金线。比较例1的构成除了未在正面电极12的表面形成镀Ni膜这一点以外与实施例1相同。即,在比较例1中,键合线7与正面电极12的接合为同种金属之间的接合。
如图6所示,在比较例1中,在1500cN以下的低接合负载,且18V的低超声波输出的条件下进行引线键合的试样中,发生键合线7与正面电极12的接合不良且不进行正常动作。推测为由于接合负载和超声波输出低,而可能使得在键合线7与正面电极12的接合界面的整个区域产生接合不良。与此相对地,如图5所示,确认了在实施例1中所有的试样都正常动作(未发生不良)。由此,可知通过形成正面金属膜14,并按以下所说明的那样增加正面金属膜14的厚度,从而缓和在引线键合时作用于半导体芯片1的应力,而不导致半导体芯片1损坏。此外,确认了实施例1可以在超声波输出和接合负载比比较例1低的条件下通过引线键合来制造。
以下,对正面金属膜14与键合线7的接合强度和接合率进行说明。图7是示出实施例2的半导体装置的正面金属膜与键合线的接合强度的特性图。图8是示出实施例2的半导体装置的正面金属膜与键合线的接合率的特性图。将正面金属膜14的厚度进行各种变更从而制造多个涉及实施方式的半导体装置(以下,称为实施例2),并将测定正面金属膜14与键合线7的接合部的抗剪强度(shear strength)的结果示于图7。此外,对于测定抗剪强度后的实施例2,将正面金属膜14与键合线7的接合率的计算结果示于图8。
实施例2的各试样的正面金属膜14的厚度分别为0.1μm、0.3μm、0.5μm、1.0μm、3.0μm和5.0μm。在实施例2中,将引线键合时的接合负载和超声波输出分别设置为1400cN和20V。实施例2的正面金属膜14的厚度以外的构成与同一引线键合条件下制作的实施例1相同。即,将正面金属膜14的厚度设置为5.0μm的试样为将引线键合时的接合负载和超声波输出分别设置为1400cN和20V的实施例1。图7、图8中将未设置正面金属膜14的比较例1作为将正面金属膜14的厚度设置为0.0μm的试样而示出。图8中,在柱形图的上方以数值示出详细的接合率。
根据图7、图8所示的结果,确认了虽然比较例1的正面电极12与键合线7的接合率为95%,但是导致半导体芯片1损坏的频率高,而导致很多半导体芯片1损坏。此外,确认了在正面金属膜14的厚度大于0.0μm小于3.0μm的情况下,正面金属膜14与键合线7的接合强度和接合率比直接在正面电极12上接合键合线7的比较例1低。进一步地,确认了在正面金属膜14的厚度大于0.0μm小于3.0μm的情况下,导致半导体芯片1损坏的频率高,而导致很多半导体芯片1损坏。
与此相对地,确认了在正面金属膜14的厚度为3.0μm以上的情况下,能够使正面金属膜14与键合线7的接合强度和接合率为与比较例1相同程度。具体说来,在将正面金属膜14的厚度设置为5.0μm的试样(实施例1)中,正面金属膜14与键合线7的接合部的抗剪强度为3761kgf,正面金属膜14与键合线7的接合率为100%。因此,根据图7、图8所示的结果,确认了通过将正面金属膜14的厚度设置为3.0μm以上,从而能够使金属种类不同的正面金属膜14和键合线7与同种金属之间的接合相同程度地良好地接合。
以下,将从上方(键合线7侧)观察测定抗剪强度后的实施例2的正面金属膜14与键合线7的接合部的状态的结果示于图9。图9是示意性地示出实施例2的半导体装置在测定抗剪强度后的状态的俯视图。图9(a)中示出比较例1(未镀Ni膜)的正面电极(Al电极)12a与键合线(高强度键合线)7a的接合部21a的状态。图9(b)中示出将正面金属膜(镀Ni膜)14b的厚度设置为0.3μm的实施例2的正面金属膜14b与键合线7b的接合部21b的状态。图9(c)中示出将正面金属膜14c的厚度设置为5.0μm的实施例2的正面金属膜14c与键合线7c的接合部21c的状态。
如图9(b)所示,确认了在正面金属膜14b的厚度为0.3μm的情况下,在正面金属膜14b与键合线7b的接合部21b产生接合不良(未接合部)22b。此时,正面金属膜14b与键合线7b的接合率为86%。如此,在正面金属膜14的厚度为大于0.0μm且小于3.0μm的情况下,在正面金属膜14与键合线7的接合部产生接合不良。因此,如上述图8所示,正面金属膜14与键合线7的接合率比比较例1的正面电极12a与键合线7a的接合率低。
与此相对地,如图9(c)所示,在正面金属膜14c的厚度为5.0μm的情况下,与将正面电极12a与键合线7a直接接合的比较例1(图9(a))相同,在正面金属膜14c与键合线7c的接合部21c不产生接合不良而进行了良好的接合(正面金属膜14c与键合线7c的接合率=100%)。如此,在正面金属膜14的厚度为3.0μm以上的情况下,在正面金属膜14与键合线7的接合部难以产生接合不良。因此,如上述图8所示,正面金属膜14与键合线7的接合率为与比较例1的正面电极12a与键合线7a的接合率相同的程度。
以下,对正面金属膜14与键合线7的接合率的计算方法进行说明。图10是示出正面金属膜与键合线的接合率的计算方法的说明图。如图10所示,将正面金属膜14与键合线7的接合部31的平面形状(即,键合线7的端部平面形状)设为例如长轴为L且短轴为D的椭圆形状。此外,将接合部31内正面金属膜14与键合线7未接合的部分(未接合部)32的平面形状设为例如长轴为l且短轴为d的椭圆形状。此时,正面金属膜14与键合线7的接合率可用下述(1)式表示。即,正面金属膜14与键合线7的接合率是指正面金属膜14与键合线7接合(接触)的部分的面积(阴影部分)相对于在没有未接合部32时的接合部31的面积的面积比。
[式1]
下面,将观察实施例2的正面金属膜14与键合线7的接合部的剖面的状态的结果示于图11。图11是示意性地示出实施例2的半导体装置在接合后的状态的剖视图。图11(a)中示出图9(a)的正面电极12a与键合线7a的接合部21a的剖面(比较例1)。图11(b)中示出图9(b)的正面金属膜14b与键合线7b的接合部21b的剖面(将正面金属膜14的厚度设置为0.3μm的实施例2)。图11(c)中示出图9(c)的正面金属膜14c与键合线7c的接合部21c的剖面(将正面金属膜14的厚度设置为5.0μm的实施例2)。在图11(a)~图11(c)中,将上图的剖面图放大显示在下图中。应予说明,符号1a~1c为半导体芯片,符号12a~12c为正面电极。
如图11(b)所示,确认了在正面金属膜14b的厚度为0.3μm的情况下,接合后会在正面金属膜14b产生裂纹,在产生该裂纹的部分,在正面金属膜14b与键合线7b的接合部21b产生接合不良22b。在正面金属膜14b的产生了裂纹的部分,正面电极12b与键合线7b对置,正面金属膜14b与键合线7b未接合(接触)(正面电极12b与键合线7b的界面未图示)。如此,确认了在正面金属膜14的厚度大于0.0μm且小于3.0μm的情况下,裂纹进入正面金属膜14,在正面金属膜14与键合线7的接合部产生接合不良。
与此相对地,如图11(c)所示,在正面金属膜14c的厚度为5.0μm的情况下,在正面金属膜14c上未产生裂纹。并且,与比较例1的正面电极12a与键合线7a的接合部21a(图11(a))相同,在正面金属膜14c与键合线7c的接合部21c未产生接合不良。如此,确认了通过将正面金属膜14的厚度设置为3.0μm以上,从而能够防止在正面金属膜14产生裂纹,因此,能够防止在正面金属膜14与键合线7的接合部产生由裂纹引起的接合不良。
以下,对键合线7的线径进行说明。图12、图13是示出实施例1的半导体装置的通电循环耐受量的特性图。将对使上述的引线键合时的接合负载和超声波输出分别为1400cN和20V的实施例1进行通电循环试验的结果示于图12、图13。图12中示出将单位键合线的电流密度设置为16.7A的情况的实施例1的通电循环耐受量。图13中示出将单位键合线的电流密度设置为25.0A的情况的实施例1的通电循环耐受量。通电循环试验中将由于电流断续流动而产生的半导体元件的接合温度的温度变化ΔTj设置为75℃。
此外,在图12、图13中,作为比较示出引线键合了通常的Al线的半导体装置(以下,称为比较例2、比较例3)的通电循环耐受量。比较例2为在与实施例1相同的引线键合条件下将线径为400μm的通常的Al线引线键合于正面金属膜14的半导体装置。比较例3为在与实施例1相同的引线键合条件下将线径为500μm的通常的Al线引线键合于正面金属膜14的半导体装置。比较例2、比较例3的构成除了使用Al线这一点以外与实施例1相同。
根据图12、图13所示的结果,确认了在单位键合线的电流密度为16.7A的情况下,比较例2的通电循环耐受量与比较例3的通电循环耐受量基本相等,键合线7的线径对通电循环耐受量的影响小。与此相对地,确认了在增大单位键合线的电流密度的情况下(电流密度=25.0A),比较例2的通电循环耐受量与比较例3的通电循环耐受量的差变大,由键合线7的线径造成的对通电循环耐受量的影响变大。然而,还确认了比较例3需要将引线键合时的接合负载和超声波输出设定得比比较例2大,而由于增大引线键合时的接合负载和超声波输出会导致半导体芯片1损坏(未图示)。
与此相对地,确认了实施例1中,能够比使用通常的Al线的比较例3更加延长寿命。具体说来,在单位键合线的电流密度为16.7A的情况下,实施例1、比较例2和比较例3的通电循环耐受量分别为600kcycle、247kcycle和297kcycle。在单位键合线的电流密度为25.0A的情况下,实施例1、比较例2和比较例3的通电循环耐受量分别为570kcycle、137kcycle和281kcycle。因此,确认了本发明的半导体装置使大电流导通和高温动作成为可能,且能够延长寿命。
如以上所说明,根据实施方式,通过利用超声波振动的引线键合将以Al为主要成分的键合线接合于在以Al为主要成分的正面电极的表面形成的以Ni为主要成分的厚度为例如3.0μm以上的正面金属膜,由此能够将正面金属膜与键合线的接合强度和接合率提高为与同种金属之间的接合相同的程度。由此,由于能够确保不同金属种类的正面金属膜与键合线的良好的接合状态,所以能够防止键合线剥离,而能够延长半导体装置的寿命。此外,根据实施方式,通过将键合线的结晶粒度控制在例如1μm以上且20μm以下的范围内,能够提高键合线的强度,并且能够使键合线的再结晶温度上升。由此,能够防止由于通电循环等的热负荷而在键合线产生裂纹或键合线断裂而剥离,因此能够延长半导体装置的寿命。因此,根据实施方式,通过使用线径为500μm以上的提高了导电性的键合线,从而能够提供实现了大电流导通和高温动作的高可靠性的半导体装置。
本发明可以在以上内容基础上进行各种变更,在上述各实施方式中,例如各部分的尺寸等可以根据要求的规格等进行各种设定。
产业上的可利用性
如上所述,本发明的半导体装置对于在通用逆变器、风力发电、太阳能发电和电气化铁路等中使用的模块结构的半导体装置具有有益效果。
Claims (12)
1.一种半导体装置,其特征在于,具备:
导电部,设置于半导体元件的表面;
金属膜,设置于所述导电部的表面,具有大于5μm且7μm以下的厚度;和
键合线,通过利用了超声波振动的引线键合而接合于所述金属膜,且具有500μm以上的线径。
2.根据权利要求1所述的半导体装置,其特征在于,
所述键合线的与所述金属膜的接合界面附近的结晶粒度为1μm以上且15μm以下的范围,并且小于所述键合线的与所述金属膜的接合界面附近以外的结晶粒度。
3.根据权利要求1或2所述的半导体装置,其特征在于,
所述键合线的引线键合前的结晶粒度控制在1μm以上且20μm以下的范围内。
4.根据权利要求1或2所述的半导体装置,其特征在于,
所述半导体元件具备:
半导体基板,选自硅基板和碳化硅基板;和
所述导电部,设置于所述半导体基板的表面,且以铝为主要成分。
5.根据权利要求1或2所述的半导体装置,其特征在于,
所述键合线是铝合金线,含有0.2重量%以上且2.0重量%以下的范围的铁,并剩余部分为纯度99.99%以上的铝,
所述金属膜以镍为主要成分。
6.根据权利要求1或2所述的半导体装置,其特征在于,
所述键合线的线径为450μm以上且550μm以下的范围,
所述金属膜为含有磷和硼中的至少一种的镍合金膜。
7.一种半导体装置的制造方法,其特征在于,所述半导体装置具备设置于半导体元件的表面的导电部、设置于所述导电部的表面的金属膜、接合于所述金属膜的键合线,
所述半导体装置的制造方法具有:
在所述导电部设置具有大于5μm且7μm以下的厚度的金属膜的工序;以及
利用引线键合,将具有500μm以上的线径的键合线接合于所述金属膜的工序。
8.根据权利要求7所述的半导体装置的制造方法,其特征在于,
所述键合线的与所述金属膜的接合界面附近的结晶粒度为1μm以上且15μm以下的范围,并且小于所述键合线的与所述金属膜的接合界面附近以外的结晶粒度。
9.根据权利要求7或8所述的半导体装置的制造方法,其特征在于,
所述键合线的引线键合前的结晶粒度控制在1μm以上且20μm以下的范围内。
10.根据权利要求7或8所述的半导体装置的制造方法,其特征在于,具备:
设置选自硅基板和碳化硅基板的半导体基板的工序;以及
在所述半导体基板的表面设置以铝为主要成分的所述导电部。
11.根据权利要求7或8所述的半导体装置的制造方法,其特征在于,
所述键合线是铝合金线,含有0.2重量%以上且2.0重量%以下的范围的铁,并剩余部分为纯度99.99%以上的铝,
所述金属膜以镍为主要成分。
12.根据权利要求7或8所述的半导体装置的制造方法,其特征在于,
所述键合线的线径为450μm以上且550μm以下的范围,
所述金属膜为含有磷和硼中的至少一种的镍合金膜。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN87107402A (zh) * | 1986-12-12 | 1988-06-22 | 株式会社东芝 | 半导体器件 |
JP2002222826A (ja) * | 2001-01-29 | 2002-08-09 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2004179484A (ja) * | 2002-11-28 | 2004-06-24 | Toyota Motor Corp | ワイヤが接合されている半導体装置の製造方法 |
JP2004200644A (ja) * | 2002-10-22 | 2004-07-15 | Kyocera Corp | 配線基板 |
JP2009076703A (ja) * | 2007-09-21 | 2009-04-09 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
US20100133688A1 (en) * | 2008-12-03 | 2010-06-03 | Renesas Technology Corp. | Semiconductor integrated circuit device |
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Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN87107402A (zh) * | 1986-12-12 | 1988-06-22 | 株式会社东芝 | 半导体器件 |
US5060051A (en) * | 1986-12-12 | 1991-10-22 | Kabushiki Kaisha Toshiba | Semiconductor device having improved electrode pad structure |
JP2002222826A (ja) * | 2001-01-29 | 2002-08-09 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
JP2004200644A (ja) * | 2002-10-22 | 2004-07-15 | Kyocera Corp | 配線基板 |
JP2004179484A (ja) * | 2002-11-28 | 2004-06-24 | Toyota Motor Corp | ワイヤが接合されている半導体装置の製造方法 |
JP2009076703A (ja) * | 2007-09-21 | 2009-04-09 | Fuji Electric Device Technology Co Ltd | 半導体装置 |
US20100133688A1 (en) * | 2008-12-03 | 2010-06-03 | Renesas Technology Corp. | Semiconductor integrated circuit device |
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