CN110222366B - Design method of output impedance matching network with high harmonic suppression function - Google Patents
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Abstract
The invention discloses a design method of an output impedance matching network with a high harmonic suppression function, which provides more design freedom for engineering personnel by utilizing a multi-stage T-shaped network for design on the premise of not increasing the circuit complexity, achieves better harmonic suppression capability within a limited in-band gain flatness range, and achieves the purpose of improving the power amplifier efficiency.
Description
Technical Field
The invention relates to the technical field of radio frequency integrated circuits, in particular to a design method of an output impedance matching network with a high harmonic suppression function.
Background
A Radio Frequency Power Amplifier (RFPA) is located at the end of a transmitter in a communication system, and is used for performing multi-stage amplification on a low-Power Radio Frequency signal generated by a modulation oscillation circuit, and when the requirement of an output Power index is met, the low-Power Radio Frequency signal can be fed to an antenna and radiated. Therefore, as one of the core functional modules in the communication system, the power amplifier directly affects important indexes of the device, such as communication quality, operating bandwidth, battery life, and the like. In huge handheld mobile terminal market now, because the power amplifier compares other subassemblies in the transceiver and consumes more energy, the duration of a journey that equipment has often been decided to its height of efficiency, has also influenced user experience indirectly, so, it is a focus of power amplifier product research to promote efficiency, also agrees with energy-concerving and environment-protective sustainable development's new era theory.
From the conservation of power, the total output power of the amplifier is equal to the sum of the fundamental wave and each harmonic power at the output end, and the heat loss in the transistor is added. To maximize the efficiency of the power amplifier, the fundamental power distributed to the load should be increased as much as possible, and the useless higher harmonic components and the internal loss of the transistor should be reduced. Since transistors have a lot of parasitic parameters and they change with the change of working environment, the improvement scheme for the internal loss power is generally difficult to achieve the ideal effect. In contrast, the purpose of high harmonic suppression can be realized by reasonably designing an output impedance matching network, and meanwhile, a standard 50 omega load is matched to the optimal impedance meeting specific performance; to maintain a certain bandwidth, we have traditionally constructed using a multi-stage down-conversion low-pass L-shaped network.
For the purpose of analysis, the single-segment L-shaped (two-element) network is described as necessary:
as shown in FIG. 1, the L-shaped matching circuit inserted in the dotted frame can match the load R L Down to a source impedance R S Parallel capacitance can reduce R L A value of (d), acting as a narrow-band impedance transformer; the series inductance cancels the capacitive reactance generated after the parallel-serial conversion, so that a small value pure resistor R is seen at the source end s 。
The impedance transformation ratio q is defined as:
and the following relationships exist:
Q＝q；
wherein Q is the quality factor of the matching network, X n Is the impedance of the corresponding element. In order to realize the harmonic suppression function, a small inductor is usually connected in series on a parallel capacitor branch circuit, and the small inductor and a capacitor are in common resonance at a specified harmonic frequency, so that the corresponding harmonic is short-circuited to the ground, and useless real power is prevented from being generated on a load, and the efficiency is improved; because the frequency response characteristic of the original matching network is changed by the additional series inductance, in order to compensate the frequency offset, the LC resonance trap circuit is redesigned by simple calculation to maintain the original matching state, and the method comprises the following steps:
wherein, C eq For LC series circuits at fundamental frequency omega 0 Equivalent capacitance of r For harmonic frequencies, fundamental frequency being the centre frequency, ω 0 ＝2πf 0 。
The complete multi-section L-shaped matching network design with harmonic suppression of order 2, 3, 5 is shown in fig. 2.
The traditional high harmonic suppression matching method is simple and easy to use, elements in the network can be assigned by a Smith chart method or preliminary calculation to observe the effect, and the elements are replaced by actual consumable elements at the later stage and combined with simulation to carry out final optimization tuning; due to the characteristics of clear flow and accurate initial value setting, the steps can be further developed into efficient computer programming processing, and therefore design time can be saved greatly.
However, for an output impedance matching network for a specific application, compromise consideration is often required among a plurality of parameters such as an impedance transformation ratio, out-of-band harmonic suppression, transmission loss (insertion loss) of the network, occupied area and the like, and L-shaped matching can only specify two of a center frequency, an impedance matching ratio and a Q value (bandwidth), and the lack of design freedom makes it difficult to apply to a more complex and efficient broadband multimode-multiband communication system. Bandwidth (BW) being the center frequency f 0 Quality factor Q.
The output matching network of the power amplifier applied to the handheld mobile terminal needs to convert a standard 50 omega load to a small impedance of only a few ohms so as to meet the requirement of high output power, the multi-stage low-pass L-shaped matching can only specify two free quantities, and after the impedance transformation ratio of each stage is determined according to the actual requirement and the selection range of element values, the Q values of a single section and the whole matching network are also determined, namely the traditional method can not effectively control the working bandwidth.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, meet the requirements of future 5G wireless communication on broadband, high efficiency and high linearity, and provide a design method of an output impedance matching network with a high harmonic suppression function. By utilizing the multi-stage T-shaped network for design, on the premise of not increasing the circuit complexity, more design freedom degrees are provided for engineering personnel, and the purpose of improving the power amplifier efficiency is achieved by achieving better harmonic suppression capability within a limited in-band gain flatness range.
In order to realize the purpose, the technical scheme provided by the invention is as follows:
the design is carried out by utilizing a multistage T-shaped matching network, and the specific steps are as follows:
a1: drawing up the optimal source impedance R according to the design index s Then, constructing a traditional multistage L-shaped matching network for reference comparison;
a2: designing an LC resonance circuit with frequency offset compensation;
a3: observing an S21 curve of the cascade network through schematic diagram simulation, determining the harmonic suppression effect and in-band gain flatness which can be achieved by the traditional method, and evaluating the difference between the current linearity and the design index;
a4: matching Q of single-section or multi-section T-shaped network in multi-stage T-shaped network according to the evaluated result in the step A3 n Setting the value of Q to be greater than the number of corresponding sections in the conventional method n A value;
a5: from the respective Q of the determined multi-stage network n Value and center frequency f 0 Determining parameter values of all elements in the network by combining the influence of the blocking capacitor with the higher harmonic wave needing short circuit treatment;
a6: observing an S21 curve of the cascade network through schematic diagram simulation, and determining the harmonic suppression effect and in-band gain flatness which can be achieved by adopting the method of the multi-stage T-shaped matching network;
a7: adjusting the cascade T-shaped matching network according to the simulation result and the index requirement, and ensuring that the designed output impedance matching network has enough harmonic suppression allowance on the premise that the in-band insertion loss fluctuation is within a tolerance range so as to counteract the influence caused by component models, simulation precision and processing errors;
a8: and (4) replacing all the elements obtained by optimizing in the step A7 with consumed actual elements, and performing iterative optimization tuning on the actual circuit schematic diagram, namely repeating the step A7 until all the design indexes are met.
Further, when the dc blocking capacitance has a large value and neglects the influence on the network, the multi-stage T-shaped matching network in step a4 is composed of a plurality of single-stage T-shaped networks; when the blocking capacitor has a small value and the influence of the blocking capacitor on the network cannot be ignored, the multi-stage T-shaped matching network described in the step A4 is composed of a single-stage T-shaped network and an L-shaped network.
Further, after the parallel capacitor C in the single-section T-shaped network is divided into two parts, the network is equivalently regarded as two back-to-back L-shaped circuits as a whole;
by a load R L First up-converted to an intermediate resistance R at the junction of two capacitors I Then down converted to R by a second L-shape match S (ii) a So that a high Q value is obtained even under the condition of giving an overall conversion ratio, thereby realizing high harmonic suppression;
the Q value of the network is:
when given Q, conversion resistance and center frequency f 0 Then, the above formula is used to obtain R I Then calculating the total capacitance C;
finally, the remaining two inductance parameter values in the network can be obtained by the following relation:
further, in step S8, when all the elements optimized in step S7 are replaced by lossy actual elements, three-dimensional electromagnetic simulation of the inductor is required to establish an accurate model.
Further, when the multi-stage T-shaped matching network is a three-stage T-shaped matching network, the impedance of the source is close to R s S3 network design at impedance transformation frequency point f 03 ，f 03 >f 0 (ii) a Will be close to the source impedance R L S1 network design at impedance transformation frequency point f 01 ，f 01 <f 0 (ii) a Will be located in the S1 network and the S3 networkThe S2 network is designed at the center frequency f 0 (ii) a So that a smooth gain is maintained over a large bandwidth.
Compared with the prior art, the principle of the scheme is as follows:
the traditional multi-stage L-shaped matching network design is changed into the design by utilizing a multi-stage T-shaped matching network.
Compared with the prior art, the scheme has the advantages that:
1. in the scheme, series inductors between two adjacent networks can be combined into a whole, the topological structure is the same as that of a traditional multistage cascade L-shaped matching network, and the topological structure is only needed to be disassembled in analysis, so that compromise can be performed among performance indexes such as impedance transformation ratio, out-of-band harmonic suppression, insertion loss of the matching network, working bandwidth and the like, and no element is added.
2. The harmonic suppression method can achieve a better harmonic suppression effect in a specified bandwidth on the premise of meeting the gain flatness, and improve the linearity and efficiency of the power amplifier.
3. All the advantages of the conventional L-type matching design are that the initial values of all the elements in the network can be derived by precise calculations, and an LC resonance trap circuit is also provided. The design of an efficient power amplifier output matching network can be carried out by means of cooperation of MATLAB (matrix laboratory) and ADS (automatic dependent Surveillance) high-frequency circuit design tools, and the time for optimizing tuning is greatly shortened.
4. The method has universality and universality, and can be equally applied to specific circuit designs such as Pi-shaped networks, up-impedance transformation and the like.
5. The gain flatness can be improved by reasonably setting the impedance transformation frequency points of each stage of network according to requirements so as to meet the scene of broadband application.
6. The influence of the DC blocking capacitor on the deviation caused by impedance transformation and element loss is comprehensively considered, the actual situation can be simulated as accurately as possible by designing the matching network according to the provided steps, and the current sheet success rate is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional single-segment L-shaped (two-element) network;
FIG. 2 is a schematic diagram of a conventional complete multi-segment L-shaped matching network with harmonic suppression of order 2, 3, and 5;
FIG. 3 is an equivalent diagram of T-shaped matching;
FIG. 4 is a schematic structural diagram of a complete three-segment T-shaped matching network;
FIG. 5 is a comparison graph of harmonic suppression effects of a conventional three-level L-shaped matching network and the three-level T-shaped matching network of the present invention;
FIG. 6 is a graph showing the comparison of the in-band gain flatness between a conventional three-stage L-shaped matching network and the three-stage T-shaped matching network of the present invention.
Detailed Description
The invention will be further illustrated with reference to specific examples:
in this embodiment, a three-level T-shaped matching network is used for design, and the specific steps are as follows:
a1: drawing up the optimal source impedance R according to the design index s Then, constructing a traditional multistage L-shaped matching network for reference comparison; it should follow the following rules: to ensure a central frequency point f within the working bandwidth 0 The values of the elements obtained by the calculation are located in an achievable appropriate range, and the impedance transformation ratio (i.e., the quality factor Q) of each stage of the single-section L-shaped network should be approximately: q. q.s 1 ≈1,q 2 ≈1-1.5,q 3 1.5-2.5 (corresponding to S1-S3 in FIG. 2, respectively);
a2: designing an LC resonance circuit with frequency offset compensation;
a3: observing an S21 curve of the cascade network through schematic diagram simulation, determining the harmonic suppression effect and in-band gain flatness which can be achieved by the traditional method, and evaluating the difference between the current linearity and the design index;
a4: matching Q of single-section or multi-section T-shaped network in three-stage T-shaped matching network according to the evaluation result of the step A3 n Setting the value of Q to be greater than the number of corresponding sections in the conventional method n A value; thus, the respective Q of the determined three-stage network n Value and center frequency f 0 The influence of the blocking capacitor is comprehensively considered together with the higher harmonic wave needing short circuit treatment, so that the parameter values of all elements in the network can be determined; it should be noted that S2 and S3 are the knots shown in FIG. 3The structure is divided into two sections of L-shaped matching to carry out element constant value calculation, which is concretely shown as follows; and S1 as the case may be.
When the value of the blocking capacitor is large and the influence of the blocking capacitor on the network is neglected, S1 is consistent with S2 and S3, and is of a T-shaped network structure, and the blocking capacitor needs to be divided into two sections of L-shaped matching to carry out element constant value calculation; when the value of the blocking capacitor is small and the influence of the blocking capacitor on the network cannot be ignored, S1 is a single-section L-shaped network structure;
a5: from the respective Q of the determined multi-stage network n Value and center frequency f 0 Determining parameter values of all elements in the network by combining the influence of the blocking capacitor with the higher harmonic wave needing short circuit treatment;
a6: observing an S21 curve of the cascade network through schematic diagram simulation, and determining the harmonic suppression effect and in-band gain flatness which can be achieved by adopting the method of the multi-stage T-shaped matching network;
a7: according to the simulation result and the index requirement, the cascade T-shaped matching network is adjusted, and the designed output impedance matching network is ensured to have enough harmonic suppression allowance under the premise that the in-band insertion loss fluctuation is within the tolerance range so as to counteract the influence caused by the component model, the simulation precision and the machining error;
a8: replacing all the elements obtained by optimizing in the step A7 with consumed actual elements, wherein three-dimensional Electromagnetic (EM) simulation needs to be carried out on the inductor to establish a more accurate model; because the quality factor of the inductor is very low compared to the capacitance, this means that there is a large loss, which has a non-negligible effect on the circuit performance; and finally, performing iterative optimization tuning on the actual circuit schematic diagram, namely repeating the step A7 until all design indexes are met.
A9: if broadband matching is to be realized, the impedance is close to the source impedance R s S3 network design at impedance transformation frequency point f 03 ，f 03 >f 0 (ii) a Will be close to the source impedance R L S1 network design at impedance transformation frequency point f 01 ，f 01 <f 0 (ii) a Designing the S2 network between the S1 network and the S3 network at the center frequency f 0 (ii) a So that the gain is kept stable in a large wide band(ii) a It should be noted that since S1 is artificially set to perform impedance transformation below the center frequency, S1 appears inductive at S2, compensating for the inductance required by S2, and similarly, the cascaded network of S1 and S2 seen at S3 appears inductive, so that the value of the series inductance parameter at the right side of S3 is set equal to the initial calculated value minus the perceived inductance value. However, the overall matching network appears to be capacitive for the output terminal of the power amplifier, and therefore, a small inductor needs to be added to the output node of the power amplifier to offset the extra capacitance.
In the step a4, after the parallel capacitor C in the single-section T-shaped network is divided into two parts, the network is equivalently regarded as two back-to-back L-shaped circuits as a whole;
by a load R L First up-converted to an intermediate resistance R at the junction of two capacitors I Then down converted to R by a second L-shape match S (ii) a So that a high Q value is obtained even under the condition of giving an overall conversion ratio, thereby realizing high harmonic suppression;
the Q value of the network is:
when given Q, conversion resistance and center frequency f 0 Then, the above formula is used to obtain R I Then calculating the total capacitance C;
finally, the remaining two inductance parameter values in the network can be obtained by the following relation:
referring to fig. 5-6, in the embodiment, a better harmonic suppression effect can be achieved within a specified bandwidth on the premise of satisfying gain flatness, and linearity and efficiency of the power amplifier can be improved.
In addition, the embodiment can perform compromise consideration among performance indexes such as impedance transformation ratio, out-of-band harmonic suppression, insertion loss of the matching network, working bandwidth and the like without adding any element; since the series inductances between S3 and S2 and between S2 and S1 can be combined into one as shown in fig. 4, the present embodiment has substantially the same topology as the conventional three-stage cascaded L-shaped matching network, and only needs to be taken apart from the analysis. Thus, the present embodiment has obvious advantages on the premise of ensuring that the implementation complexity is approximately the same.
Furthermore, this embodiment has all the advantages of the conventional L-type matching design, i.e., the initial values of all the elements in the network can be derived by precise calculation, and also provides an LC resonance trap circuit. Therefore, the embodiment can design the high-efficiency power amplifier output matching network by means of cooperation of MATLAB (matrix laboratory) and ADS (automatic dependent surveillance broadcasting) high-frequency circuit design tools, and greatly shortens the time for optimizing tuning.
Finally, the present embodiment comprehensively considers the influence of the dc blocking capacitor on the deviation and the element loss caused by the impedance transformation, and the matching network design is performed according to the provided steps, so that the actual situation can be simulated as accurately as possible, and the success rate of the current sheet is improved.
The above-mentioned embodiments are merely preferred embodiments of the present invention, and the scope of the present invention is not limited thereto, so that variations based on the shape and principle of the present invention should be covered within the scope of the present invention.
Claims (5)
1. A design method of an output impedance matching network with a high harmonic suppression function is characterized in that a multistage T-shaped matching network is used for design, and the specific steps are as follows:
a1: drawing up a source impedance R according to the design index s Then constructing a multi-stage L-shaped matching network for reference comparison;
a2: designing an LC resonance circuit with frequency offset compensation;
a3: observing an S21 curve of the cascade network through schematic diagram simulation, determining the harmonic suppression effect and in-band gain flatness which can be achieved by the multistage L-shaped matching network, and evaluating the difference between the current linearity and the design index;
a4: matching Q of single-section or multi-section T-shaped network in multi-stage T-shaped network according to the evaluated result in the step A3 n Setting a value of Q greater than the number of corresponding nodes of the multi-stage L-shaped matching network n A value;
a5: from the respective Q of the determined multi-stage network n Value and center frequency f 0 Determining parameter values of all elements in the network by combining the influence of the blocking capacitor with the higher harmonic wave needing short circuit treatment;
a6: observing an S21 curve of the cascade network through schematic diagram simulation, and determining the harmonic suppression effect and in-band gain flatness which can be achieved by adopting the method of the multi-stage T-shaped matching network;
a7: adjusting the cascade T-shaped matching network according to the simulation result and the index requirement, and ensuring that the designed output impedance matching network has enough harmonic suppression allowance on the premise that the in-band insertion loss fluctuation is within a tolerance range so as to counteract the influence caused by component models, simulation precision and processing errors;
a8: and (4) replacing all the elements obtained in the step A7 with consumed actual elements, and performing iterative tuning on the actual circuit schematic diagram, namely repeating the step A7 until all the design indexes are met.
2. The method as claimed in claim 1, wherein the multi-stage T-shaped matching network in step a4 is composed of a plurality of single-section T-shaped networks when the blocking capacitance has a large value and neglects the influence on the network; when the blocking capacitor has a small value and the influence of the blocking capacitor on the network cannot be ignored, the multi-stage T-shaped matching network described in the step A4 is composed of a single-stage T-shaped network and an L-shaped network.
3. The method as claimed in claim 2, wherein the parallel capacitor C in the single-section T-shaped network is divided into two parts, and the network is equivalently regarded as two back-to-back L-shaped circuits as a whole;
by a load R L First up-converted to an intermediate resistance R at the junction of two capacitors I Then down converted to R by a second L-shape match S (ii) a So that a high Q value is obtained even under the condition of giving an overall conversion ratio, thereby realizing high harmonic suppression;
the Q value of the network is:
when given Q, conversion resistance and center frequency f 0 Then, the above formula is used to obtain R I Then calculating the total capacitance C;
finally, the remaining two inductance parameter values in the network can be obtained by the following relation:
4. the method as claimed in claim 1, wherein in the step A8, when the elements obtained in the step a7 are all replaced by lossy actual elements, three-dimensional electromagnetic simulation of the inductor is required to establish an accurate model.
5. The method as claimed in claim 1, wherein the multi-stage T-shaped matching network is a three-stage T-shaped matching network, and the source impedance R is close to the multi-stage T-shaped matching network s S3 network design at impedance transformation frequency point f 03 ，f 03 >f 0 (ii) a Will be close to the source impedance R L S1 network design at impedance transformation frequency point f 01 ，f 01 <f 0 (ii) a Designing the S2 network between the S1 network and the S3 network at the center frequency f 0 (ii) a So that a smooth gain is maintained over a large bandwidth.
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| CN112953592B (en) * | 2021-01-22 | 2023-04-07 | RealMe重庆移动通信有限公司 | Radio frequency circuit, electronic equipment and transmission method of radio frequency signal |
| CN114792080B (en) * | 2022-06-24 | 2022-09-20 | 广州联星科技有限公司 | Design method of broadband power amplifier chip |
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