CN105631109A - Design method for radio frequency ultra-wide band high-efficiency power amplifier and circuit - Google Patents
Design method for radio frequency ultra-wide band high-efficiency power amplifier and circuit Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Abstract
The invention discloses a design method for a radio frequency ultra-wide band high-efficiency power amplifier and a circuit. The design method includes the steps of a multi-frequency point transistor input and output impedance test, design of a maximum power transmission output impedance matching network, design of a wide band input multi-section impedance matching network, design of an input harmonic suppression network and an output harmonic suppression network and design of a transistor offset network. The transistor input and output impedance test technology achieves precise calculation of transistor input and output impedance. The maximum power transmission output impedance matching network achieves transistor impedance matching and maximum power transmission. The wide band input multi-section impedance matching network achieves wide band transistor input impedance matching. The design of the input harmonic suppression network and the output harmonic suppression network eliminates higher harmonic influences at the input end and the output end of a transistor, reduce losses and improve power additional efficiency of the amplifier. The design of the offset network provides working voltage of the transistor. The power amplifier can acquire higher frequency bandwidth, output power and power additional efficiency.
Description
Technical field
The present invention relates to the design field of power amplifier, more specifically, the present invention relates to the designing technique of a kind of radio frequency ultra broadband high efficiency power amplifier, it is applicable to design of Simulation and the scientific research of the high performance power amplifier in the fields such as radio communication, electronic countermeasure, radar, navigation, and the overall performance index improving related system is significant.
Background technology
Radio-frequency power amplifier is widely used in the transmitting equipment of the systems such as radio communication, electronic countermeasure, radar, navigation, power amplifier all has great importance for the research of the improvement of systematic function, New function and new opplication, and therefore the performance of hoisting power amplifier becomes the focus that each system manufacturer is paid close attention to. The key problem of power amplifier research is broadband and high efficiency, in wide-band amplifier research field, due to S11And S21It is the function about frequency, S11With frequency every octave decline 6dB, S21With frequency every octave rising 6dB, S11And S21Determine the stability of circuit, therefore in wider frequency band, circuit stability work cannot be realized, noise coefficient and the standing wave of amplifier worsen as well as the conversion of frequency, at present, the method improving power amplifier bandwidth of operation mainly has, and compensates matching network, distributed amplifier, reversed feedback amplifier, balanced amplifier, active matching formula amplifier, resistance reactance matched amplifier etc. And the technical development that strengthens efficiency is relatively delayed, it is possible to the technology improving efficiency power amplifier common are: Doherty technology, envelope-tracking (Envelopetracking), envelope eliminate regeneration techniques (Envelopeeliminationrestoration), adaptive-biased technology (adaptivebias), peak value reduction technology (Crestfactorreduction) etc. But, find to want a certain item index of boost amplifier relatively easily to solve in theoretical research and actual engineering design, but when broadband and high efficiency are put together, design difficulty will double, and many times this is practically impossible to the imagination of realization.
Summary of the invention
Goal of the invention: seek to solve at present in the deficiency of radio frequency ultra broadband high-efficiency amplifier design studies art, for the technical problem in wideband power amplifier design process, a series of method for designing, circuit structure and network integration scheme are proposed, from the angle of theory analysis, design of Simulation and engineering practice, ultra broadband high efficiency power amplifier designed this academia difficult problem, it is provided that the resolution policy of whole set of system.
Technical scheme: the invention discloses the method for designing of a kind of ultra broadband high efficiency power amplifier, including multifrequency point transistor input and output testing impedance, the design of maximum power transfer output impedance matching networks, broadband input more piece impedance matching network design, input harmonics Suppression network and the design of output harmonic wave Suppression network, transistor biasing network design.
Further optimization as the present invention, multifrequency point transistor input/output testing impedance of the present invention, the method adopting impedance traction iteration tests, operating frequency according to transistor, a first given transistor input impedance initial value, transistor output and power efficiency are analyzed, calculate when maximum power transfer and power efficiency, transistor output impedance, then further according to transistor output impedance, calculate the input impedance of transistor further, and by iterative analysis method, finally determine that transistor is at first-harmonic, the input/output impedance of second harmonic and triple-frequency harmonics frequency.
Multifrequency point transistor input/output testing impedance of the present invention adopts iteration tests circuit, it signal source including providing radiofrequency signal, transistor, the single port S parameter actuator being connected with described transistor drain, the first DC source being connected with transistor gate, the second DC source being connected with described transistor drain, the first ammeter for test transistor grid and the current signal of the first DC source branch road, the second ammeter for test transistor drain electrode with the current signal of single port S parameter actuator branch road, the 3rd ammeter for test transistor drain electrode and the circuit signal of the second DC source branch road, utilize AdvancedDesignSystem electromagnetic simulation software, artificial circuit is built in design.
Further optimization as the present invention, maximum power transfer outfan impedance matching network of the present invention design realizes the conjugate impedance match of transistor output impedance and terminating load impedance, adopting microstrip line construction, this maximum power transfer outfan impedance matching network merges with output harmonic wave Suppression network and transistor drain biasing networks.
Further optimization as the present invention, broadband of the present invention input more piece impedance matching network design realizes the conjugate impedance match of transistor input impedance and source impedance, adopt the matching network of mixing lumped parameter and transmission line element, the matching network of this mixing lumped parameter and transmission line element and input harmonics Suppression network and the transistor gate bias network integration, can suitably access consumption gain compensation matching network in the design, it is achieved compromise certain between gain, bandwidth and reflection coefficient.
Further optimization as the present invention, input harmonics Suppression network of the present invention and the design of output harmonic wave Suppression network, adopt the microstrip transmission line harmonic suppression network of open-end in parallel, second harmonic and triple-frequency harmonics are suppressed by input and outfan at transistor respectively, harmonic suppression network can be effectively improved transistor output and power adnexa efficiency, input harmonic suppression network part circuit structure can merge mutually with gate bias network, output harmonic wave Suppression network part circuit structure can merge mutually with drain bias network, combined effect.
Further optimization as the present invention, transistor biasing network of the present invention design provides transistor running voltage to include transistor drain biasing networks and transistor gate bias network, all adopt microstrip line construction, transistor drain biasing networks completes the suppression to outfan triple-frequency harmonics, transistor gate bias network completes the suppression to input triple-frequency harmonics, the designing technique that transistor drain biasing networks and output harmonic wave Suppression network merge mutually is adopted in transistor drain biasing networks designs, biasing networks completes the realization simultaneously participating in drain electrode harmonic restraining function of network function, adopting the designing technique that transistor drain biasing networks and input harmonic suppression network merge mutually in transistor gate bias network design, gate bias network completes the realization simultaneously participating in grid harmonic restraining function of network function.
The invention also discloses a kind of ultra broadband high efficiency power amplifier circuit, including transistor, transistor input network structure and transistor output network structure, described transistor input network structure includes sequentially forming the input impedance matching network of high-pass matching network according to signal input direction, for eliminating the input harmonic suppression network of the harmonic component of input signal and for controlling the transistor gate bias network of transistor gate voltage; Described transistor output network structure provides the transistor drain biasing networks of transistor DC running voltage, the output harmonic wave Suppression network that transistor output harmonic wave is suppressed and the output impedance matching networks for the impedance of output harmonic wave Suppression network being mated with load impedance in operating frequency according to output side signal to including successively, described transistor gate bias Web-compatible is in input harmonic suppression network, and described transistor drain biasing networks is compatible with in output harmonic wave Suppression network.
Further optimization as the present invention, input impedance matching network of the present invention includes the 8th microstrip transmission line, the 7th microstrip transmission line and the 3rd electric capacity, described 8th microstrip transmission line and the series connection of the 7th microstrip transmission line, the 3rd electric capacity and the 8th microstrip transmission line are in parallel; Described input harmonic suppression network includes for controlling impedance first microstrip transmission line of input low frequency harmonic content, the second microstrip transmission line and the 3rd microstrip transmission line.
Beneficial effect: the present invention compared with prior art, has the advantage that this Designing power amplifier technology of the present invention can obtain higher frequency bandwidth, output and power added efficiency.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the method for designing of a kind of radio frequency ultra broadband high efficiency power amplifier of technical solution of the present invention;
Fig. 2 is impedance iteration tests load impedance of the present invention test circuit theory diagrams;
Fig. 3 is impedance analysis smith circle diagram of the present invention;
Fig. 4 is input more piece impedance matching network circuit theory diagrams of the present invention;
Fig. 5 is input schematic network structure of the present invention;
Fig. 6 is outfan schematic network structure of the present invention;
Fig. 7 is the designing technique instantiation circuit theory diagrams of a kind of radio frequency ultra broadband high efficiency power amplifier of the present invention.
Detailed description of the invention
Below in conjunction with specific embodiment, the present invention is described in detail; but illustrate that protection scope of the present invention is not limited to the concrete scope of the present embodiment simultaneously; based on the embodiment in the present invention; the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly falls into the scope of protection of the invention.
It should be noted that in describing the invention, except as otherwise noted, " multiple " are meant that two or more; Term " on ", D score, "left", "right", " interior ", " outward ", " front end ", " rear end ", " head ", the orientation of the instruction such as " afterbody " or position relationship be based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than instruction or hint indication device or element must have specific orientation, with specific azimuth configuration and operation, be therefore not considered as limiting the invention. Additionally, term " first ", " second ", " the 3rd " etc. are only for descriptive purposes, and it is not intended that indicate or hint relative importance.
Referring to Fig. 1, the present embodiments relate to the method for designing of a kind of radio frequency ultra broadband high efficiency power amplifier, specifically include: the design of multifrequency point transistor input and output testing impedance technology, maximum power transfer output impedance matching networks, broadband input more piece impedance matching network design, input harmonics Suppression network and the design of output harmonic wave Suppression network, transistor biasing network design.
The multifrequency point transistor input and output testing impedance technology of the present embodiment, for the measurement of multifrequency point transistor characteristic impedance, provides basis for realizing wide-band impedance coupling; Maximum power transfer output impedance matching networks designs, and for improving the output of power amplifier, improves efficiency of amplitude simultaneously; Broadband input more piece impedance matching network design, for realizing the coupling to Transistor Impedance in wide frequency range; Input harmonics Suppression network and the design of output harmonic wave Suppression network, for the adjustment of multiple transistor input and outfan higher harmonic components, reduce loss, improve the power added efficiency of power amplifier; Transistor biasing network is designed, for guaranteeing that the duty of transistor and power supply are powered.
Referring to Fig. 2, 3, multifrequency point transistor input and output testing impedance technology of the present invention, the method adopting impedance iteration tests, iteration tests circuit structure is as shown in Figure 2, this circuit includes: include the signal source 1 providing radiofrequency signal, transistor 7, drain the single port S parameter actuator 8 being connected with described transistor 7, the first DC source 5 being connected with transistor 7 grid, drain the second DC source 6 being connected with described transistor 7, the first ammeter 2 for test transistor 7 grid and the current signal of the first DC source branch road, the second ammeter 3 for test transistor 7 drain electrode with the current signal of single port S parameter actuator 8 branch road, the 3rd ammeter 4 for test transistor 7 drain electrode and the circuit signal of the second DC source branch road, single port S parameter actuator 8, wherein S11The phase and amplitude of parameter consecutive variations in unit circle, for transistor 7 outfan, be equivalent to be connected to a continuous transformation load, as shown in Figure 3, output corresponding to every load impedance point can section out on smith circle diagram, such as load impedance point 13.
When carrying out transistor output testing impedance, first, it is assumed that transistor sending-end impedance, then start load impedance is scanned, from scanning result, finally find out maximum power output point, the load impedance value of correspondence can be found.
Branch current and the direct voltage source voltage tested by each branch current table in circuit can calculate each branch power situation, according to formula calculated as below:
Power added efficiency=(output-input power)/DC input power
The transistor power added efficiency that each load impedance value is corresponding can be calculated, between peak power output and peak power added efficiency, carry out the consideration compromised.
According to the transistor output impedance recorded, by identical method of testing, calculate transistor input impedance, repeatedly test by that analogy, and finally determine transistor input and output impedance.
Referring to Fig. 4, broadband of the present invention input more piece impedance matching network design, adopt the matching network of mixing lumped parameter and transmission line element, including series connection microstrip transmission line 16 and shunt capacitance 17. For the design of this impedance matching network structure, equivalence on the single-frequency of the available asymmetrical load transmission line of lumped parameter �� shape ladder joint, the transmission abcd matrix formula of these lumped parameters and distribution ladder joint is as follows:
Lumped parameter transmission abcd matrix:
Distributed constant transmission abcd matrix:
In above formula, ��0For broadband mid frequency, ��0It it is the electrical length of transmission line when mid frequency. Thus can obtain:
When designing match circuit by single-frequency equivalence techniques, the lumped parameter �� shape that design is substituted saves, first save from the �� shape of lumped parameter and form symmetry and have and wait the �� shape of electric capacity to save, then the computing formula utilizing parameter that lumped parameter equivalence �� shape saves and above-mentioned derivation calculates the parameter of the electric capacity �� shape joints such as symmetry, after being provided with transmission line electrical length, it is possible to calculate Z0And CT, finally, utilize the lumped parameter �� shape joint of the �� shape joint alternate design of equivalence.
The particular circuit configurations adopting above-mentioned method for designing the present embodiment includes input network structure as shown in Figure 5 and outfan network structure as shown in Figure 6, this input network structure it include input impedance matching network 28, input harmonics Suppression network 26, gate bias network 25, wherein input harmonics Suppression network 26 eliminates the higher harmonic components of input end signal, reduce circuit power loss, improve the power added efficiency of amplifier, gate bias network 25 is used for controlling transistor gate voltage, realize normal table work for transistor to provide safeguard, input impedance matching network 28 forms a high-pass matching network and realizes the conjugate impedance match of input harmonics Suppression network and source impedance, owing to amplifier in harmonic wave generally comprises multiple higher harmonic components, experimental results demonstrate that the energy that the relatively low harmonics frequency component of frequency comprises is bigger, in the present embodiment, the low-order harmonic component comprising energy maximum will be analyzed.
As shown in Figure 7, input network physical circuit includes the first capacitance 30, input impedance matching network 28, input harmonics Suppression network 26, gate bias network 25 and gate-voltage source 32, wherein input impedance matching network 28 includes the 8th microstrip transmission line L8, 7th microstrip transmission line L7 and the three electric capacity C3, 8th microstrip transmission line L8, 7th microstrip transmission line L7, first capacitance 30 is connected, 3rd electric capacity C3 is in parallel with the 8th microstrip transmission line L8 being in series and the first capacitance 30, this input harmonics Suppression network 26 includes the first microstrip transmission line L1, second microstrip transmission line L2 and the three microstrip transmission line L3, transistor input is connected with input impedance matching network 28 by the second microstrip transmission line L2, first microstrip transmission line L1, second microstrip transmission line L2 is used for obtaining the Low ESR with the negative imaginary part of second harmonic source impedance, gate-voltage source 32 constitutes gate bias network 25 by the 3rd microstrip transmission line L3 access transistor, this gate bias network 25 also includes the first shunt capacitance C1, in the circuit, first microstrip transmission line L1, second microstrip transmission line L2 and the three microstrip transmission line L3 is used for controlling the impedance of input low frequency harmonic content, the length of the 3rd microstrip transmission line L3 is 1/4th operation wavelengths, realize the control to triple-frequency harmonics.
Referring to Fig. 6, the outfan network structure of the present invention includes output impedance matching networks 29, output harmonic wave Suppression network 27, drain bias network 24. Amplifier out harmonic wave generally comprises multiple higher harmonic components, experimental results demonstrate that the energy that the relatively low harmonic component of frequency comprises is bigger. In the present embodiment, the low-order harmonic component comprising energy maximum will be analyzed.
Shown in Figure 7, outfan network physical circuit includes the second capacitance 31, output impedance matching networks 29, output harmonic wave Suppression network 27, drain bias network 24 and drain electrode direct voltage source 33, this output harmonic wave Suppression network 27 includes the 4th microstrip transmission line L4, 5th microstrip transmission line L5 and the six microstrip transmission line L6, output impedance matching networks 29 is connected with transistor output by the 5th microstrip transmission line L5, drain electrode direct voltage source 33 constitutes drain bias network 24 by the 6th microstrip transmission line L6 access transistor, this drain bias network 24 also includes the second shunt capacitance C2, in the circuit, 6th microstrip transmission line L6 length is 1/4th of operation wavelength, triple-frequency harmonics is produced a short circuit current by the point of intersection at the 5th microstrip transmission line L5 and the six microstrip transmission line L6, 5th microstrip transmission line L5 produces triple-frequency harmonics reactance at the outfan of transistor, the length of the 4th the 5th microstrip transmission line L4 is 1/4th of triple-frequency harmonics wavelength, at the intersection point of the 4th microstrip transmission line L4 and the five microstrip transmission line L5 to second_harmonic generation one open circuit, 5th microstrip transmission line L5 gives the optimum load impedance of transistor at second harmonic place, the length of the second microstrip transmission line L2 depends on the parasitic parameter of transistor.
Referring to Fig. 7, input impedance matching network 28 adopts broadband input more piece impedance matching network design, including the matching network of mixing lumped parameter and transmission line element, including series connection microstrip transmission line and shunt capacitance. It addition, the left end at input impedance matching network 28 accesses the first capacitance 30, it is to avoid the direct grid current voltage source 32 interference to front stage circuits. Output impedance matching networks 29 adopts transforming impedance transmission line structure to realize mating of output harmonic wave Suppression network 27 impedance and terminal impedance. It addition, the right-hand member in output impedance matching networks 29 is concurrently accessed the second capacitance 31, it is to avoid the drain electrode direct voltage source 33 interference to late-class circuit.
The present embodiment complete circuit is referring to Fig. 7, and gate bias network 25 and input harmonics Suppression network 26 merge mutually. Drain bias network 24 and output harmonic wave Suppression network 27 merge mutually, can reduce the complexity of circuit structure after making full use of microstrip line integration technology scheme, reduce design difficulty, reduce circuit size simultaneously, save cost.
The present embodiment can be greatly improved working band width and the work efficiency of existing power amplifier, has wide application prospect.
Embodiments of the invention provide for example with for the purpose of describing, and are not exhaustively or limit the invention to disclosed form. Many modifications and variations are apparent from for the ordinary skill in the art. Selecting and describing embodiment is in order to principles of the invention and practical application are better described, and makes those of ordinary skill in the art it will be appreciated that the present invention is thus design is suitable to the various embodiments with various amendments of special-purpose.
Claims (8)
1. the method for designing of a ultra broadband high efficiency power amplifier, it is characterised in that: include multifrequency point transistor input and output testing impedance, the design of maximum power transfer output impedance matching networks, broadband input more piece impedance matching network design, input harmonics Suppression network and the design of output harmonic wave Suppression network, transistor biasing network design.
2. the method for designing of a kind of ultra broadband high efficiency power amplifier according to claim 1, it is characterized in that: described multifrequency point transistor input/output testing impedance, the method adopting impedance traction iteration tests, operating frequency according to transistor, a first given transistor input impedance initial value, transistor output and power efficiency are analyzed, calculate when maximum power transfer and power efficiency, transistor output impedance, then further according to transistor output impedance, calculate the input impedance of transistor further, and by iterative analysis method, finally determine that transistor is at first-harmonic, the input/output impedance of second harmonic and triple-frequency harmonics frequency.
3. the method for designing of a kind of ultra broadband high efficiency power amplifier according to claim 1, it is characterized in that: the design of described maximum power transfer outfan impedance matching network realizes the conjugate impedance match of transistor output impedance and terminating load impedance, adopting microstrip line construction, this maximum power transfer outfan impedance matching network merges with output harmonic wave Suppression network and transistor drain biasing networks.
4. the method for designing of a kind of ultra broadband high efficiency power amplifier according to claim 1, it is characterized in that: the input more piece impedance matching network design of described broadband realizes the conjugate impedance match of transistor input impedance and source impedance, adopt the matching network of mixing lumped parameter and transmission line element, the matching network of this mixing lumped parameter and transmission line element and input harmonics Suppression network and the transistor gate bias network integration.
5. the method for designing of a kind of ultra broadband high efficiency power amplifier according to claim 1, it is characterized in that: described input harmonics Suppression network and the design of output harmonic wave Suppression network, adopting the microstrip transmission line harmonic suppression network of open-end in parallel, second harmonic and triple-frequency harmonics are suppressed by input and outfan at transistor respectively.
6. the method for designing of a kind of ultra broadband high efficiency power amplifier according to claim 1 or 5, it is characterized in that: the design of described transistor biasing network provides transistor running voltage to include transistor drain biasing networks and transistor gate bias network, all adopt microstrip line construction, transistor drain biasing networks completes the suppression to outfan triple-frequency harmonics, transistor gate bias network completes the suppression to input triple-frequency harmonics, transistor drain biasing networks merges with output harmonic wave Suppression network, transistor gate bias network merges with input harmonics Suppression network.
7. the circuit of the method for designing of the employing a kind of ultra broadband high efficiency power amplifier described in claim 1, it is characterized in that: include transistor, transistor input network structure and transistor output network structure, described transistor input network structure according to signal input direction include sequentially forming the input impedance matching network of high-pass matching network, for eliminate input signal harmonic component input harmonic suppression network and for controlling the transistor gate bias network of transistor gate voltage; Described transistor output network structure provides the transistor drain biasing networks of transistor DC running voltage, the output harmonic wave Suppression network that transistor output harmonic wave is suppressed and the output impedance matching networks for the impedance of output harmonic wave Suppression network being mated with load impedance in operating frequency according to output side signal to including successively, described transistor gate bias Web-compatible is in input harmonic suppression network, and described transistor drain biasing networks is compatible with in output harmonic wave Suppression network.
8. a kind of ultra broadband high efficiency power amplifier circuit according to claim 7, it is characterized in that: described input impedance matching network includes the 8th microstrip transmission line, the 7th microstrip transmission line and the 3rd electric capacity, described 8th microstrip transmission line and the series connection of the 7th microstrip transmission line, the 3rd electric capacity and the 8th microstrip transmission line are in parallel; Described input harmonic suppression network includes the first microstrip transmission line of the impedance for controlling input low frequency harmonic content, the second microstrip transmission line and the 3rd microstrip transmission line.
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