CN108052733A - A kind of circuit design method and device - Google Patents
A kind of circuit design method and device Download PDFInfo
- Publication number
- CN108052733A CN108052733A CN201711309324.3A CN201711309324A CN108052733A CN 108052733 A CN108052733 A CN 108052733A CN 201711309324 A CN201711309324 A CN 201711309324A CN 108052733 A CN108052733 A CN 108052733A
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- CN
- China
- Prior art keywords
- circuit design
- input impedance
- output impedance
- load balance
- transistor
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/06—Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a kind of circuit design method and device, including：Input impedance and output impedance that chip or transistor are obtained by load balance factor are respectively written into different data files；Corresponding optimization aim is set respectively for the input impedance and the output impedance, objective optimization then is carried out to two data files, obtains corresponding match circuit.Solves the technical issues of circuit design that conventional method is not suitable for wideband power amplifer.
Description
Technical field
The present invention relates to technical field of circuit design more particularly to a kind of circuit design methods and device.
Background technology
Power amplifier (English name：Power amplifier), referred to as " power amplifier ", refer in given distortion rate condition
Under, maximum power output can be generated to drive the amplifier of a certain load (such as loud speaker).Power amplifier is in entire sound equipment
The pivotal role of " tissue, coordination " is played in system, can dominate whole system to a certain extent provide good sound
Matter exports.
The conventional method of design power amplifier circuit is first in Advanced Design System (Advanced Design
System, ADS) the inside does load balance factor to chip or transistor, and the input impedance and output for drawing chip or transistor hinder
It is anti-；Then input impedance and output impedance are matched by Smith's artwork (Smith Chart) instrument by 50 Ω；Do not stop finally
Adjusting parameter so as to obtaining desired power amplifier circuit.
However, this conventional method is only applicable to the circuit design of narrow band power amplifier, because wideband power amplifer
Circuit it is more complicated, parameter is more, thus adjusting parameter process need manually carry out, can take a substantial amount of time, thus pass
The method of system is not suitable for the circuit design of wideband power amplifer.
The content of the invention
The present invention provides a kind of circuit design method and devices, solve conventional method and are not suitable for broadband power amplification
The technical issues of circuit design of device.
The present invention provides a kind of circuit design method, including：
Input impedance and output impedance that chip or transistor are obtained by load balance factor are respectively written into different data
File；
Corresponding optimization aim is set respectively for the input impedance and the output impedance, then to two data
File carries out objective optimization, obtains corresponding match circuit.
Preferably,
Before the input impedance and output impedance write-in data file for obtaining chip or transistor by load balance factor,
It further includes：
Load balance factor is carried out to the chip or the transistor and obtains the input impedance and the output impedance.
The present invention provides a kind of circuit design device, including：
Writing module, input impedance and output impedance for chip or transistor to be obtained by load balance factor are write respectively
Enter different data files；
Objective optimization module, for setting corresponding optimization aim respectively for the input impedance and the output impedance,
Then objective optimization is carried out to two data files, obtains corresponding match circuit.
Preferably,
The circuit design device, further includes：
Load balance factor module, for the chip or the transistor are carried out load balance factor obtain the input impedance and
The output impedance.
As can be seen from the above technical solutions, the present invention has the following advantages：
Input impedance and output impedance that chip or transistor are obtained by load balance factor are first respectively written into data file,
Then corresponding optimization aim is set respectively for input impedance and output impedance, it is excellent then to carry out target to two data files
Change, obtain corresponding match circuit so that match circuit meets the corresponding optimization aim of input impedance and output impedance pair simultaneously
The optimization aim answered, compared with the prior art for, it is simpler, be not required labor costs go the plenty of time optimization circuit, more
It is suitble to do wideband circuit matching.
Description of the drawings
It in order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
To obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of flow diagram of the first embodiment of circuit design method provided by the invention；
Fig. 2 is a kind of flow diagram of the second embodiment of circuit design method provided by the invention；
Fig. 3 is a kind of structure diagram of the first embodiment of circuit design device provided by the invention；
Fig. 4 is a kind of structure diagram of the second embodiment of circuit design device provided by the invention.
Specific embodiment
An embodiment of the present invention provides a kind of circuit design method and devices, solve conventional method and are not suitable for broadband work(
The technical issues of circuit design of rate amplifier.
Goal of the invention, feature, advantage to enable the present invention is more apparent and understandable, below in conjunction with the present invention
Attached drawing in embodiment is clearly and completely described the technical solution in the embodiment of the present invention, it is clear that disclosed below
Embodiment be only part of the embodiment of the present invention, and not all embodiment.Based on the embodiments of the present invention, this field
All other embodiment that those of ordinary skill is obtained without making creative work, belongs to protection of the present invention
Scope.
Referring to Fig. 1, a kind of flow diagram of the first embodiment of circuit design method provided by the invention.
The present invention provides a kind of first embodiment of circuit design method, including：
Step 101, input impedance and output impedance that chip or transistor are obtained by load balance factor are respectively written into not
Same data file.
Data file can be SIP files.
Step 102, corresponding optimization aim is set respectively for input impedance and output impedance, then to two data files
Objective optimization is carried out, obtains corresponding match circuit.
Objective optimization is carried out to data file so that match circuit meets input impedance simultaneously and output impedance is corresponding excellent
Change target, optimization aim could be provided as being less than or equal to certain value, this value can be adjusted according to actual needs.
It should be noted that objective optimization belongs to the prior art, it is not detailed herein.
Referring to Fig. 2, a kind of flow diagram of the second embodiment of circuit design method provided by the invention.
The present invention provides a kind of second embodiment of circuit design method, including：
Step 201, load balance factor is carried out to chip or transistor and obtains input impedance and output impedance.
Step 202, input impedance and output impedance that chip or transistor are obtained by load balance factor are respectively written into not
Same data file.
S202 is identical with the content of S101 in the application first embodiment, and specific descriptions may refer to first embodiment S101
Content, details are not described herein.
Step 203, corresponding optimization aim is set respectively for input impedance and output impedance, then to two data files
Objective optimization is carried out, obtains corresponding match circuit.
S203 is identical with the content of S102 in the application first embodiment, and specific descriptions may refer to first embodiment S102
Content, details are not described herein.
Referring to Fig. 3, a kind of structure diagram of the first embodiment of circuit design device provided by the invention.
The present invention provides a kind of first embodiment of circuit design device, including：
Writing module 301, input impedance and output impedance for chip or transistor to be obtained by load balance factor divide
Different data files is not write.
Objective optimization module 302 is then right for setting corresponding optimization aim respectively for input impedance and output impedance
Two data files carry out objective optimization, obtain corresponding match circuit.
Referring to Fig. 4, a kind of structure diagram of the second embodiment of circuit design device provided by the invention.
The present invention provides a kind of second embodiment of circuit design device, including：
Load balance factor module 401, input impedance and output for chip or transistor to be obtained by load balance factor hinder
It is anti-to be respectively written into different data files.
Writing module 402, input impedance and output impedance for chip or transistor to be obtained by load balance factor are write
Enter data file.
Objective optimization module 403 is then right for setting corresponding optimization aim respectively for input impedance and output impedance
Two data files carry out objective optimization, obtain corresponding match circuit.
The above, the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to before
Embodiment is stated the present invention is described in detail, it will be understood by those of ordinary skill in the art that：It still can be to preceding
The technical solution recorded in each embodiment is stated to modify or carry out equivalent substitution to which part technical characteristic；And these
Modification is replaced, and the essence of appropriate technical solution is not made to depart from the spirit and scope of various embodiments of the present invention technical solution.
Claims (4)
1. a kind of circuit design method, which is characterized in that including：
Input impedance and output impedance that chip or transistor are obtained by load balance factor are respectively written into different data files；
Corresponding optimization aim is set respectively for the input impedance and the output impedance, then to two data files
Objective optimization is carried out, obtains corresponding match circuit.
2. circuit design method according to claim 1, which is characterized in that chip or transistor are being passed through into load balance factor
Before obtained input impedance and output impedance write-in data file, further include：
Load balance factor is carried out to the chip or the transistor and obtains the input impedance and the output impedance.
3. a kind of circuit design device, which is characterized in that including：
Writing module, input impedance and output impedance for chip or transistor to be obtained by load balance factor are respectively written into not
Same data file；
Objective optimization module, for setting corresponding optimization aim respectively for the input impedance and the output impedance, then
Objective optimization is carried out to two data files, obtains corresponding match circuit.
4. the circuit design device stated according to claim 3, which is characterized in that further include：
Load balance factor module obtains the input impedance and described for carrying out load balance factor to the chip or the transistor
Output impedance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711309324.3A CN108052733A (en) | 2017-12-11 | 2017-12-11 | A kind of circuit design method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711309324.3A CN108052733A (en) | 2017-12-11 | 2017-12-11 | A kind of circuit design method and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108052733A true CN108052733A (en) | 2018-05-18 |
Family
ID=62123816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711309324.3A Pending CN108052733A (en) | 2017-12-11 | 2017-12-11 | A kind of circuit design method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108052733A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102739167A (en) * | 2012-07-09 | 2012-10-17 | 中国科学院微电子研究所 | Design method for microwave amplifier |
| CN104617896A (en) * | 2015-02-28 | 2015-05-13 | 东南大学 | Broadband highly efficient continuous inverse class-F power amplifier and design method thereof |
| CN105631109A (en) * | 2015-12-24 | 2016-06-01 | 合肥师范学院 | Design method for radio frequency ultra-wide band high-efficiency power amplifier and circuit |
-
2017
- 2017-12-11 CN CN201711309324.3A patent/CN108052733A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102739167A (en) * | 2012-07-09 | 2012-10-17 | 中国科学院微电子研究所 | Design method for microwave amplifier |
| CN104617896A (en) * | 2015-02-28 | 2015-05-13 | 东南大学 | Broadband highly efficient continuous inverse class-F power amplifier and design method thereof |
| CN105631109A (en) * | 2015-12-24 | 2016-06-01 | 合肥师范学院 | Design method for radio frequency ultra-wide band high-efficiency power amplifier and circuit |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180518 |