CN110137089A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN110137089A
CN110137089A CN201910104546.4A CN201910104546A CN110137089A CN 110137089 A CN110137089 A CN 110137089A CN 201910104546 A CN201910104546 A CN 201910104546A CN 110137089 A CN110137089 A CN 110137089A
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CN
China
Prior art keywords
metal layer
main surface
semiconductor substrate
semiconductor
substrate
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Pending
Application number
CN201910104546.4A
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English (en)
Inventor
汉斯-马丁·里特
弗兰克·布尔迈斯特
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Yasuyo Co Ltd
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Yasuyo Co Ltd
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Application filed by Yasuyo Co Ltd filed Critical Yasuyo Co Ltd
Publication of CN110137089A publication Critical patent/CN110137089A/zh
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Abstract

本公开涉及半导体器件结构和制造半导体器件的方法。该方法包括：提供具有第一主表面和相对的第二主表面的第一半导体衬底，第一主表面上形成有第一金属层；提供具有第一主表面和相对的第二主表面的第二半导体衬底，其中第二半导体衬底包括形成在其中的多个有源器件区域和第二金属层，所述第二金属层形成在第一主表面上、连接多个有源器件区域中的每一个；将第一半导体衬底的第一金属层接合到第二半导体衬底的第二金属层；以及在第二半导体衬底的第二主表面上形成器件接触件，以用于电连接至多个有源器件区域中的每一个。

Description

半导体器件
技术领域
本公开涉及一种半导体器件结构和制造方法。具体地，本公开涉及一种包括供体衬底/基板(donor substrate)和接合载体衬底/承载基板(bonded carrier substrate)的半导体器件结构。
背景技术
芯片级半导体封装件(CSP)的特征在于是可直接表面安装的封装件。CSP布置成在封装件的一个表面上具有所有外部接触件/触点(contact)，从而使封装件能够安装在载体(例如印刷电路板)上。CSP通常包含垂直布置在封装件内的二极管和/或晶体管器件结构，使得器件结构内的主电流(dominant current flow)固有地是垂直的。然而，因为CSP被布置成在一个表面上具有接触件，所以电流必须流到同一侧上的另一个接触件，因此流过器件结构的有源区的垂直电流必须改变方向到横向，通过衬底，然后将方向改回垂直方向以达到第二接触件。由于体半导体材料的导电性有限，因此，体中的和器件结构和接触件中的电流密度将是不均匀的。器件结构中的更靠近第二接触件的各部分中的电流密度可以更高。另外，电流拥挤(current crowding)发生在各器件结构的各接触件的边缘处。因此，通过各器件结构和各接触件的最大允许总电流将小于以下情况：第二接触件放置在半导体晶体的另一个表面上；并且通过体的电流总是垂直的；以及因此对于器件结构的整个区域，各器件结构内的电流密度在原则上是相同的。
另外，寄生电流路径可能发生在各器件结构之间，这会影响性能。对于其中局部加热会导致器件故障的瞬态电压抑制装置，这些问题也是尤其相关的。
发明内容
根据一个实施例，提供一种制造半导体器件的方法，所述方法包括：提供具有第一主表面和相对的第二主表面的第一半导体衬底，所述第一主表面上形成有第一金属层；提供具有第一主表面和相对的第二主表面的第二半导体衬底，其中所述第二半导体衬底包括形成在其中的多个有源器件区域和第二金属层，所述第二金属层形成在第一主表面上、连接所述多个有源器件区域中的每一个；将第一半导体衬底的第一金属层接合到第二半导体衬底的第二金属层；以及在第二半导体衬底的第二主表面上形成器件接触件以用于电连接至多个有源器件区域中的每一个。
可选地，所述方法可以包括：将第一半导体衬底的第一金属层接合到第二半导体衬底的第二金属层，以形成设置在两个半导体层之间的金属层。可选地，第一金属层和第二金属层可以是金或铝。
可选地，所述方法还可以包括：在将第一金属层接合到第二金属层之前，使第二半导体衬底的相对的第二主表面变薄。
可选地，所述方法还可以包括：形成从第二半导体衬底的第一主表面延伸到相对的第二主表面的一个或多个沟槽区域。所述方法还可以包括：用绝缘材料填充沟槽区域。
可选地，第二半导体衬底可以是绝缘体上硅衬底。可选的，多个有源器件区域是双向有源器件区域。
根据一个实施例，还提供一种半导体器件，包括：第一半导体衬底，其具有第一主表面和相对的第二主表面，所述第一主表面上形成有第一金属层；以及第二半导体衬底，其具有第一主表面和相对的第二主表面，其中所述第二半导体衬底包括形成在其中的多个有源器件区域和第二金属层，所述第二金属层形成在第一主表面上、连接所述多个有源器件区域中的每一个；其中，第一半导体衬底的第一金属层接合到第二半导体衬底的第二金属层；以及器件接触件设置在第二半导体衬底的第二主表面上以用于电连接至多个有源器件区域中的每一个。
第一半导体衬底的第一金属层可以接合到第二半导体衬底的第二金属层，以形成设置在两个半导体层之间的金属层。
附图说明
因此，可以详细地理解本公开的特征的方式，参考各实施例进行更具体的描述，其中一些实施例在附图中示出。然而，应注意，附图仅示出了典型的实施例，因此不应视为对其范围的限制。附图用于促进对本公开的理解，因此不一定按比例绘制。通过结合附图阅读本说明书，本领域技术人员将清楚所要求保护的主题的优点，在附图中，相同的附图标记用于表示相同的元件，并且其中：
图1示出了载体衬底或晶片，其包括形成在其上的金属接触层。
图2示出了供体衬底或晶片，其包括连接到在其上形成的金属接触层的有源区；
图3a示出了根据实施例的示例的背对背二极管的有源区结构；
图3b示出了根据实施例的示例的开放式基极(open base)晶体管的有源区结构；
图4示出了在使晶片变薄之前接合到载体衬底的供体衬底；
图5示出了在使晶片变薄之后接合到载体衬底的供体衬底；
图6是根据实施例的由供体衬底和载体衬底形成的半导体器件；以及
图7示出了根据实施例的由供体衬底和载体衬底形成的半导体器件。
具体实施方式
参照图1至图6描述根据实施例的形成半导体器件的示例方法。该过程可以从图1所示的载体晶片或第一衬底100开始。可以在载体晶片或第一衬底100的第一主表面上形成第一金属导电层102。第一金属层102可以通过任何适当的工艺(例如蒸发或溅射)沉积在第一衬底100上。第一金属层102可以由例如铝、金、钛、钨、铂或其合金形成。第一衬底100可以是诸如硅衬底的半导体衬底，并且可以是掺杂衬底或未掺杂衬底。优选地，第一金属层102与第一衬底100形成欧姆接触。
如图2所示，提供供体晶片或第二衬底104。可以在第二衬底104中形成一个或多个有源半导体器件区域106。可以在第二衬底104的第一主表面上形成第二金属导电层108，并且可以将第二金属层108电连接到形成在第二衬底104中的一个或多个半导体器件区域106的接触区域。可以通过扩散和/或注入在第二衬底104中形成半导体器件区域106，并且参考下面的图3a和图3b讨论半导体器件区域结构的一些示例。
参考图3a，示出了背对背二极管结构。在该示例中，有源区106形成在轻掺杂的p-第二衬底104中。在该示例中，各有源区106的每个阴极由掩埋高掺杂的n型区域(BN)然后是深度高掺杂的n型(DN)区域形成，由此形成各二极管的阴极区域。阳极区域形成在高掺杂p+区域的衬底中，并且使用第二金属层108使阳极接触件形成到有源区106的高掺杂p+区域。
为此，背对背二极管结构是阳极-阳极连接结构，并且下面参考图6更详细地讨论阴极接触件的形成和布置。
图3b示出了示例有源结构106的另一示例。在这种情况下，有源结构106是形成在轻掺杂的p-第二衬底104中的所谓的开放式基极晶体管。在该示例中，有源区106由掩埋高掺杂的n型区域(BN)接着是p-阱基极区域进而接着是高掺杂的n+集电极区域形成，所述n型区域(BN)形成发射极区域。使用第二金属层108使集电极接触件形成至有源区106的高掺杂n+区域。由于开放式基极器件是双向型器件，因此发射极和集电极的作用将根据极性而变化，只有当极性反转时，(浮置)基极将仍是基极。
本公开的实施例不限于如图3a或图3b所示的器件结构，并且技术人员将清楚地看到，在不脱离本公开概念的情况下，可以布置和实现任何适当的器件结构、各结构的组合或多个结构。在所有实施例中，金属层108可以连接到多个器件结构。
在第一衬底100上形成第一金属层102和在第二衬底104和第二金属层108中形成有源区106之后，将第一衬底100和第二衬底104接合在一起。如图4所示，将第一金属层102接合到第二金属层108。
在这方面，从电学观点来看，接合的第一金属层102和第二金属108可以被认为是一个多层的层结构。以这种方式，接合到第二金属层108的第一金属层102可以被认为是掩埋金属层，即，掩埋在第一衬底100和第二衬底104之间。
接合技术的示例可包括热压接合。通过同时施加热和力，使第一金属层102和第二金属层108进入原子接触。来自第一金属层的晶格的各原子基于晶格振动而迁移到第二金属层的晶格，并且该原子相互作用导致第一金属层接合到第二金属层。可替换地，可以形成诸如共晶合金层的金属间接合层作为接合材料。接合层的其他替代方案可包括同时粘合-金属接合或同时熔融-金属接合。
如图5所示，在将第一衬底100和第二衬底104接合在一起之后，可以使与第二金属层108相对的主侧上的第二衬底104变薄，以暴露各有源区106的部分。例如，以下在图3a或图3b呈现的各示例之后，可以通过任何适当的蚀刻或研磨工艺来使第二衬底104变薄，以去除第二衬底104的一部分，暴露高掺杂的n+区域(BN)。去除第二衬底104的一部分允许适当地形成与各有源区106的暴露区域的接触件。
在图6中示出成品半导体器件120，其示出了在有源区106上形成适当的接触件110。在形成接触件110之前，可以在第二衬底104的与第二金属层108相对的一侧上形成可选的隔离层112。
在将第一衬底100接合到第二衬底104之前，在第二衬底104中形成有源区106。因此，在接合之前，对第二衬底104完成形成有源区106所需的所有高温扩散处理。结果，可以在接合处理中使用诸如金或铝的低熔点金属，因为接合金属不会向外扩散。此外，在形成掩埋金属层的第一金属层和第二金属层的接合之后，器件的高温处理(即，为了形成各种扩散区域)是困难的。这将需要具有高熔点的金属以承受形成各种扩散区域所需的温度，并且可能导致严重的机械问题，例如晶片弯曲或金属层的劣化。因此有利的是，在晶片接合之前进行所有高温处理，例如扩散处理。
此外，可以通过适当选择金属和/或金属厚度来控制接合的金属层102、108的电阻。
在与图5的替代工艺中，在将第一金属层102接合到第二金属层108之前，可以使在与第二金属层108相对的主侧上的第二衬底104变薄，以暴露各有源区106的部分。此外，取决于在第二衬底104中形成有源区106的厚度或深度，第二衬底104可以不需要变薄或局部变薄以暴露各有源区106，使得可以形成合适的接触件110。
可选地，在进一步处理成品器件120之前，可以使第一衬底100变薄。这可以包括使第一衬底100部分地变薄以减小其厚度和/或局部变薄，以便于从这种器件的阵列中分割该器件。
图7示出了根据一个实施例的半导体器件120。供体晶片或第二衬底104可以包括至少一个沟槽116，所述至少一个沟槽116从第二衬底104的第一主表面延伸到相对的第二主表面并且位于有源区106之间。可以用电绝缘材料(例如氧化物)填充至少一个沟槽116，所述沟槽116用于隔离各有源区106，以防止寄生电流在各有源区之间流过第二衬底104。
可以在第二衬底104中形成所述至少一个沟槽116，同时形成有源区106。如图所示，沟槽116也可以布置在器件120的边缘处，以防止来自器件120的边缘的寄生电流(例如漏电流)。在第二器件结构不是有源结构但是与体半导体材料简单接触的情况下，可以通过导电沟槽将接触件连接到掩埋金属层，来减小该接触件与掩埋金属层之间的电阻。这可以具有降低器件的导通电阻的效果。
在操作方面并参考图6，其体现图3a的背靠背二极管布置或图3b的开放式基极晶体管布置，电流可以从一个接触件110流过各有源区106中的一个并进入由第一金属层102和第二金属层108形成的多层金属层。然后电流通过多层金属和另一个有源区106，直到另一个接触件110。
由于多层金属结构由第一金属层102和第二金属层108形成，因此垂直于表面的电流分布基本上是均匀的。换句话说，在器件结构的整个区域上每个区域的电流密度基本相同。与薄层电阻为200-1000mOhm的体半导体的电流路径相比，多层金属结构的电阻非常小，其薄层电阻为1-20mΩ。结果，与已知的布置不同，器件的内边缘和外边缘处的电流密度将基本上是均匀的。
此外，由于相同的原因，差分导通电阻非常小。掩埋金属层有效地缩短了通常是电流路径的一部分的体积(bulk)。因此，根据实施例的器件的导通电阻减小了180-990mOhm。另外，因为电流路径的硅部分(即垂直路径)很小，所以电流将仅在垂直方向上从顶部接触件传输到掩埋金属层，因为该路径的硅电阻很小。
此外，多层金属结构114的引入提供了在操作期间从器件120的有源区106的改善的散热。具体地，在器件120的操作期间产生的热量将通过多层金属结构传导离开有源区106，从而增加器件120的电流稳健性。
在上述实施例的替代方案中，供体晶片或第二衬底104可以是SOI(绝缘体上硅)晶片。在SOI晶片中形成有源区106并且在第一主表面上形成第二金属导电层108之后，如上参照图4所述，可以将SOI晶片接合到第一衬底100。SOI晶片的氧化物层可以用作可选的隔离层112，其具有通过其形成的适当的接触件110，以与有源区106接触，以如上面参考图6所讨论的。
如果SOI晶片的氧化物层是掩埋氧化物，则可以使与第二金属层108相对的主表面上的SOI晶片变薄以暴露掩埋氧化物。如上所述，掩埋氧化物可以用作可选的隔离层112，并且可以通过其形成适当的接触件，以连接到有源区106。如关于图7所讨论的，沟槽116也可以形成在SOI晶片中。
如上面关于图3a和3b所提到的，技术人员将理解，有源层的布置不限于背对背二极管或开放式基极晶体管的示例。基于上述教导，技术人员将理解，掩埋金属层的概念适用于不同类型的半导体器件结构。例如，诸如垂直MOS二极管、沟槽MOS晶体管、绝缘栅双极晶体管(IGBT)和/或垂直双极晶体管的器件或器件的任何组合可以被布置为有源区106。
上述实施例特别适合用于瞬态电压抑制(TVS)的半导体器件，当瞬态电压超过器件的雪崩击穿电位时，可能需要在操作期间分流过电流。TVS器件通常抑制比器件的击穿电压高的所有瞬态电压，并且因为这些瞬态电压在器件中产生热量，所以由第一金属层102和第二金属层108形成的掩埋金属层改善了器件的散热能力，同时还降低了器件的导通电阻。由于包含额外的热传导路径和电流导电路径，该器件得到改进。
在所附独立权利要求中阐述了本发明的特定方面和优选方面。来自从属权利要求和/或独立权利要求的特征的组合可以适当地组合，而不仅仅如权利要求中所述。
本公开的范围包括明确地或隐含地公开的任何新颖的特征或特征组合或其任何概括，而不管其是否涉及要求保护的发明或者减轻本发明所解决的任何问题或所有问题。申请人在此发出通知，在本申请或由此衍生的任何此类进一步申请的审查期间，可以对这些特征提出新的权利要求。具体地，参考所附权利要求，从属权利要求的特征可以与独立权利要求的特征组合，并且来自各个独立权利要求的特征可以以任何适当的方式组合，而不仅仅是在权利要求中列举的特定组合。
在单独的实施例的上下文中描述的特征也可以在单个实施例中组合地提供。相反，为简洁起见，在单个实施例的上下文中描述的各种特征也可以单独提供或以任何合适的子组合提供。
术语“包括”不排除其他元件或步骤，术语“一个(a或an)”不排除多个。权利要求中的附图标记不应被解释为限制权利要求的范围。

Claims (15)

1.一种制造半导体器件的方法，所述方法包括：
提供具有第一主表面和相对的第二主表面的第一半导体衬底，所述第一主表面上形成有第一金属层；
提供具有第一主表面和相对的第二主表面的第二半导体衬底，其中所述第二半导体衬底包括形成在其中的多个有源器件区域和第二金属层，所述第二金属层形成在第一主表面上、连接所述多个有源器件区域中的每一个；
将所述第一半导体衬底的所述第一金属层接合到所述第二半导体衬底的所述第二金属层；以及
在所述第二半导体衬底的第二主表面上形成器件接触件以用于电连接至所述多个有源器件区域中的每一个。
2.根据权利要求1所述的方法，包括将所述第一半导体衬底的所述第一金属层接合到所述第二半导体衬底的所述第二金属层，以形成设置在两个半导体层之间的金属层。
3.根据权利要求1或2所述的方法，包括使用金接合层或铝接合层将所述第一半导体衬底的所述第一金属层接合到所述第二半导体衬底的所述第二金属层。
4.根据权利要求1至3中任一项所述的方法，包括在将所述第一金属层接合到所述第二金属层之前，使所述第二半导体衬底的相对的第二主表面变薄。
5.根据权利要求1至4中任一项所述的方法，包括形成从所述第二半导体衬底的所述第一主表面延伸到相对的第二主表面的一个或多个沟槽区域。
6.根据权利要求5所述的方法，还包括用绝缘材料填充所述沟槽区域。
7.根据权利要求1至6中任一项所述的方法，其中，所述第二半导体衬底是绝缘体上硅衬底。
8.根据权利要求1至7中任一项所述的方法，其中，所述多个有源器件区域是双向有源器件区域。
9.一种半导体器件，包括：
第一半导体衬底，其具有第一主表面和相对的第二主表面，所述第一主表面上形成有第一金属层；以及
第二半导体衬底，其具有第一主表面和相对的第二主表面，其中所述第二半导体衬底包括形成在其中的多个有源器件区域和第二金属层，所述第二金属层形成在第一主表面上、连接所述多个有源器件区域中的每一个；
其中，所述第一半导体衬底的所述第一金属层接合到所述第二半导体衬底的所述第二金属层；器件接触件设置在所述第二半导体衬底的第二主表面上以用于电连接至所述多个有源器件区域中的每一个。
10.根据权利要求9所述的半导体器件，其中，所述第一半导体衬底的所述第一金属层接合到所述第二半导体衬底的所述第二金属层，以形成设置在两个半导体层之间的金属层。
11.根据权利要求8或9所述的半导体器件，其中，所述第一金属层和所述第二金属层是金或铝。
12.根据权利要求8至10中任一项所述的半导体器件，还包括从所述第二半导体衬底的第一主表面延伸到相对的第二主表面的一个或多个沟槽区域。
13.根据权利要求11所述的半导体器件，其中，所述沟槽区域填充有绝缘材料。
14.根据权利要求8至12中任一项所述的半导体器件，其中，所述第二半导体衬底是绝缘体上硅衬底。
15.根据权利要求8至13中任一项所述的半导体器件，其中，所述有源器件区域是双向有源器件区域。
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