CN110120791A - 一种抗总剂量的cmos运算放大器 - Google Patents

一种抗总剂量的cmos运算放大器 Download PDF

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CN110120791A
CN110120791A CN201910396605.XA CN201910396605A CN110120791A CN 110120791 A CN110120791 A CN 110120791A CN 201910396605 A CN201910396605 A CN 201910396605A CN 110120791 A CN110120791 A CN 110120791A
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total dose
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廖永波
范天龙
李平
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University of Electronic Science and Technology of China
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
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    • H—ELECTRICITY
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    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
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    • H03F2203/45134—Indexing scheme relating to differential amplifiers the whole differential amplifier together with other coupled stages being fully differential realised

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Abstract

本发明属于集成电路领域，尤其涉及抗辐照集成电路技术研究领域。随着空间技术以及核工程技术的快速发展，越来越多的CMOS运算放大电路不可避免地应用于辐射环境中并受到各种辐射效应的影响，为了保证CMOS运放的可靠性和性能，抗辐照加固技术的研究始终面临着严峻的挑战。本发明以一种抗总剂量CMOS器件为基础，设计出一种抗总剂量CMOS运算放大电路，在运放的每条支路接地NMOS晶体管使用提出的抗总剂量器件，保证每条支路的总漏电流最小。对运放的尾电流源使用抗总剂量NMOS器件，保证运放的带宽和增益在总剂量辐照前后变化最小。这样得到的抗总剂量CMOS运算放大电路抗辐照能力相比传统的非抗总剂量CMOS运放明显提高。

Description

一种抗总剂量的CMOS运算放大器
技术领域
本发明属于集成电路领域，尤其涉及抗辐照集成电路技术研究领域。
背景技术
随着空间技术以及核工程技术的快速发展，越来越多的CMOS运算放大电路不可避免地应用于辐射环境中并受到各种辐射效应的影响，为了保证CMOS运放的可靠性和性能，抗辐照加固技术的研究始终面临着严峻的挑战。集成电路在辐射环境中受到的辐照机理有多种形式，主要的辐照效应包括如下:总剂量电离辐射效应、中子辐射效应、瞬时辐射效应、单粒子效应、剂量增强效应、低计量率效应，其中单粒子效应是具有一定能量的单个重离子或质子射入半导体器件或集成电路，致使半导体器件或集成电路性能退化或功能失效的现象的统称，单粒子效应又可以细分为:单粒子翻转、单粒子瞬变、单粒子功能中断、单粒子扰动、单粒子门锁、单粒子介质击穿和单粒子栅穿等。本文主要对总剂量电离辐射效应(TotalIonizing Dose,TID)开展研究，总剂量效应是集成电路和微电子器件性能退化甚至失效的主要原因之一，是导致集成电路和微电子器件性能退化和失效的一种长期机制，其主要作用于集成电路的氧化层。主要是当集成电路和微电子器件暴露于空间或核辐射等环境中时，γ射线、X射线或带电粒子对集成电路和微电子器件进行轰击，在芯片内部沉积能量，使材料原子电离产生电子-空穴对，之后产生的电子-空穴对在氧化层内部经历复合、输运、被俘获等过程，最终形成氧化层固定电荷和界面陷阱电荷，进而影响集成电路和微电子器件的电学特性。NMOS器件和PMOS器件是CMOS集成电路的两种基本单元，总剂量辐照下，这两种晶体管类型的电学特性退化并不相同。对于NMOS器件来说，总剂量效应使其电学特性参数发生退化，主要体现在使NMOS器件阈值电压发生负向漂移、泄漏电流增大、跨导退化、载流子迁移率下降、1/f噪声增大等，并且随着辐照剂量的增加，NMOS器件的电学特性退化越严重；而对于PMOS器件而言，阈值电压负向漂移意味着其阈值电压的绝对值增加，使得PMOS器件泄漏电流反而减小，因此NMOS器件对总剂量辐射效应更加敏感。这些参数的退化导致集成电路和微电子器件短期或永久性的损伤，最终造成集成电路功能失效。
从版图设计角度进行抗总剂量加固，人们常常是通过改变栅结构来避免NMOS晶体管氧侧向漏电的问题。改变栅结构形成的NMOS管主要有:H形栅结构、全环栅结构、半环栅结构。但是这些变形栅结构存在的一个共同问题就是集成度不高，无法适用于超大规模集成电路。所以有必要研究一种新的晶体管结构，可以改变上述的不足，使晶体管兼容主流的CMOS工艺，可以使用商用工艺线进行生产，适合大规模集成，适用于超大规模集成电路。总剂量辐射效应除了使NMOS器件的阈值电压发生负向漂移外，还会使器件的泄漏电流随着累积辐射剂量的增加而增大，是引起NMOS器件和集成电路失效的另外一个重要机制，并且集成电路的集成度越高，总剂量辐射引起的泄漏电流问题也就越明显，对集成电路的功耗影响更加严峻。其场氧化层会引起泄漏电流的增加，场氧化层引起的泄漏电流又可以分成器件内部的泄漏电流和器件之间的泄漏电路。器件内部的泄漏电流是指由于场氧化层侧向漏电，从而在NMOS晶体管的源漏之间存在电压差时产生的泄漏电流；而器件之间的泄漏电流主要来自相邻晶体管不同偏压的源/漏端之间或者来自存在电压差的相邻N阱之间，是由于场氧化层底部漏电产生的。研究表明由于场氧化层底部的电场强度要比顶部小三个数量级，从而造成对应区域的空穴产额差别很大，使得器件之间的泄漏电流要远小于器件内部的泄漏电流。NMOS器件内部的场氧化层侧向漏电示意图附图1所示[1]，其中(a)为NMOS器件的版图，箭头所示的是NMOS器件源漏之间存在的漏电通道，该漏电通道靠近场氧化层侧表面；图(b)是图(a)沿AB虚线切开的剖面图，从图可知，由于总剂量效应的影响，在靠近硅衬底的场氧化层表面产生了正的氧化层陷阱电荷，并且这些陷阱电荷使得硅衬底表面感生出电子从而形成源漏之间的漏电通道。
基于上述的设计加固理念，运用提出一种抗总剂量加固的基本NMOS器件结构[1]，如附图2所示，为了方便介绍，本文暂时将该结构称为I型NMOS晶体管。在I型NMOS晶体管结构中，源漏两端的P+掺杂区都是低电位，即两边不存在电压差，所以不会有泄漏电流的产生；另一方面由于P+掺杂区的存在，使得场氧化层侧面与沟道区边缘之间不存在寄生的NMOS晶体管，晶体管从漏端经过场氧侧面到达源端的漏电通道被P+掺杂区所阻隔，从而大幅度地减小了泄漏电流，并且由于P+掺杂区的掺杂浓度远高于衬底浓度，P+掺杂区将会向沟道区进行横向扩散，使得沟道区中靠近源漏区的两侧有效掺杂浓度提高，沟道更不容易发生反型导通，从而进一步减小了泄漏电流的产生。
参考文献
[1]李平，陈孔滨.一种抗总剂量CMOS电路基本晶体管结构[P].中国，发明专利201710017901.5,2017年02月07日
发明内容
本设计专利以一种抗总剂量CMOS器件为基础，提出一种抗总剂量CMOS运算放大电路，主要就其抗总剂量辐照能力以及其结构特性对抗总剂量能力的影响进行研究，并将其与传统的非抗总剂量CMOS运放进行比对。从对比结果中可以看出抗总剂量CMOS运放的实用性。
基于总剂量的设计加固理念，使用一种抗总剂量MOS结构，该结构通过在普通NMOS晶体管的源漏区外围形成P+掺杂区从而使得晶体管获得抗总剂量辐照的能力。
使用抗总剂量MOS管设计的CMOS运放在有较强的辐射环境下依然可以有着稳定的性能。对比传统运放在强辐射环境下的性能差异，抗总剂量MOS管设计的CMOS运放抗辐照效果提升明显，从而可以直观地衡量所提出的抗总剂量CMOS运算放大器在实际工程应用中的价值。
附图说明
附图1为NMOS器件场氧化层侧向漏电示意图。(a)版图；(b)沿AB线剖面图
附图2为I型NMOS晶体管结构示意图
附图3为不使用抗总剂量MOS器件加固的运放电路设计图
附图4为普通条栅晶体管受辐照前后仿真模型
附图5为加固尾电流NMOS器件的运放电路设计图
附图6为使用抗总剂量MOS器件加固的运放电路设计图
附图7为抗总剂量MOS器件加固的运放增益和带宽特性曲线
附图8为加固尾电流NMOS运放增益和带宽特性曲线
附图9为普通条栅MOS运放增益和带宽特性曲线
附图10为使用抗总剂量MOS器件加固运放输出电压噪声特性曲线
附图11为加固尾电流NMOS运放输出电压噪声特性曲线
附图12为普通条栅MOS运放输出电压噪声特性曲线
具体实施方式
基于抗总剂量NMOS器件，设计出抗总剂量运算放大器，并将抗总剂量运算放大器与普通的运算放大器的性能进行比对。通过在运放的每条支路接地NMOS晶体管使用提出的抗总剂量器件，保证每条支路的总漏电流最小。对运放的尾电流源使用抗总剂量NMOS器件，保证运放的带宽和增益在总剂量辐照前后变化最小。附图3给出了运算放大器的实际电路图，如图一所示，电路分为三个部分：1)提供静态工作点的偏置电路。2)电流镜做负载的差分输入级。3)带密勒补偿的共源功率输出级。本文的电路设计基于cadence仿真软件和tsmc0.18um工艺平台。基于普通条栅NMOS管受到辐射后场氧化层有漏电流的原理，做出了受辐照后的仿真模型。如图4所示。NMOS漏源等效小信号电阻R＝Ron//Req//[1/(jωCeq)]。其中Ron为NMOS本征小信号电阻。ω为信号频率，Req和Ceq分别为受辐照后源漏两端漏电等效电阻和等效电容的值。
由运放原理可知，提供尾电流的NMOS管(图3中的M5)中电流变化对运放的性能起着决定性作用，当该管的电流变大时，比如普通条栅晶体管受辐照产生漏电流导致的电流增大，运放的增益会显著降低。又由于漏源间的场氧化层的导通之后的结电容的存在，运放的带宽也会减小。
下面我们给出上面所说的加抗总剂量NMOS晶体管的运放和普通条栅晶体管运放的仿真结果，图5和图6分别是普通条栅晶体管和使用抗总剂量MOS器件加固的运放电路。图7是为抗总剂量MOS器件加固的运放增益和带宽特性仿真结果，从图中可知，运放的平带增益为68dB,带宽为210KHz。附图8为加固尾电流NMOS运放增益和带宽特性曲线仿真结果，从图中可知，运放的平带增益为65dB,带宽为190KHz，附图9是使用普通NMOS晶体管设计的运放的仿真结果，从图中可知，运放的平带增益为31dB,带宽为8KHz。通过对比可知，用抗总剂量NMOS器件加固设计的运放在辐照环境下，可以表现出更高的增益和更稳定的带宽性能。而普通条栅晶体管在辐照条件下，漏源间的场氧化层间存在这较大的源漏电流，使得增益和带宽都显著下降。此外，附图7和附图8的结果表明，只加固尾电流NMOS与底部NMOS全加固的效果几乎一样，这正验证了尾电流管电流对整个运放性能起关键作用，也对加固设计电路也有很大的参考意义。增益和带宽的性能之外，噪声性能在受辐照后也会由于场氧化层漏电变差，图10是抗总剂量MOS管运放的输出电压噪声曲线，图11和图12是普通条栅晶体管运放的输出电压噪声曲线。通过对比可知，普通条栅晶体管运放受辐照后噪声特性退化明显，而抗总剂量MOS的噪声特性在受辐照后基本不受影响。
除增益和带宽的性能之外，噪声性能在受辐照后也会由于场氧化层漏电变差，图10是为使用抗总剂量MOS器件加固运放输出电压噪声特性曲线，图11和图12是为加固尾电流NMOS运放输出电压噪声特性曲线和普通条栅MOS运放输出电压噪声特性曲线。通过对比可知，普通条栅晶体管运放受辐照后噪声特性退化明显，而抗总剂量MOS器件加固运和加固尾电流NMOS运放的噪声特性在受辐照后基本不受影响。

Claims (2)

1.一种抗总剂量CMOS运算放大器，其特征在于：对运放的每条支路接地NMOS晶体管使用提出的抗总剂量器件，保证每条支路的总漏电流最小；电路的具体结构和连接方式如下：在偏置电路中，R1一端接VDD，另一端与M9管的源端连接，M9管的栅极与二极管连接方式的M8管的栅极连接，M8管的源极与VDD连接，M8、M9的宽长比的比值以及R1的阻值决定了偏置电流的大小；M10的栅极与二极管连接方式的M11的栅极连接，M13的栅极与二极管连接方式的M12的栅极连接，M12管和M13管的漏极分别与M11管和M10管的源极连接，M12管和M13管的源极与GND相连接；在输入级电路，M1管和M2管组成差分输入，差分输入对管的漏极连接着电流镜负载管M3管和M4管的漏极，M3管和M4管的源极连接着VDD，M3管和M4管将双端输入转化为单端输出，差分输入对管的源极连接着尾电流源管M5管的漏极，M5源极与GND相连接，M5管栅极于偏置电路连接为差分输入对管提供偏置；在共源输出级电路中，放大管M6的漏极连接着有源负载管M7管，M7管为放大管M6提供静态工作电流和负载；运放抗总剂量加固：在偏置电路中的M12管和M13管、输入级的尾电流源M5管，输出级负载M7管用进行抗总剂量加固。
2.如权利要求1所述的抗总剂量CMOS运算放大器，其特征在于：在要求1所用到的运算放大器基础上，在单独对运放的尾电流源使用抗总剂量NMOS器件，与要求1中的加固方式的运放进行仿真对比带宽和增益在总剂量辐照前后变化；电路结构与要求1中相同，运放尾电流管抗总剂量加固：只对输入级的尾电流源M5管用进行部分抗总剂量加固。
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