CN106783853A - 一种抗总剂量cmos电路基本晶体管结构 - Google Patents
一种抗总剂量cmos电路基本晶体管结构 Download PDFInfo
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Abstract
本发明提出一种抗总剂量CMOS电路基本晶体管结构,属于抗辐照半导体技术领域。本发明适用于各种CMOS电路结构,能够提高CMOS电路的抗总剂量辐射能力,能够适用于超大规模集成电路。其特征在于,在传统NMOS晶体管N+源漏区的外围通过离子注入形成P+掺杂区,即对NMOS晶体管的源漏区进行N+和P+掺杂。本发明的优势在于,与传统半导体工艺完全兼容,无需增加额外的掩膜和工艺步骤,即可提高CMOS电路的抗总剂量辐射能力,而且适合于大规模集成。
Description
技术领域
本发明涉及集成电路,特别涉及半导体器件。
背景技术
CMOS电路基本晶体管结构在当今信息社会中扮演着极其重要的作用,是所有CMOS电路的基础。当CMOS电路应用于辐射环境中,特别是应用于航空航天领域中,由于长期处于辐射环境中,其绝缘层中会不断积累氧化层固定电荷和界面态陷阱电荷,从而导致半导体器件性能退化,这种现象就称为电离辐射总剂量(Total Ionizing Dose,TID)效应。总剂量效应会引起NMOS晶体管的阈值电压漂移、泄漏电流增加等问题。随着半导体制造工艺的不断进步,栅氧化层越来越薄,使得总剂量效应对栅氧化层的影响变得越来越小,甚至可以忽略不计;但是在NMOS晶体管沟道区边缘,作为器件之间隔离使用的场氧化层与NMOS晶体管之间会形成寄生晶体管,并且场氧化层比较厚且比较宽,受总剂量效应的影响比较大;会使场氧化层与NMOS晶体管沟道区之间的寄生晶体管阈值电压逐步减小;即会在场氧化层与NMOS晶体管沟道区边缘之间形成漏电通道,产生场氧化层侧向漏电,使得晶体管泄漏电流增加,导致整个CMOS电路的功耗增加,可能引起CMOS电路工作异常甚至发生失效。而传统的抗总剂量加固措施中使用的H形栅结构、环形栅结构和半环形栅结构虽然可以提高半导体器件的抗总剂量能力,但是它们运用于电路中时存在集成度不高,不适用于超大规模集成电路的缺点。
发明内容
本发明所要解决的技术问题是,提供一种抗总剂量CMOS电路基本晶体管结构,该晶体管结构与传统半导体工艺完全兼容,无需增加额外的掩膜和工艺步骤,即可提高CMOS电路的抗电离辐射能力,而且适用于大规模集成。
本发明解决所述技术问题采用的技术方案是:
在传统NMOS晶体管的N+源漏区外围通过离子注入形成P+掺杂区,或只在传统NMOS晶体管的N+源区外围通过离子注入形成P+掺杂区。形成的P+掺杂区可以通过接触孔连接至低电位,也可以不对P+掺杂区进行连接从而降低晶体管的面积。
本发明的优势在于,制造工艺与传统半导体工艺完全兼容,无需增加额外的掩膜和工艺步骤,即可提高CMOS电路的抗电离辐射能力,能够进行大规模集成,能够直接替换现有CMOS集成电路中的NMOS晶体管,从而实现抗总剂量辐射的能力。
附图说明
图1是本发明的示意图
图2是寄生漏电沟道示意图
图3为图1的一种变形结构
图4为图3的一种变形结构
图5为图1的另一种变形结构
图6为图5的一种变形结构
图7为图6的一种变形结构
图8为图1的第三种变形结构
图9为图3的一种变形结构
图10为图4的一种变形结构
图11为使用本发明结构的基本与非门下拉网络
图12为使用本发明结构的基本或非门下拉网络
图13为使用本发明结构的电流镜
具体实施方式
以下结合附图对本发明的具体实施方式作进一步的说明:
本发明提出了一种抗总剂量CMOS电路基本晶体管结构,如图1所示。从图中可以看出,本发明是在传统NMOS晶体管结构的基础上,在其N+源漏区外围通过离子注入的方式形成P+掺杂区。该P+掺杂区连接至低电位。该晶体管的基本工作原理与传统NMOS晶体管工作原理一样,形成的P+掺杂区不参与开关工作。形成的P+掺杂区的意义在于,在现有先进的半导体制造工艺中,MOS晶体管的栅氧化层厚度已经可以做得非常薄,受总剂量效应的影响非常小,而场氧化层作为器件间隔离的作用,其厚度和宽度都比较大,又由于MOS晶体管的阈值电压漂移值与氧化层厚度的平方成正比,所以在辐照环境中,场氧化层与普通MOS晶体管沟道区边缘之间形成的寄生MOS管阈值电压漂移值就比较大,特别是对NMOS晶体管,在长期的辐照环境中,就会导致寄生NMOS管阈值电压变得很低,导致漏电通道的形成,如图2所示,从而引起CMOS电路泄漏电流增大、功耗增加,甚至导致CMOS电路功能异常或失效。而采用本发明提出的晶体管结构,在NMOS管的N+源漏区的外围形成P+掺杂区,则可以抑制如图2所示的NMOS晶体管沟道区边缘漏电通道的形成,最终有效提高NMOS晶体管抗总剂量的能力。
图3是图1的一种变形,如图所示,图1将P+掺杂区通过接触孔引出来连接到低电平,但是由于接触孔通常比较大,从而使得P+掺杂区也必须做得比较大;而图3则不使用接触孔对P+掺杂区进行连接,从而可以使P+掺杂区的面积更小,达到减小晶体管面积的目的。
图4是图3的一种变形结构,如图所示,其只在NMOS晶体管源漏区靠近沟道边缘处进行离子注入形成最小面积的P+掺杂区,并且由于该P+掺杂区会进一步向沟道区横向扩散,从而可以提高P+掺杂区附近漏电通道的阈值电压,可以有效提高NMOS晶体管抗总剂量的能力。并且这种变形结构相比图3所示的结构更加节省晶体管的面积。
图5是图1的另一种变形结构,如图所示,其只在NMOS晶体管的源区外围通过离子注入形成P+掺杂区,这种结构也可以抑制如图2所示的漏电通道的形成,这种变形结构的好处是不在漏区形成P+掺杂区,从而避免在漏区形成P+N+结构的PN结,可以提高漏区的击穿电压,降低漏区隧道击穿的风险。
图6为图5的一种变形结构,如图所示,相比图5,图6中的P+掺杂区不通过接触孔进行连接,从而可以使P+掺杂区的面积更小,达到减小晶体管面积的目的。
图7为图6的一种变形结构,如图所示,其只在NMOS晶体管源区靠近沟道边缘处进行离子注入形成最小面积的P+掺杂区,并且由于该P+掺杂区也会进一步向沟道区横向扩散,从而提高P+掺杂区附近漏电通道的阈值电压,有效提高NMOS晶体管抗总剂量的能力。并且这种变形结构相比图6所示的结构更加节省晶体管的面积。
图8为图1的第三种变形结构,如图所示,其在P+掺杂区和N+掺杂区之间形成一个过渡带,过渡带的掺杂类型可以为低掺杂N型或低掺杂P型,也可以为不掺杂的绝缘型。这种结构相比如图1所示的结构,可以避免P+N+结的形成,可以避免在N+区电压较高时产生P+N+结隧道击穿的风险。根据相同原理,可以得到图3的变形结构为图9;图4的变形结构为图10。
集成电路在完成电路网表设计后,需要进行相应的版图设计。而在现代集成电路设计中,为了节省芯片面积,提高电路的集成度和匹配度,在版图结构上会对晶体管采用源/漏共用的形式进行版图设计,此时本发明的结构就可以像普通MOS管一样进行源/漏共用提高电路集成度和匹配度,节省芯片面积。
如图11、图12、图13分别为基本与非门NMOS下拉网络、基本或非门NMOS下拉网络、模拟电路电流镜结构使用本发明结构的示意图,采用晶体管源/漏共用的形式,其相比普通MOS结构只有一点面积的牺牲,但是相比其他的抗总剂量版图加固措施而言则极大的提高了集成度,节省了芯片面积。
Claims (4)
1.一种抗总剂量CMOS电路基本晶体管结构,其特征在于,在传统NMOS晶体管的N+源漏区外围通过离子注入形成P+掺杂区。
2.如权利要求1所述的一种抗总剂量CMOS电路基本晶体管结构,其特征在于,可以只在传统NMOS晶体管的N+源区外围通过离子注入形成P+掺杂区。
3.如权利要求1所述的一种抗总剂量CMOS电路基本晶体管结构,其特征在于,形成的P+掺杂区可以通过接触孔连接至低电位,也可以不打接触孔从而进一步降低晶体管面积。
4.如权利要求1所述的一种抗总剂量CMOS电路基本晶体管结构,其特征在于,形成的P+掺杂区与N+掺杂区之间可以额外形成过渡带,从而减小P+N+结之间隧道击穿风险。
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CN108598168A (zh) * | 2018-05-03 | 2018-09-28 | 深圳吉华微特电子有限公司 | 抗总剂量辐射的功率场效应晶体管及其制造方法 |
CN110120791A (zh) * | 2019-05-14 | 2019-08-13 | 电子科技大学 | 一种抗总剂量的cmos运算放大器 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN108598168A (zh) * | 2018-05-03 | 2018-09-28 | 深圳吉华微特电子有限公司 | 抗总剂量辐射的功率场效应晶体管及其制造方法 |
CN110120791A (zh) * | 2019-05-14 | 2019-08-13 | 电子科技大学 | 一种抗总剂量的cmos运算放大器 |
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