CN110006580B - 集成电路芯片的堆叠和电子器件 - Google Patents
集成电路芯片的堆叠和电子器件 Download PDFInfo
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- CN110006580B CN110006580B CN201910130969.3A CN201910130969A CN110006580B CN 110006580 B CN110006580 B CN 110006580B CN 201910130969 A CN201910130969 A CN 201910130969A CN 110006580 B CN110006580 B CN 110006580B
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Abstract
本公开涉及集成电路芯片的堆叠和电子器件,该堆叠由第一集成电路芯片和第二集成电路芯片形成。该芯片具有通过中介间隔物彼此分离的相对面。间隔物通过粘接至相对面中的仅一个面而被固定。相对面通过与间隔物分离的局部粘接剂彼此固定。
Description
本申请是于申请日2015年04月02日提交的、申请号为201510154913.3、发明名称为“集成电路芯片的堆叠和电子器件”的分案申请。
优先权要求
本申请要求于2014年6月12日提交的第1455350号法国专利申请的优先权,其公开内容通过引用并入于此。
技术领域
本发明涉及微电子领域。
背景技术
为了使经堆叠的集成电路芯片彼此固定,公知的是在那些集成电路芯片之间的空间中提供粘接剂层或粘接剂区域,以便形成刚性的固定。
发明内容
提供了一种堆叠,其包括:第一和第二集成电路芯片,具有彼此相距一定距离定位的相对面;间隔物,在第二芯片的所述面的外围区域的至少一部分之上介于第二芯片的所述面的外围区域和第一芯片的所述面之间,并且通过粘接至这些面中的仅一个面而被固定;以及局部粘接剂固定装置,介于第二芯片的所述面的中心区域和第一芯片的所述面之间,以便将所述芯片彼此固定。
所述固定装置和所述间隔物可以彼此相距一定距离。
所述间隔物可以形成至少一个出口。
所述间隔物可以包括间隔环。
所述间隔环可以包括形成出口的至少一个槽。
所述间隔物可以包括开口的间隔环。
所述间隔物可以包括彼此分离的多个柱,每个柱能够通过粘接至所述面中的仅一个面而被固定。
所述固定装置可以包括至少一滴粘接剂。
所述第二芯片可以包括压力传感器。
也提供了电子器件,该电子器件包括堆叠,并且该电子器件包括具有至少一个贯通开口的包封封装体。
所述包封封装体可以部分地填充有胶体(gel)。
附图说明
现在将借助由附图图示的非限制性示例来描述根据本发明的堆叠,其中:
图1代表在封装体中的堆叠的截面;
图2代表封装体为截面时堆叠的平面图;以及
图3代表另一堆叠的平面图。
具体实施方式
如图1和2中图示,堆叠1包括第一集成电路芯片2和第二集成电路芯片3,第一集成电路芯片2和第二集成电路芯片3具有彼此相距一定距离定位并彼此平行的相对面4和5,从而在它们之间存在空间6。
芯片2的面4比芯片3的面5大,并且与面5完全相对地延伸。
堆叠1包括间隔物7,其介于第二芯片3的面5的外围区域和第一芯片2的面4之间。
根据该示例,间隔物7包括间隔环8,间隔环8仅通过粘接剂层9被固定在第一芯片的面4上,并且不固定在第二芯片3的面5上。间隔环8可以由玻璃纤维和树脂的衬底而形成。
堆叠1还包括局部粘接剂固定装置10,介于第二芯片3的面5的中心区域和第一芯片2的面4之间,以便将所述芯片彼此固定。该局部粘接剂固定装置10可以包括与间隔环8分离的成滴的固化粘接剂11,例如粘附到第一芯片2的面4和第二芯片3的面5的具有相对低的杨氏模量的成滴的环氧粘接剂。
为了制造堆叠1,间隔环8被固定在第一芯片2的面4上,成滴的液态粘接剂11被设置在间隔环8内并与间隔环8相距一定距离,随后第二芯片3被放置在间隔环8上方以便压缩成滴的粘接剂11。
在成滴的粘接剂11固化之后,芯片2和3仅通过该成滴的粘接剂11被局部地彼此固定,并且它们由间隔环8的存在而被防止相对于彼此倾斜。
此外,局部的成滴的固定粘接剂11在芯片2和3之间引入很少机械应力形式的应力,并且在芯片2和3由于温度变化的膨胀或收缩的情况下,芯片2可以在固定到芯片2的间隔环8上滑动。
根据一个备选的实施例,间隔环8可以在其面对着芯片3的面中具有至少一个槽12。根据另一备选的实施例,该槽12可以是贯通槽,间隔环8此时是开口的。槽12形成用于由芯片2和3以及间隔环8限定的空间的出口。
根据图示在图3中的另一备选的实施例,间隔物7包括分离的多个柱13(例如四个),柱13介于芯片3的面5的外围区域的四个角和芯片2之间。柱13之间的空间形成出口。如前文,这些柱13仅被粘接地结合在芯片2的面4上。
根据另一备选的实施例,替代被粘接地结合在芯片2的面4上,间隔环8或柱13可以被粘接地结合第二芯片3的面5,而不附接到芯片2的面4。
如图1和2中图示,堆叠1被布置在包封封装体14内部,以便构成电子器件15。
封装体14包括支撑板16,芯片2的在其面4另一侧的面通过粘接剂层16固定在支撑板16上。该支撑板16包括贯通装置,用于着眼于堆叠1的外部电连接的电连接17。
芯片3通过电连接线18被连接到芯片2,并且芯片2由电连接线19被连接到电连接装置17。
封装体14还包括帽20,帽20以一定距离覆盖堆叠1和电连接线18和19,并且帽20的边缘被固定在支撑板16的外围上。
根据一个示例性实施例,芯片3可以包括在其面5的另一侧上的前部面中的压力传感器21,并且芯片2可以包括用于处理来自于压力传感器21的信号的装置。
帽20可以具有贯通孔22,位于例如在压力传感器21的前面,以便压力传感器21通过该孔22承受封装体14之外的压力。
此外,根据一个备选的实施例,封装体可以被部分地填充有包封胶体,芯片3和线18和19被嵌入包封胶体中以便它们被保护,尤其防止氧化。期望的是该胶体没有到达封装体14的前壁,贯通前壁形成有孔22。
根据一个备选的实施例,胶体可以通过孔22被引入到封装体14中。根据一个备选的实施例,封装体14可以包括外围壁和包括孔22的封盖。在这种情况下,该外围壁将首先被安装,随后胶体将被引入到由该外围壁限定的空间中,随后封盖将被安装在外围壁上,封盖并不与胶体的表面发生接触。
以上已经描述的内容的结果是芯片3经受的机械应力可以非常受限或甚至不存在,当该芯片3包括压力传感器21时这是相当有益的。
本发明不限于上文描述的示例。备选的实施例在不偏离本发明的范围的情况下是可能的。
Claims (20)
1.一种集成电路芯片的堆叠,包括:
第一集成电路芯片和第二集成电路芯片,分别具有彼此相距一定距离定位的相对的第一面和第二面;
间隔物,介于所述第二集成电路芯片的所述第二面的外围区域的一部分与所述第一集成电路芯片的所述第一面之间,所述间隔物与所述第一集成电路芯片的所述第一面以及所述第二集成电路芯片的所述第二面的所述外围区域的所述一部分竖直对准;
第一粘接剂,将所述间隔物仅附接至所述第一面和所述第二面中的一个面;以及
第二粘接剂,介于所述第二集成电路芯片的所述第二面的中心区域与所述第一集成电路芯片的所述第一面之间,以将所述第一集成电路芯片与所述第二集成电路芯片彼此固定,其中所述第二粘结剂与所述间隔物分离而不与所述间隔物接触。
2.根据权利要求1所述的堆叠,还包括电连接线,其连接在所述第一集成电路芯片和所述第二集成电路芯片之间。
3.根据权利要求1所述的堆叠,其中所述间隔物从所述中心区域形成至少一个出口。
4.根据权利要求1所述的堆叠,其中所述间隔物包括间隔环。
5.根据权利要求4所述的堆叠,其中所述间隔环包括从所述中心区域形成出口的至少一个槽。
6.根据权利要求1所述的堆叠,其中所述间隔物包括开口的间隔环。
7.根据权利要求1所述的堆叠,其中所述间隔物包括彼此分离的多个柱,每个柱通过所述第一粘接剂被固定至所述第一面和所述第二面中的仅一个面。
8.根据权利要求1所述的堆叠,其中所述第二粘接剂包括至少一滴粘接剂材料。
9.根据权利要求1所述的堆叠,其中所述第二集成电路芯片包括压力传感器。
10.根据权利要求1所述的堆叠,还包括具有至少一个贯通开口的包封封装体。
11.根据权利要求10所述的堆叠,其中所述包封封装体至少部分地填充有胶体。
12.一种具有集成电路芯片的堆叠的装置,包括:
第一集成电路芯片,具有顶表面;
第二集成电路芯片,具有底表面;
其中所述顶表面面向所述底表面;
间隔物,被定位在所述顶表面与所述底表面之间,所述间隔物与所述顶表面和所述底表面竖直对准;其中所述间隔物被永久附接至所述顶表面和所述底表面中的仅一个表面;
粘接剂材料,被配置为出于将所述第一集成电路芯片永久附接至所述第二集成电路芯片的目的而单独地接触所述顶表面和所述底表面。
13.根据权利要求12所述的装置,其中如果所述间隔物被永久附接至所述顶表面,则所述底表面不被永久附接至所述间隔物。
14.根据权利要求12所述的装置,其中所述间隔物是间隔环。
15.根据权利要求14所述的装置,其中所述间隔环包括出口槽。
16.根据权利要求12所述的装置,还包括支撑衬底,其中所述第一集成电路芯片被安装在所述支撑衬底上并且电连接至所述支撑衬底。
17.根据权利要求16所述的装置,其中所述第二集成电路芯片电连接至所述第一集成电路芯片。
18.根据权利要求12所述的装置,其中所述间隔物包括多个间隔柱。
19.一种集成电路芯片的堆叠,包括:
第一集成电路芯片和第二集成电路芯片,分别具有相对的第一面和第二面;
间隔物,介于所述第二集成电路芯片的所述第二面和所述第一集成电路芯片的所述第一面之间;
粘结剂,用于将所述第二集成电路芯片的所述第二面固定至所述第一集成电路芯片的所述第一面,而所述粘结剂不与所述间隔物接触;
其中所述间隔物与所述第一面和所述第二面中的一个面直接接触,但不附接至所述一个面,并且所述间隔物附接至所述第一面和所述第二面中的另一个面。
20.根据权利要求19所述的堆叠,还包括另外的粘结剂,其配置成将所述间隔物附接至所述第一面和所述第二面中的所述另一个面。
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CN204732405U (zh) * | 2014-06-12 | 2015-10-28 | 意法半导体(格勒诺布尔2)公司 | 集成电路芯片的堆叠和电子装置 |
FR3029013A1 (fr) | 2014-11-21 | 2016-05-27 | Stmicroelectronics (Grenoble 2) Sas | Dispositif electronique comprenant des puces empilees |
US9773740B2 (en) | 2014-11-26 | 2017-09-26 | Stmicroelectronics (Grenoble 2) Sas | Stacked electronic device including a protective wafer bonded to a chip by an infused adhesive |
DE102016115197A1 (de) * | 2016-08-16 | 2018-02-22 | Endress + Hauser Gmbh + Co. Kg | Füllkörper zur Reduktion eines Volumens einer Druckmesskammer |
KR102511832B1 (ko) * | 2016-08-26 | 2023-03-20 | 삼성전자주식회사 | 반도체 패키지 장치 |
CN106531694B (zh) * | 2016-12-06 | 2020-04-21 | 歌尔股份有限公司 | 一种环境传感器 |
JP6669104B2 (ja) * | 2017-03-03 | 2020-03-18 | 株式会社デンソー | 半導体装置 |
US11258229B2 (en) * | 2019-08-16 | 2022-02-22 | Cisco Technology, Inc. | Thermal gel application on electronic and optical components |
CN111987069A (zh) * | 2020-08-28 | 2020-11-24 | 西安微电子技术研究所 | 一种锁胶阵列引线框架及其在芯片封装件中的应用 |
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